2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/ioport.h>
22 #include <linux/pci.h>
23 #include <linux/tty.h>
26 #include <asm/bootinfo.h>
28 #include <asm/mips-boards/generic.h>
29 #include <asm/mips-boards/prom.h>
30 #include <asm/mips-boards/malta.h>
31 #include <asm/mips-boards/maltaint.h>
34 #include <asm/traps.h>
36 #include <linux/console.h>
39 extern void mips_reboot_setup(void);
40 extern void mips_time_init(void);
41 extern void mips_timer_setup(struct irqaction
*irq
);
42 extern unsigned long mips_rtc_get_time(void);
45 extern void kgdb_config(void);
48 struct resource standard_io_resources
[] = {
49 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY
},
50 { "timer", 0x40, 0x5f, IORESOURCE_BUSY
},
51 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY
},
52 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY
},
53 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY
},
56 const char *get_system_type(void)
61 #ifdef CONFIG_BLK_DEV_FD
62 void __init
fd_activate(void)
65 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
67 * Done by YAMON 2.00 onwards
69 /* Entering config state. */
70 SMSC_WRITE(SMSC_CONFIG_ENTER
, SMSC_CONFIG_REG
);
72 /* Activate floppy controller. */
73 SMSC_WRITE(SMSC_CONFIG_DEVNUM
, SMSC_CONFIG_REG
);
74 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY
, SMSC_DATA_REG
);
75 SMSC_WRITE(SMSC_CONFIG_ACTIVATE
, SMSC_CONFIG_REG
);
76 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE
, SMSC_DATA_REG
);
78 /* Exit config state. */
79 SMSC_WRITE(SMSC_CONFIG_EXIT
, SMSC_CONFIG_REG
);
83 static int __init
malta_setup(void)
87 /* Request I/O space for devices used on the Malta board. */
88 for (i
= 0; i
< ARRAY_SIZE(standard_io_resources
); i
++)
89 request_resource(&ioport_resource
, standard_io_resources
+i
);
92 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
100 if ((mips_revision_corid
== MIPS_REVISION_CORID_BONITO64
) ||
101 (mips_revision_corid
== MIPS_REVISION_CORID_CORE_20K
) ||
102 (mips_revision_corid
== MIPS_REVISION_CORID_CORE_EMUL_BON
)) {
105 argptr
= prom_getcmdline();
106 if (strstr(argptr
, "debug")) {
107 BONITO_BONGENCFG
|= BONITO_BONGENCFG_DEBUGMODE
;
108 printk ("Enabled Bonito debug mode\n");
111 BONITO_BONGENCFG
&= ~BONITO_BONGENCFG_DEBUGMODE
;
113 #ifdef CONFIG_DMA_COHERENT
114 if (BONITO_PCICACHECTRL
& BONITO_PCICACHECTRL_CPUCOH_PRES
) {
115 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_CPUCOH_EN
;
116 printk("Enabled Bonito CPU coherency\n");
118 argptr
= prom_getcmdline();
119 if (strstr(argptr
, "iobcuncached")) {
120 BONITO_PCICACHECTRL
&= ~BONITO_PCICACHECTRL_IOBCCOH_EN
;
121 BONITO_PCIMEMBASECFG
= BONITO_PCIMEMBASECFG
&
122 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
123 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
124 printk("Disabled Bonito IOBC coherency\n");
127 BONITO_PCICACHECTRL
|= BONITO_PCICACHECTRL_IOBCCOH_EN
;
128 BONITO_PCIMEMBASECFG
|=
129 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
|
130 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
);
131 printk("Disabled Bonito IOBC coherency\n");
135 panic ("Hardware DMA cache coherency not supported\n");
139 #ifdef CONFIG_DMA_COHERENT
141 panic ("Hardware DMA cache coherency not supported\n");
145 #ifdef CONFIG_BLK_DEV_IDE
146 /* Check PCI clock */
148 int jmpr
= (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG
, sizeof(unsigned int))) >> 2) & 0x07;
149 static const int pciclocks
[] __initdata
= {
150 33, 20, 25, 30, 12, 16, 37, 10
152 int pciclock
= pciclocks
[jmpr
];
153 char *argptr
= prom_getcmdline();
155 if (pciclock
!= 33 && !strstr (argptr
, "idebus=")) {
156 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock
);
157 argptr
+= strlen(argptr
);
158 sprintf (argptr
, " idebus=%d", pciclock
);
159 if (pciclock
< 20 || pciclock
> 66)
160 printk ("WARNING: IDE timing calculations will be incorrect\n");
164 #ifdef CONFIG_BLK_DEV_FD
168 #if defined(CONFIG_VGA_CONSOLE)
169 screen_info
= (struct screen_info
) {
170 0, 25, /* orig-x, orig-y */
172 0, /* orig-video-page */
173 0, /* orig-video-mode */
174 80, /* orig-video-cols */
175 0,0,0, /* ega_ax, ega_bx, ega_cx */
176 25, /* orig-video-lines */
177 VIDEO_TYPE_VGAC
, /* orig-video-isVGA */
178 16 /* orig-video-points */
184 board_time_init
= mips_time_init
;
185 board_timer_setup
= mips_timer_setup
;
186 rtc_get_time
= mips_rtc_get_time
;
191 early_initcall(malta_setup
);