arch/mips/mips-boards/generic/pci.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  *  This program is free software; you can distribute it and/or modify it
   6  *  under the terms of the GNU General Public License (Version 2) as
   7  *  published by the Free Software Foundation.
   8  *
   9  *  This program is distributed in the hope it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  *  for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License along
  15  *  with this program; if not, write to the Free Software Foundation, Inc.,
  16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17  *
  18  * MIPS boards specific PCI support.
  19  */
  20 #include <linux/config.h>
  21 #include <linux/types.h>
  22 #include <linux/pci.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25
  26 #include <asm/mips-boards/generic.h>
  27 #include <asm/pci_channel.h>
  28 #include <asm/gt64120.h>
  29 #include <asm/mips-boards/bonito64.h>
  30 #include <asm/mips-boards/msc01_pci.h>
  31 #ifdef CONFIG_MIPS_MALTA
  32 #include <asm/mips-boards/malta.h>
  33 #endif
  34
  35 static struct resource bonito64_mem_resource = {
  36         .name   = "Bonito PCI MEM",
  37         .start  = 0x10000000UL,
  38         .end    = 0x1bffffffUL,
  39         .flags  = IORESOURCE_MEM,
  40 };
  41
  42 static struct resource bonito64_io_resource = {
  43         .name   = "Bonito IO MEM",
  44         .start  = 0x00002000UL, /* avoid conflicts with YAMON allocated I/O addresses */
  45         .end    = 0x000fffffUL,
  46         .flags  = IORESOURCE_IO,
  47 };
  48
  49 static struct resource gt64120_mem_resource = {
  50         .name   = "GT64120 PCI MEM",
  51         .start  = 0x10000000UL,
  52         .end    = 0x1bdfffffUL,
  53         .flags  = IORESOURCE_MEM,
  54 };
  55
  56 static struct resource gt64120_io_resource = {
  57         .name   = "GT64120 IO MEM",
  58 #ifdef CONFIG_MIPS_ATLAS
  59         .start  = 0x18000000UL,
  60         .end    = 0x181fffffUL,
  61 #endif
  62 #ifdef CONFIG_MIPS_MALTA
  63         .start  = 0x00002000UL,
  64         .end    = 0x001fffffUL,
  65 #endif
  66         .flags  = IORESOURCE_IO,
  67 };
  68
  69 static struct resource msc_mem_resource = {
  70         .name   = "MSC PCI MEM",
  71         .start  = 0x10000000UL,
  72         .end    = 0x1fffffffUL,
  73         .flags  = IORESOURCE_MEM,
  74 };
  75
  76 static struct resource msc_io_resource = {
  77         .name   = "MSC IO MEM",
  78         .start  = 0x00002000UL,
  79         .end    = 0x007fffffUL,
  80         .flags  = IORESOURCE_IO,
  81 };
  82
  83 extern struct pci_ops bonito64_pci_ops;
  84 extern struct pci_ops gt64120_pci_ops;
  85 extern struct pci_ops msc_pci_ops;
  86
  87 static struct pci_controller bonito64_controller = {
  88         .pci_ops        = &bonito64_pci_ops,
  89         .io_resource    = &bonito64_io_resource,
  90         .mem_resource   = &bonito64_mem_resource,
  91         .mem_offset     = 0x10000000UL,
  92         .io_offset      = 0x00000000UL,
  93 };
  94
  95 static struct pci_controller gt64120_controller = {
  96         .pci_ops        = &gt64120_pci_ops,
  97         .io_resource    = &gt64120_io_resource,
  98         .mem_resource   = &gt64120_mem_resource,
  99         .mem_offset     = 0x00000000UL,
 100         .io_offset      = 0x00000000UL,
 101 };
 102
 103 static struct pci_controller  msc_controller = {
 104         .pci_ops        = &msc_pci_ops,
 105         .io_resource    = &msc_io_resource,
 106         .mem_resource   = &msc_mem_resource,
 107         .mem_offset     = 0x10000000UL,
 108         .io_offset      = 0x00000000UL,
 109 };
 110
 111 static int __init pcibios_init(void)
 112 {
 113         struct pci_controller *controller;
 114
 115         switch (mips_revision_corid) {
 116         case MIPS_REVISION_CORID_QED_RM5261:
 117         case MIPS_REVISION_CORID_CORE_LV:
 118         case MIPS_REVISION_CORID_CORE_FPGA:
 119         case MIPS_REVISION_CORID_CORE_FPGAR2:
 120                 /*
 121                  * Due to a bug in the Galileo system controller, we need
 122                  * to setup the PCI BAR for the Galileo internal registers.
 123                  * This should be done in the bios/bootprom and will be
 124                  * fixed in a later revision of YAMON (the MIPS boards
 125                  * boot prom).
 126                  */
 127                 GT_WRITE(GT_PCI0_CFGADDR_OFS,
 128                          (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
 129                          (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
 130                          (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
 131                          ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
 132                          GT_PCI0_CFGADDR_CONFIGEN_BIT );
 133
 134                 /* Perform the write */
 135                 GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
 136
 137                 controller = &gt64120_controller;
 138                 break;
 139
 140         case MIPS_REVISION_CORID_BONITO64:
 141         case MIPS_REVISION_CORID_CORE_20K:
 142         case MIPS_REVISION_CORID_CORE_EMUL_BON:
 143                 controller = &bonito64_controller;
 144                 break;
 145
 146         case MIPS_REVISION_CORID_CORE_MSC:
 147         case MIPS_REVISION_CORID_CORE_FPGA2:
 148         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 149                 controller = &msc_controller;
 150                 break;
 151         default:
 152                 return 1;
 153         }
 154
 155         ioport_resource.end = controller->io_resource->end;
 156
 157         register_pci_controller (controller);
 158
 159         return 0;
 160 }
 161
 162 early_initcall(pcibios_init);