2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
14 #include <linux/config.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
24 #include <asm/bootinfo.h>
25 #include <asm/branch.h>
26 #include <asm/break.h>
29 #include <asm/module.h>
30 #include <asm/pgtable.h>
31 #include <asm/ptrace.h>
32 #include <asm/sections.h>
33 #include <asm/system.h>
34 #include <asm/tlbdebug.h>
35 #include <asm/traps.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/watch.h>
39 #include <asm/types.h>
41 extern asmlinkage
void handle_mod(void);
42 extern asmlinkage
void handle_tlbl(void);
43 extern asmlinkage
void handle_tlbs(void);
44 extern asmlinkage
void __xtlb_mod(void);
45 extern asmlinkage
void __xtlb_tlbl(void);
46 extern asmlinkage
void __xtlb_tlbs(void);
47 extern asmlinkage
void handle_adel(void);
48 extern asmlinkage
void handle_ades(void);
49 extern asmlinkage
void handle_ibe(void);
50 extern asmlinkage
void handle_dbe(void);
51 extern asmlinkage
void handle_sys(void);
52 extern asmlinkage
void handle_bp(void);
53 extern asmlinkage
void handle_ri(void);
54 extern asmlinkage
void handle_cpu(void);
55 extern asmlinkage
void handle_ov(void);
56 extern asmlinkage
void handle_tr(void);
57 extern asmlinkage
void handle_fpe(void);
58 extern asmlinkage
void handle_mdmx(void);
59 extern asmlinkage
void handle_watch(void);
60 extern asmlinkage
void handle_mcheck(void);
61 extern asmlinkage
void handle_reserved(void);
63 extern int fpu_emulator_cop1Handler(int xcptno
, struct pt_regs
*xcp
,
64 struct mips_fpu_soft_struct
*ctx
);
66 void (*board_be_init
)(void);
67 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
70 * These constant is for searching for possible module text segments.
71 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
73 #define MODULE_RANGE (8*1024*1024)
76 * This routine abuses get_user()/put_user() to reference pointers
77 * with at least a bit of error checking ...
79 void show_stack(struct task_struct
*task
, unsigned long *sp
)
81 const int field
= 2 * sizeof(unsigned long);
85 sp
= sp
? sp
: (unsigned long *) &sp
;
89 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
90 if (i
&& ((i
% (64 / field
)) == 0))
97 if (__get_user(stackdata
, sp
++)) {
98 printk(" (Bad stack address)");
102 printk(" %0*lx", field
, stackdata
);
108 void show_trace(struct task_struct
*task
, unsigned long *stack
)
110 const int field
= 2 * sizeof(unsigned long);
114 stack
= (unsigned long*)&stack
;
116 printk("Call Trace:");
117 #ifdef CONFIG_KALLSYMS
120 while (!kstack_end(stack
)) {
122 if (__kernel_text_address(addr
)) {
123 printk(" [<%0*lx>] ", field
, addr
);
124 print_symbol("%s\n", addr
);
131 * The architecture-independent dump_stack generator
133 void dump_stack(void)
137 show_trace(current
, &stack
);
140 EXPORT_SYMBOL(dump_stack
);
142 void show_code(unsigned int *pc
)
148 for(i
= -3 ; i
< 6 ; i
++) {
150 if (__get_user(insn
, pc
+ i
)) {
151 printk(" (Bad address in epc)\n");
154 printk("%c%08x%c", (i
?' ':'<'), insn
, (i
?' ':'>'));
158 void show_regs(struct pt_regs
*regs
)
160 const int field
= 2 * sizeof(unsigned long);
161 unsigned int cause
= regs
->cp0_cause
;
164 printk("Cpu %d\n", smp_processor_id());
167 * Saved main processor registers
169 for (i
= 0; i
< 32; ) {
173 printk(" %0*lx", field
, 0UL);
174 else if (i
== 26 || i
== 27)
175 printk(" %*s", field
, "");
177 printk(" %0*lx", field
, regs
->regs
[i
]);
184 printk("Hi : %0*lx\n", field
, regs
->hi
);
185 printk("Lo : %0*lx\n", field
, regs
->lo
);
188 * Saved cp0 registers
190 printk("epc : %0*lx ", field
, regs
->cp0_epc
);
191 print_symbol("%s ", regs
->cp0_epc
);
192 printk(" %s\n", print_tainted());
193 printk("ra : %0*lx ", field
, regs
->regs
[31]);
194 print_symbol("%s\n", regs
->regs
[31]);
196 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
198 if (regs
->cp0_status
& ST0_KX
)
200 if (regs
->cp0_status
& ST0_SX
)
202 if (regs
->cp0_status
& ST0_UX
)
204 switch (regs
->cp0_status
& ST0_KSU
) {
209 printk("SUPERVISOR ");
218 if (regs
->cp0_status
& ST0_ERL
)
220 if (regs
->cp0_status
& ST0_EXL
)
222 if (regs
->cp0_status
& ST0_IE
)
226 printk("Cause : %08x\n", cause
);
228 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
229 if (1 <= cause
&& cause
<= 5)
230 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
232 printk("PrId : %08x\n", read_c0_prid());
235 void show_registers(struct pt_regs
*regs
)
239 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
240 current
->comm
, current
->pid
, current_thread_info(), current
);
241 show_stack(current
, (long *) regs
->regs
[29]);
242 show_trace(current
, (long *) regs
->regs
[29]);
243 show_code((unsigned int *) regs
->cp0_epc
);
247 static spinlock_t die_lock
= SPIN_LOCK_UNLOCKED
;
249 NORET_TYPE
void __die(const char * str
, struct pt_regs
* regs
,
250 const char * file
, const char * func
, unsigned long line
)
252 static int die_counter
;
255 spin_lock_irq(&die_lock
);
258 printk(" in %s:%s, line %ld", file
, func
, line
);
259 printk("[#%d]:\n", ++die_counter
);
260 show_registers(regs
);
261 spin_unlock_irq(&die_lock
);
265 void __die_if_kernel(const char * str
, struct pt_regs
* regs
,
266 const char * file
, const char * func
, unsigned long line
)
268 if (!user_mode(regs
))
269 __die(str
, regs
, file
, func
, line
);
272 extern const struct exception_table_entry __start___dbe_table
[];
273 extern const struct exception_table_entry __stop___dbe_table
[];
275 void __declare_dbe_table(void)
277 __asm__
__volatile__(
278 ".section\t__dbe_table,\"a\"\n\t"
283 /* Given an address, look for it in the exception tables. */
284 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
286 const struct exception_table_entry
*e
;
288 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
290 e
= search_module_dbetables(addr
);
294 asmlinkage
void do_be(struct pt_regs
*regs
)
296 const int field
= 2 * sizeof(unsigned long);
297 const struct exception_table_entry
*fixup
= NULL
;
298 int data
= regs
->cp0_cause
& 4;
299 int action
= MIPS_BE_FATAL
;
301 /* XXX For now. Fixme, this searches the wrong table ... */
302 if (data
&& !user_mode(regs
))
303 fixup
= search_dbe_tables(exception_epc(regs
));
306 action
= MIPS_BE_FIXUP
;
308 if (board_be_handler
)
309 action
= board_be_handler(regs
, fixup
!= 0);
312 case MIPS_BE_DISCARD
:
316 regs
->cp0_epc
= fixup
->nextinsn
;
325 * Assume it would be too dangerous to continue ...
327 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
328 data
? "Data" : "Instruction",
329 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
330 die_if_kernel("Oops", regs
);
331 force_sig(SIGBUS
, current
);
334 static inline int get_insn_opcode(struct pt_regs
*regs
, unsigned int *opcode
)
338 epc
= (unsigned int *) regs
->cp0_epc
+
339 ((regs
->cp0_cause
& CAUSEF_BD
) != 0);
340 if (!get_user(*opcode
, epc
))
343 force_sig(SIGSEGV
, current
);
351 #define OPCODE 0xfc000000
352 #define BASE 0x03e00000
353 #define RT 0x001f0000
354 #define OFFSET 0x0000ffff
355 #define LL 0xc0000000
356 #define SC 0xe0000000
359 * The ll_bit is cleared by r*_switch.S
362 unsigned long ll_bit
;
364 static struct task_struct
*ll_task
= NULL
;
366 static inline void simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
368 unsigned long value
, *vaddr
;
373 * analyse the ll instruction that just caused a ri exception
374 * and put the referenced address to addr.
377 /* sign extend offset */
378 offset
= opcode
& OFFSET
;
382 vaddr
= (unsigned long *)((long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
384 if ((unsigned long)vaddr
& 3) {
388 if (get_user(value
, vaddr
)) {
393 if (ll_task
== NULL
|| ll_task
== current
) {
400 regs
->regs
[(opcode
& RT
) >> 16] = value
;
402 compute_return_epc(regs
);
406 force_sig(signal
, current
);
409 static inline void simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
411 unsigned long *vaddr
, reg
;
416 * analyse the sc instruction that just caused a ri exception
417 * and put the referenced address to addr.
420 /* sign extend offset */
421 offset
= opcode
& OFFSET
;
425 vaddr
= (unsigned long *)((long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
426 reg
= (opcode
& RT
) >> 16;
428 if ((unsigned long)vaddr
& 3) {
432 if (ll_bit
== 0 || ll_task
!= current
) {
434 compute_return_epc(regs
);
438 if (put_user(regs
->regs
[reg
], vaddr
)) {
445 compute_return_epc(regs
);
449 force_sig(signal
, current
);
453 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
454 * opcodes are supposed to result in coprocessor unusable exceptions if
455 * executed on ll/sc-less processors. That's the theory. In practice a
456 * few processors such as NEC's VR4100 throw reserved instruction exceptions
457 * instead, so we're doing the emulation thing in both exception handlers.
459 static inline int simulate_llsc(struct pt_regs
*regs
)
463 if (unlikely(get_insn_opcode(regs
, &opcode
)))
466 if ((opcode
& OPCODE
) == LL
) {
467 simulate_ll(regs
, opcode
);
470 if ((opcode
& OPCODE
) == SC
) {
471 simulate_sc(regs
, opcode
);
475 return -EFAULT
; /* Strange things going on ... */
478 asmlinkage
void do_ov(struct pt_regs
*regs
)
482 info
.si_code
= FPE_INTOVF
;
483 info
.si_signo
= SIGFPE
;
485 info
.si_addr
= (void *)regs
->cp0_epc
;
486 force_sig_info(SIGFPE
, &info
, current
);
490 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
492 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
494 if (fcr31
& FPU_CSR_UNI_X
) {
498 * Unimplemented operation exception. If we've got the full
499 * software emulator on-board, let's use it...
501 * Force FPU to dump state into task/thread context. We're
502 * moving a lot of data here for what is probably a single
503 * instruction, but the alternative is to pre-decode the FP
504 * register operands before invoking the emulator, which seems
505 * a bit extreme for what should be an infrequent event.
509 /* Run the emulator */
510 sig
= fpu_emulator_cop1Handler (0, regs
,
511 ¤t
->thread
.fpu
.soft
);
514 * We can't allow the emulated instruction to leave any of
515 * the cause bit set in $fcr31.
517 current
->thread
.fpu
.soft
.fcr31
&= ~FPU_CSR_ALL_X
;
519 /* Restore the hardware register state */
522 /* If something went wrong, signal */
524 force_sig(sig
, current
);
529 force_sig(SIGFPE
, current
);
532 asmlinkage
void do_bp(struct pt_regs
*regs
)
534 unsigned int opcode
, bcode
;
537 die_if_kernel("Break instruction in kernel code", regs
);
539 if (get_insn_opcode(regs
, &opcode
))
543 * There is the ancient bug in the MIPS assemblers that the break
544 * code starts left to bit 16 instead to bit 6 in the opcode.
545 * Gas is bug-compatible, but not always, grrr...
546 * We handle both cases with a simple heuristics. --macro
548 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
549 if (bcode
< (1 << 10))
553 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
554 * insns, even for break codes that indicate arithmetic failures.
556 * But should we continue the brokenness??? --macro
559 case BRK_OVERFLOW
<< 10:
560 case BRK_DIVZERO
<< 10:
561 if (bcode
== (BRK_DIVZERO
<< 10))
562 info
.si_code
= FPE_INTDIV
;
564 info
.si_code
= FPE_INTOVF
;
565 info
.si_signo
= SIGFPE
;
567 info
.si_addr
= (void *)regs
->cp0_epc
;
568 force_sig_info(SIGFPE
, &info
, current
);
571 force_sig(SIGTRAP
, current
);
575 asmlinkage
void do_tr(struct pt_regs
*regs
)
577 unsigned int opcode
, tcode
= 0;
580 die_if_kernel("Trap instruction in kernel code", regs
);
582 if (get_insn_opcode(regs
, &opcode
))
585 /* Immediate versions don't provide a code. */
586 if (!(opcode
& OPCODE
))
587 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
590 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
591 * insns, even for trap codes that indicate arithmetic failures.
593 * But should we continue the brokenness??? --macro
598 if (tcode
== BRK_DIVZERO
)
599 info
.si_code
= FPE_INTDIV
;
601 info
.si_code
= FPE_INTOVF
;
602 info
.si_signo
= SIGFPE
;
604 info
.si_addr
= (void *)regs
->cp0_epc
;
605 force_sig_info(SIGFPE
, &info
, current
);
608 force_sig(SIGTRAP
, current
);
612 asmlinkage
void do_ri(struct pt_regs
*regs
)
614 die_if_kernel("Reserved instruction in kernel code", regs
);
617 if (!simulate_llsc(regs
))
620 force_sig(SIGILL
, current
);
623 asmlinkage
void do_cpu(struct pt_regs
*regs
)
627 die_if_kernel("do_cpu invoked from kernel context!", regs
);
629 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
636 if (!simulate_llsc(regs
))
642 if (current
->used_math
) { /* Using the FPU again. */
644 } else { /* First time FPU user. */
646 current
->used_math
= 1;
650 int sig
= fpu_emulator_cop1Handler(0, regs
,
651 ¤t
->thread
.fpu
.soft
);
653 force_sig(sig
, current
);
663 force_sig(SIGILL
, current
);
666 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
668 force_sig(SIGILL
, current
);
671 asmlinkage
void do_watch(struct pt_regs
*regs
)
674 * We use the watch exception where available to detect stack
679 panic("Caught WATCH exception - probably caused by stack overflow.");
682 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
687 * Some chips may have other causes of machine check (e.g. SB1
690 panic("Caught Machine Check exception - %scaused by multiple "
691 "matching entries in the TLB.",
692 (regs
->cp0_status
& ST0_TS
) ? "" : "not ");
695 asmlinkage
void do_reserved(struct pt_regs
*regs
)
698 * Game over - no way to handle this if it ever occurs. Most probably
699 * caused by a new unknown cpu type or after another deadly
700 * hard/software error.
703 panic("Caught reserved exception %ld - should not happen.",
704 (regs
->cp0_cause
& 0x7f) >> 2);
708 * Some MIPS CPUs can enable/disable for cache parity detection, but do
711 static inline void parity_protection_init(void)
713 switch (current_cpu_data
.cputype
) {
715 /* 24K cache parity not currently implemented in FPGA */
716 printk(KERN_INFO
"Disable cache parity protection for "
718 write_c0_ecc(read_c0_ecc() & ~0x80000000);
721 /* Set the PE bit (bit 31) in the c0_ecc register. */
722 printk(KERN_INFO
"Enable cache parity protection for "
723 "MIPS 5KC/24K CPUs.\n");
724 write_c0_ecc(read_c0_ecc() | 0x80000000);
728 /* Clear the DE bit (bit 16) in the c0_status register. */
729 printk(KERN_INFO
"Enable cache parity protection for "
730 "MIPS 20KC/25KF CPUs.\n");
731 clear_c0_status(ST0_DE
);
738 asmlinkage
void cache_parity_error(void)
740 const int field
= 2 * sizeof(unsigned long);
741 unsigned int reg_val
;
743 /* For the moment, report the problem and hang. */
744 printk("Cache error exception:\n");
745 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
746 reg_val
= read_c0_cacheerr();
747 printk("c0_cacheerr == %08x\n", reg_val
);
749 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
750 reg_val
& (1<<30) ? "secondary" : "primary",
751 reg_val
& (1<<31) ? "data" : "insn");
752 printk("Error bits: %s%s%s%s%s%s%s\n",
753 reg_val
& (1<<29) ? "ED " : "",
754 reg_val
& (1<<28) ? "ET " : "",
755 reg_val
& (1<<26) ? "EE " : "",
756 reg_val
& (1<<25) ? "EB " : "",
757 reg_val
& (1<<24) ? "EI " : "",
758 reg_val
& (1<<23) ? "E1 " : "",
759 reg_val
& (1<<22) ? "E0 " : "");
760 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
762 #if defined(CONFIG_CPU_MIPS32) || defined (CONFIG_CPU_MIPS64)
763 if (reg_val
& (1<<22))
764 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
766 if (reg_val
& (1<<23))
767 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
770 panic("Can't handle the cache error!");
774 * SDBBP EJTAG debug exception handler.
775 * We skip the instruction and return to the next instruction.
777 void ejtag_exception_handler(struct pt_regs
*regs
)
779 const int field
= 2 * sizeof(unsigned long);
780 unsigned long depc
, old_epc
;
783 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
784 depc
= read_c0_depc();
785 debug
= read_c0_debug();
786 printk("c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
787 if (debug
& 0x80000000) {
789 * In branch delay slot.
790 * We cheat a little bit here and use EPC to calculate the
791 * debug return address (DEPC). EPC is restored after the
794 old_epc
= regs
->cp0_epc
;
795 regs
->cp0_epc
= depc
;
796 __compute_return_epc(regs
);
797 depc
= regs
->cp0_epc
;
798 regs
->cp0_epc
= old_epc
;
804 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
805 write_c0_debug(debug
| 0x100);
810 * NMI exception handler.
812 void nmi_exception_handler(struct pt_regs
*regs
)
814 printk("NMI taken!!!!\n");
819 unsigned long exception_handlers
[32];
822 * As a side effect of the way this is implemented we're limited
823 * to interrupt handlers in the address range from
824 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
826 void *set_except_vector(int n
, void *addr
)
828 unsigned long handler
= (unsigned long) addr
;
829 unsigned long old_handler
= exception_handlers
[n
];
831 exception_handlers
[n
] = handler
;
832 if (n
== 0 && cpu_has_divec
) {
833 *(volatile u32
*)(CAC_BASE
+ 0x200) = 0x08000000 |
834 (0x03ffffff & (handler
>> 2));
835 flush_icache_range(CAC_BASE
+ 0x200, CAC_BASE
+ 0x204);
837 return (void *)old_handler
;
841 * This is used by native signal handling
843 asmlinkage
int (*save_fp_context
)(struct sigcontext
*sc
);
844 asmlinkage
int (*restore_fp_context
)(struct sigcontext
*sc
);
846 extern asmlinkage
int _save_fp_context(struct sigcontext
*sc
);
847 extern asmlinkage
int _restore_fp_context(struct sigcontext
*sc
);
849 extern asmlinkage
int fpu_emulator_save_context(struct sigcontext
*sc
);
850 extern asmlinkage
int fpu_emulator_restore_context(struct sigcontext
*sc
);
852 static inline void signal_init(void)
855 save_fp_context
= _save_fp_context
;
856 restore_fp_context
= _restore_fp_context
;
858 save_fp_context
= fpu_emulator_save_context
;
859 restore_fp_context
= fpu_emulator_restore_context
;
863 #ifdef CONFIG_MIPS32_COMPAT
866 * This is used by 32-bit signal stuff on the 64-bit kernel
868 asmlinkage
int (*save_fp_context32
)(struct sigcontext32
*sc
);
869 asmlinkage
int (*restore_fp_context32
)(struct sigcontext32
*sc
);
871 extern asmlinkage
int _save_fp_context32(struct sigcontext32
*sc
);
872 extern asmlinkage
int _restore_fp_context32(struct sigcontext32
*sc
);
874 extern asmlinkage
int fpu_emulator_save_context32(struct sigcontext32
*sc
);
875 extern asmlinkage
int fpu_emulator_restore_context32(struct sigcontext32
*sc
);
877 static inline void signal32_init(void)
880 save_fp_context32
= _save_fp_context32
;
881 restore_fp_context32
= _restore_fp_context32
;
883 save_fp_context32
= fpu_emulator_save_context32
;
884 restore_fp_context32
= fpu_emulator_restore_context32
;
889 extern void cpu_cache_init(void);
890 extern void tlb_init(void);
892 void __init
per_cpu_trap_init(void)
894 unsigned int cpu
= smp_processor_id();
896 /* Some firmware leaves the BEV flag set, clear it. */
897 clear_c0_status(ST0_CU1
|ST0_CU2
|ST0_CU3
|ST0_BEV
);
899 set_c0_status(ST0_CU0
|ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
);
902 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_IV
)
903 set_c0_status(ST0_XX
);
906 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
907 * interrupt processing overhead. Use it where available.
910 set_c0_cause(CAUSEF_IV
);
912 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
913 TLBMISS_HANDLER_SETUP();
915 atomic_inc(&init_mm
.mm_count
);
916 current
->active_mm
= &init_mm
;
918 enter_lazy_tlb(&init_mm
, current
);
924 void __init
trap_init(void)
926 extern char except_vec3_generic
, except_vec3_r4000
;
927 extern char except_vec_ejtag_debug
;
928 extern char except_vec4
;
934 * Copy the generic exception handlers to their final destination.
935 * This will be overriden later as suitable for a particular
938 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
941 * Setup default vectors
943 for (i
= 0; i
<= 31; i
++)
944 set_except_vector(i
, handle_reserved
);
947 * Copy the EJTAG debug exception vector handler code to it's final
951 memcpy((void *)(CAC_BASE
+ 0x300), &except_vec_ejtag_debug
, 0x80);
954 * Only some CPUs have the watch exceptions.
957 set_except_vector(23, handle_watch
);
960 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
961 * interrupt processing overhead. Use it where available.
964 memcpy((void *)(CAC_BASE
+ 0x200), &except_vec4
, 0x8);
967 * Some CPUs can enable/disable for cache parity detection, but does
970 parity_protection_init();
973 * The Data Bus Errors / Instruction Bus Errors are signaled
974 * by external hardware. Therefore these two exceptions
975 * may have board specific handlers.
981 set_except_vector(1, handle_mod
);
982 set_except_vector(2, handle_tlbl
);
983 set_except_vector(3, handle_tlbs
);
986 set_except_vector(1, __xtlb_mod
);
987 set_except_vector(2, __xtlb_tlbl
);
988 set_except_vector(3, __xtlb_tlbs
);
990 set_except_vector(4, handle_adel
);
991 set_except_vector(5, handle_ades
);
993 set_except_vector(6, handle_ibe
);
994 set_except_vector(7, handle_dbe
);
996 set_except_vector(8, handle_sys
);
997 set_except_vector(9, handle_bp
);
998 set_except_vector(10, handle_ri
);
999 set_except_vector(11, handle_cpu
);
1000 set_except_vector(12, handle_ov
);
1001 set_except_vector(13, handle_tr
);
1002 set_except_vector(22, handle_mdmx
);
1004 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1005 set_except_vector(15, handle_fpe
);
1008 set_except_vector(24, handle_mcheck
);
1011 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_r4000
, 0x80);
1012 else if (cpu_has_4kex
)
1013 memcpy((void *)(CAC_BASE
+ 0x180), &except_vec3_generic
, 0x80);
1015 memcpy((void *)(CAC_BASE
+ 0x080), &except_vec3_generic
, 0x80);
1017 if (current_cpu_data
.cputype
== CPU_R6000
||
1018 current_cpu_data
.cputype
== CPU_R6000A
) {
1020 * The R6000 is the only R-series CPU that features a machine
1021 * check exception (similar to the R4000 cache error) and
1022 * unaligned ldc1/sdc1 exception. The handlers have not been
1023 * written yet. Well, anyway there is no R6000 machine on the
1024 * current list of targets for Linux/MIPS.
1025 * (Duh, crap, there is someone with a tripple R6k machine)
1027 //set_except_vector(14, handle_mc);
1028 //set_except_vector(15, handle_ndc);
1032 #ifdef CONFIG_MIPS32_COMPAT
1036 flush_icache_range(CAC_BASE
, CAC_BASE
+ 0x400);