arch/mips/jmr3927/rbhma3100/irq.c

   1 /*
   2  * Copyright 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              ahennessy@mvista.com
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  *
  10  * Copyright (C) 2000-2001 Toshiba Corporation
  11  *
  12  *  This program is free software; you can redistribute  it and/or modify it
  13  *  under  the terms of  the GNU General  Public License as published by the
  14  *  Free Software Foundation;  either version 2 of the  License, or (at your
  15  *  option) any later version.
  16  *
  17  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  18  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  19  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  20  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  21  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  23  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  25  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  *  You should have received a copy of the  GNU General Public License along
  29  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  30  *  675 Mass Ave, Cambridge, MA 02139, USA.
  31  */
  32 #include <linux/config.h>
  33 #include <linux/init.h>
  34
  35 #include <linux/errno.h>
  36 #include <linux/irq.h>
  37 #include <linux/kernel_stat.h>
  38 #include <linux/signal.h>
  39 #include <linux/sched.h>
  40 #include <linux/types.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/ioport.h>
  43 #include <linux/timex.h>
  44 #include <linux/slab.h>
  45 #include <linux/random.h>
  46 #include <linux/smp.h>
  47 #include <linux/smp_lock.h>
  48
  49 #include <asm/bitops.h>
  50 #include <asm/io.h>
  51 #include <asm/mipsregs.h>
  52 #include <asm/system.h>
  53
  54 #include <asm/ptrace.h>
  55 #include <asm/processor.h>
  56 #include <asm/jmr3927/irq.h>
  57 #include <asm/debug.h>
  58 #include <asm/jmr3927/jmr3927.h>
  59
  60 #if JMR3927_IRQ_END > NR_IRQS
  61 #error JMR3927_IRQ_END > NR_IRQS
  62 #endif
  63
  64 struct tb_irq_space* tb_irq_spaces;
  65
  66 static int jmr3927_irq_base = -1;
  67
  68 #ifdef CONFIG_PCI
  69 static int jmr3927_gen_iack(void)
  70 {
  71         /* generate ACK cycle */
  72 #ifdef __BIG_ENDIAN
  73         return (tx3927_pcicptr->iiadp >> 24) & 0xff;
  74 #else
  75         return tx3927_pcicptr->iiadp & 0xff;
  76 #endif
  77 }
  78 #endif
  79
  80 extern asmlinkage void jmr3927_IRQ(void);
  81
  82 #define irc_dlevel      0
  83 #define irc_elevel      1
  84
  85 static unsigned char irc_level[TX3927_NUM_IR] = {
  86         5, 5, 5, 5, 5, 5,       /* INT[5:0] */
  87         7, 7,                   /* SIO */
  88         5, 5, 5, 0, 0,          /* DMA, PIO, PCI */
  89         6, 6, 6                 /* TMR */
  90 };
  91
  92 static inline void mask_irq(unsigned int irq_nr)
  93 {
  94         struct tb_irq_space* sp;
  95         for (sp = tb_irq_spaces; sp; sp = sp->next) {
  96                 if (sp->start_irqno <= irq_nr &&
  97                     irq_nr < sp->start_irqno + sp->nr_irqs) {
  98                         if (sp->mask_func)
  99                                 sp->mask_func(irq_nr - sp->start_irqno,
 100                                               sp->space_id);
 101                         break;
 102                 }
 103         }
 104 }
 105
 106 static inline void unmask_irq(unsigned int irq_nr)
 107 {
 108         struct tb_irq_space* sp;
 109         for (sp = tb_irq_spaces; sp; sp = sp->next) {
 110                 if (sp->start_irqno <= irq_nr &&
 111                     irq_nr < sp->start_irqno + sp->nr_irqs) {
 112                         if (sp->unmask_func)
 113                                 sp->unmask_func(irq_nr - sp->start_irqno,
 114                                                 sp->space_id);
 115                         break;
 116                 }
 117         }
 118 }
 119
 120 static void jmr3927_irq_disable(unsigned int irq_nr);
 121 static void jmr3927_irq_enable(unsigned int irq_nr);
 122
 123 static spinlock_t jmr3927_irq_lock = SPIN_LOCK_UNLOCKED;
 124
 125 static unsigned int jmr3927_irq_startup(unsigned int irq)
 126 {
 127         jmr3927_irq_enable(irq);
 128
 129         return 0;
 130 }
 131
 132 #define jmr3927_irq_shutdown    jmr3927_irq_disable
 133
 134 static void jmr3927_irq_ack(unsigned int irq)
 135 {
 136         if (irq == JMR3927_IRQ_IRC_TMR0) {
 137                 jmr3927_tmrptr->tisr = 0;       /* ack interrupt */
 138         }
 139
 140         jmr3927_irq_disable(irq);
 141 }
 142
 143 static void jmr3927_irq_end(unsigned int irq)
 144 {
 145         jmr3927_irq_enable(irq);
 146 }
 147
 148 static void jmr3927_irq_disable(unsigned int irq_nr)
 149 {
 150         unsigned long flags;
 151
 152         spinlock_irqsave(&jmr3927_irq_lock, flags);
 153         mask_irq(irq_nr);
 154         spinlock_irqrestore(&jmr3927_irq_lock, flags);
 155 }
 156
 157 static void jmr3927_irq_enable(unsigned int irq_nr)
 158 {
 159         unsigned long flags;
 160
 161         spinlock_irqsave(&jmr3927_irq_lock, flags);
 162         unmask_irq(irq_nr);
 163         spinlock_irqrestore(&jmr3927_irq_lock, flags);
 164 }
 165
 166 /*
 167  * CP0_STATUS is a thread's resource (saved/restored on context switch).
 168  * So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
 169  */
 170 static void mask_irq_isac(int irq_nr, int space_id)
 171 {
 172         /* 0: mask */
 173         unsigned char imask =
 174                 jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 175         unsigned int bit  = 1 << irq_nr;
 176         jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
 177         /* flush write buffer */
 178         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 179 }
 180 static void unmask_irq_isac(int irq_nr, int space_id)
 181 {
 182         /* 0: mask */
 183         unsigned char imask = jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
 184         unsigned int bit  = 1 << irq_nr;
 185         jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
 186         /* flush write buffer */
 187         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 188 }
 189
 190 static void mask_irq_ioc(int irq_nr, int space_id)
 191 {
 192         /* 0: mask */
 193         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 194         unsigned int bit = 1 << irq_nr;
 195         jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
 196         /* flush write buffer */
 197         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 198 }
 199 static void unmask_irq_ioc(int irq_nr, int space_id)
 200 {
 201         /* 0: mask */
 202         unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
 203         unsigned int bit = 1 << irq_nr;
 204         jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
 205         /* flush write buffer */
 206         (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 207 }
 208
 209 static void mask_irq_irc(int irq_nr, int space_id)
 210 {
 211         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 212         if (irq_nr & 1)
 213                 *ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
 214         else
 215                 *ilrp = (*ilrp & 0xff00) | irc_dlevel;
 216         /* update IRCSR */
 217         tx3927_ircptr->imr = 0;
 218         tx3927_ircptr->imr = irc_elevel;
 219 }
 220 static void unmask_irq_irc(int irq_nr, int space_id)
 221 {
 222         volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
 223         if (irq_nr & 1)
 224                 *ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
 225         else
 226                 *ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
 227         /* update IRCSR */
 228         tx3927_ircptr->imr = 0;
 229         tx3927_ircptr->imr = irc_elevel;
 230 }
 231
 232 struct tb_irq_space jmr3927_isac_irqspace = {
 233         .next = NULL,
 234         .start_irqno = JMR3927_IRQ_ISAC,
 235         nr_irqs : JMR3927_NR_IRQ_ISAC,
 236         .mask_func = mask_irq_isac,
 237         .unmask_func = unmask_irq_isac,
 238         .name = "ISAC",
 239         .space_id = 0,
 240         can_share : 0
 241 };
 242 struct tb_irq_space jmr3927_ioc_irqspace = {
 243         .next = NULL,
 244         .start_irqno = JMR3927_IRQ_IOC,
 245         nr_irqs : JMR3927_NR_IRQ_IOC,
 246         .mask_func = mask_irq_ioc,
 247         .unmask_func = unmask_irq_ioc,
 248         .name = "IOC",
 249         .space_id = 0,
 250         can_share : 1
 251 };
 252 struct tb_irq_space jmr3927_irc_irqspace = {
 253         .next = NULL,
 254         .start_irqno = JMR3927_IRQ_IRC,
 255         nr_irqs : JMR3927_NR_IRQ_IRC,
 256         .mask_func = mask_irq_irc,
 257         .unmask_func = unmask_irq_irc,
 258         .name = "on-chip",
 259         .space_id = 0,
 260         can_share : 0
 261 };
 262
 263 void jmr3927_spurious(struct pt_regs *regs)
 264 {
 265 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 266         tx_branch_likely_bug_fixup(regs);
 267 #endif
 268         printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
 269                regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
 270 }
 271
 272 void jmr3927_irc_irqdispatch(struct pt_regs *regs)
 273 {
 274         int irq;
 275
 276 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 277         tx_branch_likely_bug_fixup(regs);
 278 #endif
 279         if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
 280 #if 0
 281                 jmr3927_spurious(regs);
 282 #endif
 283                 return;
 284         }
 285         irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
 286
 287         do_IRQ(irq + JMR3927_IRQ_IRC, regs);
 288 }
 289
 290 static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 291 {
 292         unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
 293         int i;
 294
 295         for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
 296                 if (istat & (1 << i)) {
 297                         irq = JMR3927_IRQ_IOC + i;
 298                         do_IRQ(irq, regs);
 299                 }
 300         }
 301 }
 302
 303 static struct irqaction ioc_action = {
 304         jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
 305 };
 306
 307 static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 308 {
 309         unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
 310         int i;
 311
 312         for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
 313                 if (istat & (1 << i)) {
 314                         irq = JMR3927_IRQ_ISAC + i;
 315                         do_IRQ(irq, regs);
 316                 }
 317         }
 318 }
 319
 320 static struct irqaction isac_action = {
 321         jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
 322 };
 323
 324
 325 static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 326 {
 327         printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
 328 }
 329 static struct irqaction isaerr_action = {
 330         jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
 331 };
 332
 333 static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
 334 {
 335         printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
 336         printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
 337                tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
 338 }
 339 static struct irqaction pcierr_action = {
 340         jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
 341 };
 342
 343 int jmr3927_ether1_irq = 0;
 344
 345 void jmr3927_irq_init(u32 irq_base);
 346 void jmr3927_irq_setup(void)
 347 {
 348         /* look for io board's presence */
 349         int have_isac = jmr3927_have_isac();
 350
 351         /* Now, interrupt control disabled, */
 352         /* all IRC interrupts are masked, */
 353         /* all IRC interrupt mode are Low Active. */
 354
 355         if (have_isac) {
 356
 357                 /* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
 358                 /* temporary enable interrupt control */
 359                 tx3927_ircptr->cer = 1;
 360                 /* ETHER1 Int. Is High-Active. */
 361                 if (tx3927_ircptr->ssr & (1 << 0))
 362                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
 363 #if 0   /* INT3 may be asserted by ether0 (even after reboot...) */
 364                 else if (tx3927_ircptr->ssr & (1 << 3))
 365                         jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
 366 #endif
 367                 /* disable interrupt control */
 368                 tx3927_ircptr->cer = 0;
 369
 370                 /* Ether1: High Active */
 371                 if (jmr3927_ether1_irq) {
 372                         int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
 373                         tx3927_ircptr->cr[ether1_irc / 8] |=
 374                                 TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
 375                 }
 376         }
 377
 378         /* mask all IOC interrupts */
 379         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
 380         /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
 381         jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
 382
 383         if (have_isac) {
 384                 /* mask all ISAC interrupts */
 385                 jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
 386                 /* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
 387                 jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
 388         }
 389
 390         /* clear PCI Soft interrupts */
 391         jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
 392         /* clear PCI Reset interrupts */
 393         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 394
 395         /* enable interrupt control */
 396         tx3927_ircptr->cer = TX3927_IRCER_ICE;
 397         tx3927_ircptr->imr = irc_elevel;
 398
 399         jmr3927_irq_init(NR_ISA_IRQS);
 400
 401         set_except_vector(0, jmr3927_IRQ);
 402
 403         /* setup irq space */
 404         add_tb_irq_space(&jmr3927_isac_irqspace);
 405         add_tb_irq_space(&jmr3927_ioc_irqspace);
 406         add_tb_irq_space(&jmr3927_irc_irqspace);
 407
 408         /* setup IOC interrupt 1 (PCI, MODEM) */
 409         setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
 410
 411         if (have_isac) {
 412                 setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
 413                 setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
 414         }
 415
 416 #ifdef CONFIG_PCI
 417         setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
 418 #endif
 419
 420         /* enable all CPU interrupt bits. */
 421         set_c0_status(ST0_IM);  /* IE bit is still 0. */
 422 }
 423
 424 void (*irq_setup)(void);
 425
 426 void __init init_IRQ(void)
 427 {
 428
 429 #ifdef CONFIG_KGDB
 430         extern void breakpoint(void);
 431         extern void set_debug_traps(void);
 432
 433         puts("Wait for gdb client connection ...\n");
 434         set_debug_traps();
 435         breakpoint();
 436 #endif
 437
 438         /* invoke board-specific irq setup */
 439         irq_setup();
 440 }
 441
 442 static hw_irq_controller jmr3927_irq_controller = {
 443         "jmr3927_irq",
 444         jmr3927_irq_startup,
 445         jmr3927_irq_shutdown,
 446         jmr3927_irq_enable,
 447         jmr3927_irq_disable,
 448         jmr3927_irq_ack,
 449         jmr3927_irq_end,
 450 };
 451
 452 void jmr3927_irq_init(u32 irq_base)
 453 {
 454         u32 i;
 455
 456         init_generic_irq();
 457         for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
 458                 irq_desc[i].status = IRQ_DISABLED;
 459                 irq_desc[i].action = NULL;
 460                 irq_desc[i].depth = 1;
 461                 irq_desc[i].handler = &jmr3927_irq_controller;
 462         }
 463
 464         jmr3927_irq_base = irq_base;
 465 }
 466
 467 #ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
 468 static int tx_branch_likely_bug_count = 0;
 469 static int have_tx_branch_likely_bug = 0;
 470 void tx_branch_likely_bug_fixup(struct pt_regs *regs)
 471 {
 472         /* TX39/49-BUG: Under this condition, the insn in delay slot
 473            of the branch likely insn is executed (not nullified) even
 474            the branch condition is false. */
 475         if (!have_tx_branch_likely_bug)
 476                 return;
 477         if ((regs->cp0_epc & 0xfff) == 0xffc &&
 478             KSEGX(regs->cp0_epc) != KSEG0 &&
 479             KSEGX(regs->cp0_epc) != KSEG1) {
 480                 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
 481                 /* beql,bnel,blezl,bgtzl */
 482                 /* bltzl,bgezl,blezall,bgezall */
 483                 /* bczfl, bcztl */
 484                 if ((insn & 0xf0000000) == 0x50000000 ||
 485                     (insn & 0xfc0e0000) == 0x04020000 ||
 486                     (insn & 0xf3fe0000) == 0x41020000) {
 487                         regs->cp0_epc -= 4;
 488                         tx_branch_likely_bug_count++;
 489                         printk(KERN_INFO
 490                                "fix branch-likery bug in %s (insn %08x)\n",
 491                                current->comm, insn);
 492                 }
 493         }
 494 }
 495 #endif