arch/mips/ddb5xxx/ddb5476/setup.c

   1 /*
   2  *  arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
   3  *
   4  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
   5  *                     Sony Software Development Center Europe (SDCE), Brussels
   6  */
   7 #include <linux/config.h>
   8 #include <linux/init.h>
   9 #include <linux/kbd_ll.h>
  10 #include <linux/kernel.h>
  11 #include <linux/kdev_t.h>
  12 #include <linux/types.h>
  13 #include <linux/sched.h>
  14 #include <linux/pci.h>
  15
  16 #include <asm/addrspace.h>
  17 #include <asm/bcache.h>
  18 #include <asm/irq.h>
  19 #include <asm/reboot.h>
  20 #include <asm/gdb-stub.h>
  21 #include <asm/time.h>
  22 #include <asm/debug.h>
  23 #include <asm/traps.h>
  24
  25 #include <asm/ddb5xxx/ddb5xxx.h>
  26
  27 // #define USE_CPU_COUNTER_TIMER        /* whether we use cpu counter */
  28
  29 #ifdef USE_CPU_COUNTER_TIMER
  30
  31 #define CPU_COUNTER_FREQUENCY           83000000
  32 #else
  33 /* otherwise we use general purpose timer */
  34 #define TIMER_FREQUENCY                 83000000
  35 #define TIMER_BASE                      DDB_T2CTRL
  36 #define TIMER_IRQ                       (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
  37 #endif
  38
  39 #ifdef CONFIG_KGDB
  40 extern void breakpoint(void);
  41 #endif
  42
  43 static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
  44
  45 static void ddb_machine_restart(char *command)
  46 {
  47         u32 t;
  48
  49         /* PCI cold reset */
  50         t = ddb_in32(DDB_PCICTRL + 4);
  51         t |= 0x40000000;
  52         ddb_out32(DDB_PCICTRL + 4, t);
  53         /* CPU cold reset */
  54         t = ddb_in32(DDB_CPUSTAT);
  55         t |= 1;
  56         ddb_out32(DDB_CPUSTAT, t);
  57         /* Call the PROM */
  58         back_to_prom();
  59 }
  60
  61 static void ddb_machine_halt(void)
  62 {
  63         printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
  64         while (1);
  65 }
  66
  67 static void ddb_machine_power_off(void)
  68 {
  69         printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
  70         while (1);
  71 }
  72
  73 extern void ddb_irq_setup(void);
  74 extern void rtc_ds1386_init(unsigned long base);
  75
  76 static void __init ddb_time_init(void)
  77 {
  78 #if defined(USE_CPU_COUNTER_TIMER)
  79         mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
  80 #endif
  81
  82         /* we have ds1396 RTC chip */
  83         rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
  84 }
  85
  86
  87 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
  88 static void __init ddb_timer_setup(struct irqaction *irq)
  89 {
  90 #if defined(USE_CPU_COUNTER_TIMER)
  91
  92         unsigned int count;
  93
  94         /* we are using the cpu counter for timer interrupts */
  95         setup_irq(CPU_IRQ_BASE + 7, irq);
  96
  97         /* to generate the first timer interrupt */
  98         count = read_c0_count();
  99         write_c0_compare(count + 1000);
 100
 101 #else
 102
 103         ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
 104         ddb_out32(TIMER_BASE+4, 0x1);   /* enable timer */
 105         setup_irq(TIMER_IRQ, irq);
 106 #endif
 107 }
 108
 109 static struct {
 110         struct resource dma1;
 111         struct resource timer;
 112         struct resource rtc;
 113         struct resource dma_page_reg;
 114         struct resource dma2;
 115 } ddb5476_ioport = {
 116         {
 117         "dma1", 0x00, 0x1f, IORESOURCE_BUSY}, {
 118         "timer", 0x40, 0x5f, IORESOURCE_BUSY}, {
 119         "rtc", 0x70, 0x7f, IORESOURCE_BUSY}, {
 120         "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY}, {
 121         "dma2", 0xc0, 0xdf, IORESOURCE_BUSY}
 122 };
 123
 124 static struct {
 125         struct resource nile4;
 126 } ddb5476_iomem = {
 127         { "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
 128 };
 129
 130
 131 static void ddb5476_board_init(void);
 132 extern void ddb5476_irq_setup(void);
 133 extern void (*irq_setup)(void);
 134
 135 static void __init ddb5476_setup(void)
 136 {
 137         extern int panic_timeout;
 138
 139         irq_setup = ddb5476_irq_setup;
 140         set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
 141
 142         board_time_init = ddb_time_init;
 143         board_timer_setup = ddb_timer_setup;
 144
 145         _machine_restart = ddb_machine_restart;
 146         _machine_halt = ddb_machine_halt;
 147         _machine_power_off = ddb_machine_power_off;
 148
 149         /* request io port/mem resources  */
 150         if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
 151             request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
 152             request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
 153             request_resource(&ioport_resource,
 154                              &ddb5476_ioport.dma_page_reg)
 155             || request_resource(&ioport_resource, &ddb5476_ioport.dma2)
 156             || request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
 157                 printk
 158                     ("ddb_setup - requesting oo port resources failed.\n");
 159                 for (;;);
 160         }
 161
 162         /* Reboot on panic */
 163         panic_timeout = 180;
 164
 165         /* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
 166         /* *(long*)0xbfa00218 = 0x8; */
 167
 168         /* board initialization stuff */
 169         ddb5476_board_init();
 170 }
 171
 172 early_initcall(ddb5476_setup);
 173
 174 /*
 175  * We don't trust bios.  We essentially does hardware re-initialization
 176  * as complete as possible, as far as we know we can safely do.
 177  */
 178 static void ddb5476_board_init(void)
 179 {
 180         /* ----------- setup PDARs ------------ */
 181         /* check SDRAM0, whether we are on MEM bus does not matter */
 182         db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
 183                   ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
 184
 185         /* SDRAM1 should be turned off.  What is this for anyway ? */
 186         db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
 187
 188         /* flash 1&2, DDB status, DDB control */
 189         ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
 190         ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
 191         ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
 192         ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
 193
 194         /* shut off other pdar so they don't accidentally get into the way */
 195         ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
 196         ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
 197         ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
 198
 199         /* verify VRC5477 base addr */
 200         /* don't care about some details */
 201         db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
 202                   ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
 203
 204         /* verify BOOT ROM addr */
 205         /* don't care about some details */
 206         db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
 207                   ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
 208
 209         /* setup PCI windows - window1 for MEM/config, window0 for IO */
 210         ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
 211         ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
 212
 213         ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
 214         ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
 215
 216         /* ----------- setup PDARs ------------ */
 217         /* this is problematic - it will reset Aladin which cause we loose
 218          * serial port, and we don't know how to set up Aladin chip again.
 219          */
 220         // ddb_pci_reset_bus();
 221
 222         ddb_out32(DDB_BAR0, 0x00000008);
 223
 224         ddb_out32(DDB_BARC, 0xffffffff);
 225         ddb_out32(DDB_BARB, 0xffffffff);
 226         ddb_out32(DDB_BAR1, 0xffffffff);
 227         ddb_out32(DDB_BAR2, 0xffffffff);
 228         ddb_out32(DDB_BAR3, 0xffffffff);
 229         ddb_out32(DDB_BAR4, 0xffffffff);
 230         ddb_out32(DDB_BAR5, 0xffffffff);
 231         ddb_out32(DDB_BAR6, 0xffffffff);
 232         ddb_out32(DDB_BAR7, 0xffffffff);
 233         ddb_out32(DDB_BAR8, 0xffffffff);
 234
 235         /* ----------- switch PCI1 to PCI CONFIG space  ------------ */
 236         ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
 237         ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
 238
 239         /* ----- M1543 PCI setup ------ */
 240
 241         /* we know M1543 PCI-ISA controller is at addr:18 */
 242         /* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
 243         *(volatile unsigned char *) 0xa8040072 &= 0xf0;
 244         *(volatile unsigned char *) 0xa8040072 |= 0xa;
 245
 246         /* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
 247          * no IOCHRDY signal, (bit 7 - 1)
 248          * M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
 249          * Make USB Master INTAJ level to edge conversion (bit 4 - 1)
 250          */
 251         *(unsigned char *) 0xa8040074 = 0xd1;
 252
 253         /* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
 254          * SCI routing to IRQ 13 disabled (bit 7 - 1)
 255          * SCI interrupt level to edge conversion bypassed (bit 4 - 0)
 256          */
 257         *(unsigned char *) 0xa8040076 = 0x83;
 258
 259         /* setup IDE controller
 260          * enable IDE controller (bit 6 - 1)
 261          * IDE IDSEL to be addr:24 (bit 4:5 - 11)
 262          * no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
 263          * no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
 264          * primary IRQ is 14, secondary is 15 (bit 1:0 - 01
 265          */
 266         // *(unsigned char*)0xa8040058 = 0x71;
 267         // *(unsigned char*)0xa8040058 = 0x79;
 268         // *(unsigned char*)0xa8040058 = 0x74;              // use SIRQ, primary tri-state
 269         *(unsigned char *) 0xa8040058 = 0x75;   // primary tri-state
 270
 271 #if 0
 272         /* this is not necessary if M5229 does not use SIRQ */
 273         *(unsigned char *) 0xa8040044 = 0x0d;   // primary to IRQ 14
 274         *(unsigned char *) 0xa8040075 = 0x0d;   // secondary to IRQ 14
 275 #endif
 276
 277         /* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
 278         /* M5229 IDSEL is addr:24; see above setting */
 279         *(unsigned char *) 0xa9000050 |= 0x1;
 280
 281         /* enable bus master (bit 2)  and IO decoding  (bit 0) */
 282         *(unsigned char *) 0xa9000004 |= 0x5;
 283
 284         /* enable native, copied from arch/ppc/k2boot/head.S */
 285         /* TODO - need volatile, need to be portable */
 286         *(unsigned char *) 0xa9000009 = 0xff;
 287
 288         /* ----- end of M1543 PCI setup ------ */
 289
 290         /* ----- reset on-board ether chip  ------ */
 291         *((volatile u32 *) 0xa8020004) |= 1;    /* decode I/O */
 292         *((volatile u32 *) 0xa8020010) = 0;     /* set BAR address */
 293
 294         /* send reset command */
 295         *((volatile u32 *) 0xa6000000) = 1;     /* do a soft reset */
 296
 297         /* disable ether chip */
 298         *((volatile u32 *) 0xa8020004) = 0;     /* disable any decoding */
 299
 300         /* put it into sleep */
 301         *((volatile u32 *) 0xa8020040) = 0x80000000;
 302
 303         /* ----- end of reset on-board ether chip  ------ */
 304
 305         /* ----------- switch PCI1 back to PCI MEM space  ------------ */
 306         ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
 307         ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
 308 }