arch/mips/au1000/common/pci.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Alchemy/AMD Au1x00 pci support.
   4  *
   5  * Copyright 2001,2002,2003 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  Support for all devices (greater than 16) added by David Gathright.
  10  *
  11  *  This program is free software; you can redistribute  it and/or modify it
  12  *  under  the terms of  the GNU General  Public License as published by the
  13  *  Free Software Foundation;  either version 2 of the  License, or (at your
  14  *  option) any later version.
  15  *
  16  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  17  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  18  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  19  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  20  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  22  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  23  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  24  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  *  You should have received a copy of the  GNU General Public License along
  28  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  29  *  675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31 #include <linux/config.h>
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/init.h>
  36
  37 #include <asm/mach-au1x00/au1000.h>
  38 #include <asm/pci_channel.h>
  39
  40 /* TBD */
  41 static struct resource pci_io_resource = {
  42         "pci IO space",
  43         (u32)PCI_IO_START,
  44         (u32)PCI_IO_END,
  45         IORESOURCE_IO
  46 };
  47
  48 static struct resource pci_mem_resource = {
  49         "pci memory space",
  50         (u32)PCI_MEM_START,
  51         (u32)PCI_MEM_END,
  52         IORESOURCE_MEM
  53 };
  54
  55 extern struct pci_ops au1x_pci_ops;
  56
  57 static struct pci_controller au1x_controller = {
  58         .pci_ops        = &au1x_pci_ops,
  59         .io_resource    = &pci_io_resource,
  60         .mem_resource   = &pci_mem_resource,
  61 };
  62
  63 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  64 static unsigned long virt_io_addr;
  65 #endif
  66
  67 static int __init au1x_pci_setup(void)
  68 {
  69 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
  70         int i;
  71         struct pci_dev *dev;
  72
  73         virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
  74                         Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
  75
  76         if (!virt_io_addr) {
  77                 printk(KERN_ERR "Unable to ioremap pci space\n");
  78                 return;
  79         }
  80
  81 #ifdef CONFIG_DMA_NONCOHERENT
  82         /*
  83          *  Set the NC bit in controller for pre-AC silicon
  84          */
  85         au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
  86         printk("Non-coherent PCI accesses enabled\n");
  87 #endif
  88
  89         set_io_port_base(virt_io_addr);
  90 #endif
  91
  92         register_pci_controller(&au1x_controller);
  93         return 0;
  94 }
  95
  96 arch_initcall(au1x_pci_setup);