1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5307 ColdFire Arnewsh board.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
7 * Copyright (C) 2000 Lineo Inc. (www.lineo.com)
9 * 1999/02/24 Modified for the 5307 processor David W. Miller
12 /*****************************************************************************/
14 #include "linux/autoconf.h"
15 #include "asm/coldfire.h"
16 #include "asm/mcfsim.h"
17 #include "asm/nettel.h"
19 /*****************************************************************************/
22 * SnapGear/NETtel board memory setup.
24 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
25 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
26 #define VBR_BASE MEM_BASE /* Vector address */
28 /*****************************************************************************/
36 /*****************************************************************************/
41 * Set up the usable of RAM stuff. Size of RAM is determined then
42 * an initial stack set up at the end.
53 /*****************************************************************************/
58 * This is the codes first entry point. This is where it all
64 move.w #0x2700, %sr /* No interrupts */
67 * Setup VBR here, otherwise buserror remap will not work.
68 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
72 * Note: this is because dBUG points VBR to ROM, making vectors read
73 * only, so the bus trap can't be changed. (RS)
75 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
77 move.l %a7, _ramvec /* Set up vector addr */
78 move.l %a7, _rambase /* Set up base RAM addr */
82 * Determine size of RAM, then set up initial stack.
86 move.l %a0, %d0 /* Mem end addr is in a0 */
87 move.l %d0, %sp /* Set up initial stack ptr */
88 move.l %d0, _ramend /* Set end ram addr */
90 /* make region ROM cachable (turn off for flash programming?) */
91 /* 0xff000000 - 0xffffffff */
92 #ifdef DEBUGGER_COMPATIBLE_CACHE
93 movl #(0xff<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WTHRU+ACR_WPROTECT,%d0
95 movl #(0xff<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WBACK+ACR_WPROTECT,%d0
99 /* make region RAM cachable *
100 /* 0x00000000 - 0x00ffffffff */
101 #ifdef DEBUGGER_COMPATIBLE_CACHE
102 movl #(0x00<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WTHRU,%d0
104 movl #(0x00<<ACR_BASE_POS)+(0<<ACR_MASK_POS)+ACR_ENABLE+ACR_ANY+ACR_CM_WBACK,%d0
108 /* make the default cache mode precise */
109 movl #CACR_EC+CACR_ESB+CACR_DCM_OFF_PRE,%d0 /* enable cache */
114 #ifdef CONFIG_ROMFS_FS
116 * Move ROM filesystem above bss :-)
118 lea.l _sbss, %a0 /* Get start of bss */
119 lea.l _ebss, %a1 /* Set up destination */
120 move.l %a0, %a2 /* Copy of bss start */
122 move.l 8(%a0), %d0 /* Get size of ROMFS */
123 addq.l #8, %d0 /* Allow for rounding */
124 and.l #0xfffffffc, %d0 /* Whole words */
126 add.l %d0, %a0 /* Copy from end */
127 add.l %d0, %a1 /* Copy from end */
128 move.l %a1, _ramstart /* Set start of ram */
131 move.l -(%a0), %d0 /* Copy dword */
133 cmp.l %a0, %a2 /* Check if at end */
136 #else /* CONFIG_ROMFS_FS */
138 move.l %a1, _ramstart
139 #endif /* CONFIG_ROMFS_FS */
143 * Zero out the bss region.
145 lea.l _sbss, %a0 /* Get start of bss */
146 lea.l _ebss, %a1 /* Get end of bss */
147 clr.l %d0 /* Set value */
149 move.l %d0, (%a0)+ /* Clear each word */
150 cmp.l %a0, %a1 /* Check if at end */
154 * load the current task pointer and stack
156 lea init_thread_union, %a0
160 * Assember start up done, start code proper.
162 jsr start_kernel /* Start Linux kernel */
165 jmp _exit /* Should never get here */
167 /*****************************************************************************/