1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5272 ColdFire based boards.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com).
7 * (C) Copyright 2000, Lineo (www.lineo.com).
10 /*****************************************************************************/
12 #include <linux/config.h>
13 #include <linux/threads.h>
14 #include <linux/linkage.h>
15 #include <asm/segment.h>
16 #include <asm/coldfire.h>
17 #include <asm/mcfsim.h>
19 /*****************************************************************************/
22 * senTec COBRA5272 board, chip select and memory setup.
25 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
26 #define VBR_BASE MEM_BASE /* Vector address */
28 #if defined(CONFIG_RAM16MB)
29 #define MEM_SIZE 0x01000000 /* Memory size 16Mb */
30 #elif defined(CONFIG_RAM8MB)
31 #define MEM_SIZE 0x00800000 /* Memory size 8Mb */
33 #define MEM_SIZE 0x00400000 /* Memory size 4Mb */
36 /*****************************************************************************/
44 /*****************************************************************************/
49 * Set up the usable of RAM stuff. Size of RAM is determined then
50 * an initial stack set up at the end.
61 /*****************************************************************************/
66 * This is the codes first entry point. This is where it all
72 move.w #0x2700, %sr /* No interrupts */
75 * Setup VBR here, otherwise buserror remap will not work.
76 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
80 * Note: this is because dBUG points VBR to ROM, making vectors read
81 * only, so the bus trap can't be changed. (RS)
83 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
85 move.l %a7, _ramvec /* Set up vector addr */
86 move.l %a7, _rambase /* Set up base RAM addr */
94 move.l %a0, %d0 /* Mem end addr is in a0 */
95 move.l %d0, %sp /* Set up initial stack ptr */
96 move.l %d0, _ramend /* Set end ram addr */
99 * Enable CPU internal cache.
101 move.l #0x01000000, %d0 /* Invalidate cache cmd */
102 movec %d0, %CACR /* Invalidate cache */
103 move.l #0x80000100, %d0 /* Setup cache mask */
104 movec %d0, %CACR /* Enable cache */
106 #ifdef CONFIG_ROMFS_FS
108 * Move ROM filesystem above bss :-)
110 lea.l _sbss, %a0 /* Get start of bss */
111 lea.l _ebss, %a1 /* Set up destination */
112 move.l %a0, %a2 /* Copy of bss start */
114 move.l 8(%a0), %d0 /* Get size of ROMFS */
115 addq.l #8, %d0 /* Allow for rounding */
116 and.l #0xfffffffc, %d0 /* Whole words */
118 add.l %d0, %a0 /* Copy from end */
119 add.l %d0, %a1 /* Copy from end */
120 move.l %a1, _ramstart /* Set start of ram */
123 move.l -(%a0), %d0 /* Copy dword */
125 cmp.l %a0, %a2 /* Check if at end */
128 #else /* CONFIG_ROMFS_FS */
130 move.l %a1, _ramstart
131 #endif /* CONFIG_ROMFS_FS */
135 * Zero out the bss region.
137 lea.l _sbss, %a0 /* Get start of bss */
138 lea.l _ebss, %a1 /* Get end of bss */
139 clr.l %d0 /* Set value */
141 move.l %d0, (%a0)+ /* Clear each word */
142 cmp.l %a0, %a1 /* Check if at end */
146 * Load the current thread pointer and stack.
148 lea init_thread_union, %a0
152 * Assember start up done, start code proper.
154 jsr start_kernel /* Start Linux kernel */
157 jmp _exit /* Should never get here */
159 /*****************************************************************************/