arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/mm.h>
  18 #include <linux/irq.h>
  19 #include <linux/delay.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/mc146818rtc.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/module.h>
  26 #include <linux/nmi.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/sysctl.h>
  29
  30 #include <asm/smp.h>
  31 #include <asm/mtrr.h>
  32 #include <asm/mpspec.h>
  33 #include <asm/nmi.h>
  34
  35 #include "mach_traps.h"
  36
  37 unsigned int nmi_watchdog = NMI_NONE;
  38 extern int unknown_nmi_panic;
  39 static unsigned int nmi_hz = HZ;
  40 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  41 static unsigned int nmi_p4_cccr_val;
  42 extern void show_registers(struct pt_regs *regs);
  43
  44 /*
  45  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  46  * - it may be reserved by some other driver, or not
  47  * - when not reserved by some other driver, it may be used for
  48  *   the NMI watchdog, or not
  49  *
  50  * This is maintained separately from nmi_active because the NMI
  51  * watchdog may also be driven from the I/O APIC timer.
  52  */
  53 static spinlock_t lapic_nmi_owner_lock = SPIN_LOCK_UNLOCKED;
  54 static unsigned int lapic_nmi_owner;
  55 #define LAPIC_NMI_WATCHDOG      (1<<0)
  56 #define LAPIC_NMI_RESERVED      (1<<1)
  57
  58 /* nmi_active:
  59  * +1: the lapic NMI watchdog is active, but can be disabled
  60  *  0: the lapic NMI watchdog has not been set up, and cannot
  61  *     be enabled
  62  * -1: the lapic NMI watchdog is disabled, but can be enabled
  63  */
  64 int nmi_active;
  65
  66 #define K7_EVNTSEL_ENABLE       (1 << 22)
  67 #define K7_EVNTSEL_INT          (1 << 20)
  68 #define K7_EVNTSEL_OS           (1 << 17)
  69 #define K7_EVNTSEL_USR          (1 << 16)
  70 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  71 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  72
  73 #define P6_EVNTSEL0_ENABLE      (1 << 22)
  74 #define P6_EVNTSEL_INT          (1 << 20)
  75 #define P6_EVNTSEL_OS           (1 << 17)
  76 #define P6_EVNTSEL_USR          (1 << 16)
  77 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
  78 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
  79
  80 #define MSR_P4_MISC_ENABLE      0x1A0
  81 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  82 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  83 #define MSR_P4_PERFCTR0         0x300
  84 #define MSR_P4_CCCR0            0x360
  85 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  86 #define P4_ESCR_OS              (1<<3)
  87 #define P4_ESCR_USR             (1<<2)
  88 #define P4_CCCR_OVF_PMI0        (1<<26)
  89 #define P4_CCCR_OVF_PMI1        (1<<27)
  90 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  91 #define P4_CCCR_COMPLEMENT      (1<<19)
  92 #define P4_CCCR_COMPARE         (1<<18)
  93 #define P4_CCCR_REQUIRED        (3<<16)
  94 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  95 #define P4_CCCR_ENABLE          (1<<12)
  96 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  97    CRU_ESCR0 (with any non-null event selector) through a complemented
  98    max threshold. [IA32-Vol3, Section 14.9.9] */
  99 #define MSR_P4_IQ_COUNTER0      0x30C
 100 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
 101 #define P4_NMI_IQ_CCCR0 \
 102         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
 103          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
 104
 105 int __init check_nmi_watchdog (void)
 106 {
 107         unsigned int prev_nmi_count[NR_CPUS];
 108         int cpu;
 109
 110         printk(KERN_INFO "testing NMI watchdog ... ");
 111
 112         for (cpu = 0; cpu < NR_CPUS; cpu++)
 113                 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
 114         local_irq_enable();
 115         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 116
 117         /* FIXME: Only boot CPU is online at this stage.  Check CPUs
 118            as they come up. */
 119         for (cpu = 0; cpu < NR_CPUS; cpu++) {
 120                 if (!cpu_online(cpu))
 121                         continue;
 122                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 123                         printk("CPU#%d: NMI appears to be stuck!\n", cpu);
 124                         nmi_active = 0;
 125                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 126                         return -1;
 127                 }
 128         }
 129         printk("OK.\n");
 130
 131         /* now that we know it works we can reduce NMI frequency to
 132            something more reasonable; makes a difference in some configs */
 133         if (nmi_watchdog == NMI_LOCAL_APIC)
 134                 nmi_hz = 1;
 135
 136         return 0;
 137 }
 138
 139 static int __init setup_nmi_watchdog(char *str)
 140 {
 141         int nmi;
 142
 143         get_option(&str, &nmi);
 144
 145         if (nmi >= NMI_INVALID)
 146                 return 0;
 147         if (nmi == NMI_NONE)
 148                 nmi_watchdog = nmi;
 149         /*
 150          * If any other x86 CPU has a local APIC, then
 151          * please test the NMI stuff there and send me the
 152          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 153          */
 154         if ((nmi == NMI_LOCAL_APIC) &&
 155                         (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
 156                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 157                 nmi_watchdog = nmi;
 158         if ((nmi == NMI_LOCAL_APIC) &&
 159                         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 160                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 161                 nmi_watchdog = nmi;
 162         /*
 163          * We can enable the IO-APIC watchdog
 164          * unconditionally.
 165          */
 166         if (nmi == NMI_IO_APIC) {
 167                 nmi_active = 1;
 168                 nmi_watchdog = nmi;
 169         }
 170         return 1;
 171 }
 172
 173 __setup("nmi_watchdog=", setup_nmi_watchdog);
 174
 175 static void disable_lapic_nmi_watchdog(void)
 176 {
 177         if (nmi_active <= 0)
 178                 return;
 179         switch (boot_cpu_data.x86_vendor) {
 180         case X86_VENDOR_AMD:
 181                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 182                 break;
 183         case X86_VENDOR_INTEL:
 184                 switch (boot_cpu_data.x86) {
 185                 case 6:
 186                         if (boot_cpu_data.x86_model > 0xd)
 187                                 break;
 188
 189                         wrmsr(MSR_P6_EVNTSEL0, 0, 0);
 190                         break;
 191                 case 15:
 192                         if (boot_cpu_data.x86_model > 0x3)
 193                                 break;
 194
 195                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 196                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 197                         break;
 198                 }
 199                 break;
 200         }
 201         nmi_active = -1;
 202         /* tell do_nmi() and others that we're not active any more */
 203         nmi_watchdog = 0;
 204 }
 205
 206 static void enable_lapic_nmi_watchdog(void)
 207 {
 208         if (nmi_active < 0) {
 209                 nmi_watchdog = NMI_LOCAL_APIC;
 210                 setup_apic_nmi_watchdog();
 211         }
 212 }
 213
 214 int reserve_lapic_nmi(void)
 215 {
 216         unsigned int old_owner;
 217
 218         spin_lock(&lapic_nmi_owner_lock);
 219         old_owner = lapic_nmi_owner;
 220         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 221         spin_unlock(&lapic_nmi_owner_lock);
 222         if (old_owner & LAPIC_NMI_RESERVED)
 223                 return -EBUSY;
 224         if (old_owner & LAPIC_NMI_WATCHDOG)
 225                 disable_lapic_nmi_watchdog();
 226         return 0;
 227 }
 228
 229 void release_lapic_nmi(void)
 230 {
 231         unsigned int new_owner;
 232
 233         spin_lock(&lapic_nmi_owner_lock);
 234         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 235         lapic_nmi_owner = new_owner;
 236         spin_unlock(&lapic_nmi_owner_lock);
 237         if (new_owner & LAPIC_NMI_WATCHDOG)
 238                 enable_lapic_nmi_watchdog();
 239 }
 240
 241 void disable_timer_nmi_watchdog(void)
 242 {
 243         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 244                 return;
 245
 246         unset_nmi_callback();
 247         nmi_active = -1;
 248         nmi_watchdog = NMI_NONE;
 249 }
 250
 251 void enable_timer_nmi_watchdog(void)
 252 {
 253         if (nmi_active < 0) {
 254                 nmi_watchdog = NMI_IO_APIC;
 255                 touch_nmi_watchdog();
 256                 nmi_active = 1;
 257         }
 258 }
 259
 260 #ifdef CONFIG_PM
 261
 262 static int nmi_pm_active; /* nmi_active before suspend */
 263
 264 static int lapic_nmi_suspend(struct sys_device *dev, u32 state)
 265 {
 266         nmi_pm_active = nmi_active;
 267         disable_lapic_nmi_watchdog();
 268         return 0;
 269 }
 270
 271 static int lapic_nmi_resume(struct sys_device *dev)
 272 {
 273         if (nmi_pm_active > 0)
 274                 enable_lapic_nmi_watchdog();
 275         return 0;
 276 }
 277
 278
 279 static struct sysdev_class nmi_sysclass = {
 280         set_kset_name("lapic_nmi"),
 281         .resume         = lapic_nmi_resume,
 282         .suspend        = lapic_nmi_suspend,
 283 };
 284
 285 static struct sys_device device_lapic_nmi = {
 286         .id     = 0,
 287         .cls    = &nmi_sysclass,
 288 };
 289
 290 static int __init init_lapic_nmi_sysfs(void)
 291 {
 292         int error;
 293
 294         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 295                 return 0;
 296
 297         error = sysdev_class_register(&nmi_sysclass);
 298         if (!error)
 299                 error = sysdev_register(&device_lapic_nmi);
 300         return error;
 301 }
 302 /* must come after the local APIC's device_initcall() */
 303 late_initcall(init_lapic_nmi_sysfs);
 304
 305 #endif  /* CONFIG_PM */
 306
 307 /*
 308  * Activate the NMI watchdog via the local APIC.
 309  * Original code written by Keith Owens.
 310  */
 311
 312 static void clear_msr_range(unsigned int base, unsigned int n)
 313 {
 314         unsigned int i;
 315
 316         for(i = 0; i < n; ++i)
 317                 wrmsr(base+i, 0, 0);
 318 }
 319
 320 static void setup_k7_watchdog(void)
 321 {
 322         unsigned int evntsel;
 323
 324         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 325
 326         clear_msr_range(MSR_K7_EVNTSEL0, 4);
 327         clear_msr_range(MSR_K7_PERFCTR0, 4);
 328
 329         evntsel = K7_EVNTSEL_INT
 330                 | K7_EVNTSEL_OS
 331                 | K7_EVNTSEL_USR
 332                 | K7_NMI_EVENT;
 333
 334         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 335         Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
 336         wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
 337         apic_write(APIC_LVTPC, APIC_DM_NMI);
 338         evntsel |= K7_EVNTSEL_ENABLE;
 339         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 340 }
 341
 342 static void setup_p6_watchdog(void)
 343 {
 344         unsigned int evntsel;
 345
 346         nmi_perfctr_msr = MSR_P6_PERFCTR0;
 347
 348         clear_msr_range(MSR_P6_EVNTSEL0, 2);
 349         clear_msr_range(MSR_P6_PERFCTR0, 2);
 350
 351         evntsel = P6_EVNTSEL_INT
 352                 | P6_EVNTSEL_OS
 353                 | P6_EVNTSEL_USR
 354                 | P6_NMI_EVENT;
 355
 356         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 357         Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
 358         wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
 359         apic_write(APIC_LVTPC, APIC_DM_NMI);
 360         evntsel |= P6_EVNTSEL0_ENABLE;
 361         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 362 }
 363
 364 static int setup_p4_watchdog(void)
 365 {
 366         unsigned int misc_enable, dummy;
 367
 368         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 369         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 370                 return 0;
 371
 372         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 373         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 374 #ifdef CONFIG_SMP
 375         if (smp_num_siblings == 2)
 376                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 377 #endif
 378
 379         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 380                 clear_msr_range(0x3F1, 2);
 381         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 382            docs doesn't fully define it, so leave it alone for now. */
 383         if (boot_cpu_data.x86_model >= 0x3) {
 384                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 385                 clear_msr_range(0x3A0, 26);
 386                 clear_msr_range(0x3BC, 3);
 387         } else {
 388                 clear_msr_range(0x3A0, 31);
 389         }
 390         clear_msr_range(0x3C0, 6);
 391         clear_msr_range(0x3C8, 6);
 392         clear_msr_range(0x3E0, 2);
 393         clear_msr_range(MSR_P4_CCCR0, 18);
 394         clear_msr_range(MSR_P4_PERFCTR0, 18);
 395
 396         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 397         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 398         Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
 399         wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
 400         apic_write(APIC_LVTPC, APIC_DM_NMI);
 401         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 402         return 1;
 403 }
 404
 405 void setup_apic_nmi_watchdog (void)
 406 {
 407         switch (boot_cpu_data.x86_vendor) {
 408         case X86_VENDOR_AMD:
 409                 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 410                         return;
 411                 setup_k7_watchdog();
 412                 break;
 413         case X86_VENDOR_INTEL:
 414                 switch (boot_cpu_data.x86) {
 415                 case 6:
 416                         if (boot_cpu_data.x86_model > 0xd)
 417                                 return;
 418
 419                         setup_p6_watchdog();
 420                         break;
 421                 case 15:
 422                         if (boot_cpu_data.x86_model > 0x3)
 423                                 return;
 424
 425                         if (!setup_p4_watchdog())
 426                                 return;
 427                         break;
 428                 default:
 429                         return;
 430                 }
 431                 break;
 432         default:
 433                 return;
 434         }
 435         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 436         nmi_active = 1;
 437 }
 438
 439 /*
 440  * the best way to detect whether a CPU has a 'hard lockup' problem
 441  * is to check it's local APIC timer IRQ counts. If they are not
 442  * changing then that CPU has some problem.
 443  *
 444  * as these watchdog NMI IRQs are generated on every CPU, we only
 445  * have to check the current processor.
 446  *
 447  * since NMIs don't listen to _any_ locks, we have to be extremely
 448  * careful not to rely on unsafe variables. The printk might lock
 449  * up though, so we have to break up any console locks first ...
 450  * [when there will be more tty-related locks, break them up
 451  *  here too!]
 452  */
 453
 454 static unsigned int
 455         last_irq_sums [NR_CPUS],
 456         alert_counter [NR_CPUS];
 457
 458 void touch_nmi_watchdog (void)
 459 {
 460         int i;
 461
 462         /*
 463          * Just reset the alert counters, (other CPUs might be
 464          * spinning on locks we hold):
 465          */
 466         for (i = 0; i < NR_CPUS; i++)
 467                 alert_counter[i] = 0;
 468 }
 469
 470 extern void die_nmi(struct pt_regs *, const char *msg);
 471
 472 void nmi_watchdog_tick (struct pt_regs * regs)
 473 {
 474
 475         /*
 476          * Since current_thread_info()-> is always on the stack, and we
 477          * always switch the stack NMI-atomically, it's safe to use
 478          * smp_processor_id().
 479          */
 480         int sum, cpu = smp_processor_id();
 481
 482         sum = irq_stat[cpu].apic_timer_irqs;
 483
 484         if (last_irq_sums[cpu] == sum) {
 485                 /*
 486                  * Ayiee, looks like this CPU is stuck ...
 487                  * wait a few IRQs (5 seconds) before doing the oops ...
 488                  */
 489                 alert_counter[cpu]++;
 490                 if (alert_counter[cpu] == 5*nmi_hz)
 491                         die_nmi(regs, "NMI Watchdog detected LOCKUP");
 492         } else {
 493                 last_irq_sums[cpu] = sum;
 494                 alert_counter[cpu] = 0;
 495         }
 496         if (nmi_perfctr_msr) {
 497                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 498                         /*
 499                          * P4 quirks:
 500                          * - An overflown perfctr will assert its interrupt
 501                          *   until the OVF flag in its CCCR is cleared.
 502                          * - LVTPC is masked on interrupt and must be
 503                          *   unmasked by the LVTPC handler.
 504                          */
 505                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 506                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 507                 }
 508                 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
 509                         /* Only P6 based Pentium M need to re-unmask
 510                          * the apic vector but it doesn't hurt
 511                          * other P6 variant */
 512                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 513                 }
 514                 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
 515         }
 516 }
 517
 518 #ifdef CONFIG_SYSCTL
 519
 520 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 521 {
 522         unsigned char reason = get_nmi_reason();
 523         char buf[64];
 524
 525         if (!(reason & 0xc0)) {
 526                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 527                 die_nmi(regs, buf);
 528         }
 529         return 0;
 530 }
 531
 532 /*
 533  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 534  */
 535 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
 536                         void __user *buffer, size_t *length, loff_t *ppos)
 537 {
 538         int old_state;
 539
 540         old_state = unknown_nmi_panic;
 541         proc_dointvec(table, write, file, buffer, length, ppos);
 542         if (!!old_state == !!unknown_nmi_panic)
 543                 return 0;
 544
 545         if (unknown_nmi_panic) {
 546                 if (reserve_lapic_nmi() < 0) {
 547                         unknown_nmi_panic = 0;
 548                         return -EBUSY;
 549                 } else {
 550                         set_nmi_callback(unknown_nmi_panic_callback);
 551                 }
 552         } else {
 553                 release_lapic_nmi();
 554                 unset_nmi_callback();
 555         }
 556         return 0;
 557 }
 558
 559 #endif
 560
 561 EXPORT_SYMBOL(nmi_active);
 562 EXPORT_SYMBOL(nmi_watchdog);
 563 EXPORT_SYMBOL(reserve_lapic_nmi);
 564 EXPORT_SYMBOL(release_lapic_nmi);
 565 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 566 EXPORT_SYMBOL(enable_timer_nmi_watchdog);