arch/i386/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18
  19 #include <asm/msr.h>
  20 #include "speedstep-lib.h"
  21
  22
  23 /* DEBUG
  24  *   Define it if you want verbose debug output, e.g. for bug reporting
  25  */
  26 //#define SPEEDSTEP_DEBUG
  27
  28 #ifdef SPEEDSTEP_DEBUG
  29 #define dprintk(msg...) printk(msg)
  30 #else
  31 #define dprintk(msg...) do { } while(0)
  32 #endif
  33
  34 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  35 static int relaxed_check = 0;
  36 #else
  37 #define relaxed_check 0
  38 #endif
  39
  40 /*********************************************************************
  41  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  42  *********************************************************************/
  43
  44 static unsigned int pentium3_get_frequency (unsigned int processor)
  45 {
  46         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  47         struct {
  48                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  49                 u8 bitmap;              /* power on configuration bits
  50                                            [27, 25:22] (in MSR 0x2a) */
  51         } msr_decode_mult [] = {
  52                 { 30, 0x01 },
  53                 { 35, 0x05 },
  54                 { 40, 0x02 },
  55                 { 45, 0x06 },
  56                 { 50, 0x00 },
  57                 { 55, 0x04 },
  58                 { 60, 0x0b },
  59                 { 65, 0x0f },
  60                 { 70, 0x09 },
  61                 { 75, 0x0d },
  62                 { 80, 0x0a },
  63                 { 85, 0x26 },
  64                 { 90, 0x20 },
  65                 { 100, 0x2b },
  66                 { 0, 0xff }     /* error or unknown value */
  67         };
  68
  69         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  70         struct {
  71                 unsigned int value;     /* Front Side Bus speed in MHz */
  72                 u8 bitmap;              /* power on configuration bits [18: 19]
  73                                            (in MSR 0x2a) */
  74         } msr_decode_fsb [] = {
  75                 {  66, 0x0 },
  76                 { 100, 0x2 },
  77                 { 133, 0x1 },
  78                 {   0, 0xff}
  79         };
  80
  81         u32     msr_lo, msr_tmp;
  82         int     i = 0, j = 0;
  83
  84         /* read MSR 0x2a - we only need the low 32 bits */
  85         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  86         dprintk(KERN_DEBUG "speedstep-lib: P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  87         msr_tmp = msr_lo;
  88
  89         /* decode the FSB */
  90         msr_tmp &= 0x00c0000;
  91         msr_tmp >>= 18;
  92         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  93                 if (msr_decode_fsb[i].bitmap == 0xff)
  94                         return 0;
  95                 i++;
  96         }
  97
  98         /* decode the multiplier */
  99         if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY)
 100                 msr_lo &= 0x03c00000;
 101         else
 102                 msr_lo &= 0x0bc00000;
 103         msr_lo >>= 22;
 104         while (msr_lo != msr_decode_mult[j].bitmap) {
 105                 if (msr_decode_mult[j].bitmap == 0xff)
 106                         return 0;
 107                 j++;
 108         }
 109
 110         return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
 111 }
 112
 113
 114 static unsigned int pentiumM_get_frequency(void)
 115 {
 116         u32     msr_lo, msr_tmp;
 117
 118         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 119         dprintk(KERN_DEBUG "speedstep-lib: PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 120
 121         /* see table B-2 of 24547212.pdf */
 122         if (msr_lo & 0x00040000) {
 123                 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
 124                 return 0;
 125         }
 126
 127         msr_tmp = (msr_lo >> 22) & 0x1f;
 128         dprintk(KERN_DEBUG "speedstep-lib: bits 22-26 are 0x%x\n", msr_tmp);
 129
 130         return (msr_tmp * 100 * 1000);
 131 }
 132
 133
 134 static unsigned int pentium4_get_frequency(void)
 135 {
 136         struct cpuinfo_x86 *c = &boot_cpu_data;
 137         u32 msr_lo, msr_hi, mult;
 138         unsigned int fsb = 0;
 139
 140         rdmsr(0x2c, msr_lo, msr_hi);
 141
 142         dprintk(KERN_DEBUG "speedstep-lib: P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 143
 144         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 145          * Developer's Manual, Volume 3: System Prgramming Guide,
 146          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 147          * Intel Xeon Processors, on page B-4 and B-5.
 148          */
 149         if (c->x86_model < 2)
 150                 fsb = 100 * 1000;
 151         else {
 152                 u8 fsb_code = (msr_lo >> 16) & 0x7;
 153                 switch (fsb_code) {
 154                 case 0:
 155                         fsb = 100 * 1000;
 156                         break;
 157                 case 1:
 158                         fsb = 13333 * 10;
 159                         break;
 160                 case 2:
 161                         fsb = 200 * 1000;
 162                         break;
 163                 }
 164         }
 165
 166         if (!fsb)
 167                 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
 168
 169         /* Multiplier. */
 170         mult = msr_lo >> 24;
 171
 172         dprintk(KERN_DEBUG "speedstep-lib: P4 - FSB %u kHz; Multiplier %u\n", fsb, mult);
 173
 174         return (fsb * mult);
 175 }
 176
 177
 178 unsigned int speedstep_get_processor_frequency(unsigned int processor)
 179 {
 180         switch (processor) {
 181         case SPEEDSTEP_PROCESSOR_PM:
 182                 return pentiumM_get_frequency();
 183         case SPEEDSTEP_PROCESSOR_P4D:
 184         case SPEEDSTEP_PROCESSOR_P4M:
 185                 return pentium4_get_frequency();
 186         case SPEEDSTEP_PROCESSOR_PIII_T:
 187         case SPEEDSTEP_PROCESSOR_PIII_C:
 188         case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
 189                 return pentium3_get_frequency(processor);
 190         default:
 191                 return 0;
 192         };
 193         return 0;
 194 }
 195 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
 196
 197
 198 /*********************************************************************
 199  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 200  *********************************************************************/
 201
 202 unsigned int speedstep_detect_processor (void)
 203 {
 204         struct cpuinfo_x86 *c = cpu_data;
 205         u32                     ebx, msr_lo, msr_hi;
 206
 207         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 208             ((c->x86 != 6) && (c->x86 != 0xF)))
 209                 return 0;
 210
 211         if (c->x86 == 0xF) {
 212                 /* Intel Mobile Pentium 4-M
 213                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 214                 if (c->x86_model != 2)
 215                         return 0;
 216
 217                 ebx = cpuid_ebx(0x00000001);
 218                 ebx &= 0x000000FF;
 219
 220                 dprintk(KERN_INFO "ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 221
 222                 switch (c->x86_mask) {
 223                 case 4:
 224                         /*
 225                          * B-stepping [M-P4-M]
 226                          * sample has ebx = 0x0f, production has 0x0e.
 227                          */
 228                         if ((ebx == 0x0e) || (ebx == 0x0f))
 229                                 return SPEEDSTEP_PROCESSOR_P4M;
 230                         break;
 231                 case 7:
 232                         /*
 233                          * C-stepping [M-P4-M]
 234                          * needs to have ebx=0x0e, else it's a celeron:
 235                          * cf. 25130917.pdf / page 7, footnote 5 even
 236                          * though 25072120.pdf / page 7 doesn't say
 237                          * samples are only of B-stepping...
 238                          */
 239                         if (ebx == 0x0e)
 240                                 return SPEEDSTEP_PROCESSOR_P4M;
 241                         break;
 242                 case 9:
 243                         /*
 244                          * D-stepping [M-P4-M or M-P4/533]
 245                          *
 246                          * this is totally strange: CPUID 0x0F29 is
 247                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 248                          * The latter need to be sorted out as they don't
 249                          * support speedstep.
 250                          * Celerons with CPUID 0x0F29 may have either
 251                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 252                          * specific.
 253                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 254                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 255                          * also, M-P4M HTs have ebx=0x8, too
 256                          * For now, they are distinguished by the model_id string
 257                          */
 258                         if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
 259                                 return SPEEDSTEP_PROCESSOR_P4M;
 260                         break;
 261                 default:
 262                         break;
 263                 }
 264                 return 0;
 265         }
 266
 267         switch (c->x86_model) {
 268         case 0x0B: /* Intel PIII [Tualatin] */
 269                 /* cpuid_ebx(1) is 0x04 for desktop PIII,
 270                                    0x06 for mobile PIII-M */
 271                 ebx = cpuid_ebx(0x00000001);
 272
 273                 ebx &= 0x000000FF;
 274
 275                 if (ebx != 0x06)
 276                         return 0;
 277
 278                 /* So far all PIII-M processors support SpeedStep. See
 279                  * Intel's 24540640.pdf of June 2003
 280                  */
 281
 282                 return SPEEDSTEP_PROCESSOR_PIII_T;
 283
 284         case 0x08: /* Intel PIII [Coppermine] */
 285
 286                 /* all mobile PIII Coppermines have FSB 100 MHz
 287                  * ==> sort out a few desktop PIIIs. */
 288                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 289                 dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
 290                 msr_lo &= 0x00c0000;
 291                 if (msr_lo != 0x0080000)
 292                         return 0;
 293
 294                 /*
 295                  * If the processor is a mobile version,
 296                  * platform ID has bit 50 set
 297                  * it has SpeedStep technology if either
 298                  * bit 56 or 57 is set
 299                  */
 300                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 301                 dprintk(KERN_DEBUG "cpufreq: Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
 302                 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 303                         if (c->x86_mask == 0x01)
 304                                 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
 305                         else
 306                                 return SPEEDSTEP_PROCESSOR_PIII_C;
 307                 }
 308
 309         default:
 310                 return 0;
 311         }
 312 }
 313 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 314
 315
 316 /*********************************************************************
 317  *                     DETECT SPEEDSTEP SPEEDS                       *
 318  *********************************************************************/
 319
 320 unsigned int speedstep_get_freqs(unsigned int processor,
 321                                   unsigned int *low_speed,
 322                                   unsigned int *high_speed,
 323                                   void (*set_state) (unsigned int state))
 324 {
 325         unsigned int prev_speed;
 326         unsigned int ret = 0;
 327         unsigned long flags;
 328
 329         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 330                 return -EINVAL;
 331
 332         /* get current speed */
 333         prev_speed = speedstep_get_processor_frequency(processor);
 334         if (!prev_speed)
 335                 return -EIO;
 336
 337         local_irq_save(flags);
 338
 339         /* switch to low state */
 340         set_state(SPEEDSTEP_LOW);
 341         *low_speed = speedstep_get_processor_frequency(processor);
 342         if (!*low_speed) {
 343                 ret = -EIO;
 344                 goto out;
 345         }
 346
 347         /* switch to high state */
 348         set_state(SPEEDSTEP_HIGH);
 349         *high_speed = speedstep_get_processor_frequency(processor);
 350         if (!*high_speed) {
 351                 ret = -EIO;
 352                 goto out;
 353         }
 354
 355         if (*low_speed == *high_speed) {
 356                 ret = -ENODEV;
 357                 goto out;
 358         }
 359
 360         /* switch to previous state, if necessary */
 361         if (*high_speed != prev_speed)
 362                 set_state(SPEEDSTEP_LOW);
 363
 364  out:
 365         local_irq_restore(flags);
 366         return (ret);
 367 }
 368 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 369
 370 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 371 module_param(relaxed_check, int, 0444);
 372 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
 373 #endif
 374
 375 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
 376 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 377 MODULE_LICENSE ("GPL");