arch/arm/mach-omap/gpio.c

   1 /*
   2  *  linux/arch/arm/mach-omap/gpio.c
   3  *
   4  * Support functions for OMAP GPIO
   5  *
   6  * Copyright (C) 2003 Nokia Corporation
   7  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/sched.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/ptrace.h>
  20
  21 #include <asm/hardware.h>
  22 #include <asm/irq.h>
  23 #include <asm/arch/irqs.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/mach/irq.h>
  26
  27 #include <asm/io.h>
  28
  29 /*
  30  * OMAP1510 GPIO registers
  31  */
  32 #define OMAP1510_GPIO_BASE              0xfffce000
  33 #define OMAP1510_GPIO_DATA_INPUT        0x00
  34 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
  35 #define OMAP1510_GPIO_DIR_CONTROL       0x08
  36 #define OMAP1510_GPIO_INT_CONTROL       0x0c
  37 #define OMAP1510_GPIO_INT_MASK          0x10
  38 #define OMAP1510_GPIO_INT_STATUS        0x14
  39 #define OMAP1510_GPIO_PIN_CONTROL       0x18
  40
  41 #define OMAP1510_IH_GPIO_BASE           64
  42
  43 /*
  44  * OMAP1610 specific GPIO registers
  45  */
  46 #define OMAP1610_GPIO1_BASE             0xfffbe400
  47 #define OMAP1610_GPIO2_BASE             0xfffbec00
  48 #define OMAP1610_GPIO3_BASE             0xfffbb400
  49 #define OMAP1610_GPIO4_BASE             0xfffbbc00
  50 #define OMAP1610_GPIO_REVISION          0x0000
  51 #define OMAP1610_GPIO_SYSCONFIG         0x0010
  52 #define OMAP1610_GPIO_SYSSTATUS         0x0014
  53 #define OMAP1610_GPIO_IRQSTATUS1        0x0018
  54 #define OMAP1610_GPIO_IRQENABLE1        0x001c
  55 #define OMAP1610_GPIO_DATAIN            0x002c
  56 #define OMAP1610_GPIO_DATAOUT           0x0030
  57 #define OMAP1610_GPIO_DIRECTION         0x0034
  58 #define OMAP1610_GPIO_EDGE_CTRL1        0x0038
  59 #define OMAP1610_GPIO_EDGE_CTRL2        0x003c
  60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
  61 #define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
  62 #define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
  63 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
  64
  65 /*
  66  * OMAP730 specific GPIO registers
  67  */
  68 #define OMAP730_GPIO1_BASE              0xfffbc000
  69 #define OMAP730_GPIO2_BASE              0xfffbc800
  70 #define OMAP730_GPIO3_BASE              0xfffbd000
  71 #define OMAP730_GPIO4_BASE              0xfffbd800
  72 #define OMAP730_GPIO5_BASE              0xfffbe000
  73 #define OMAP730_GPIO6_BASE              0xfffbe800
  74 #define OMAP730_GPIO_DATA_INPUT         0x00
  75 #define OMAP730_GPIO_DATA_OUTPUT        0x04
  76 #define OMAP730_GPIO_DIR_CONTROL        0x08
  77 #define OMAP730_GPIO_INT_CONTROL        0x0c
  78 #define OMAP730_GPIO_INT_MASK           0x10
  79 #define OMAP730_GPIO_INT_STATUS         0x14
  80
  81 #define OMAP_MPUIO_MASK         (~OMAP_MAX_GPIO_LINES & 0xff)
  82
  83 struct gpio_bank {
  84         u32 base;
  85         u16 irq;
  86         u16 virtual_irq_start;
  87         u8 method;
  88         u32 reserved_map;
  89         spinlock_t lock;
  90 };
  91
  92 #define METHOD_MPUIO            0
  93 #define METHOD_GPIO_1510        1
  94 #define METHOD_GPIO_1610        2
  95 #define METHOD_GPIO_730         3
  96
  97 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
  98 static struct gpio_bank gpio_bank_1610[5] = {
  99         { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
 100         { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
 101         { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
 102         { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
 103         { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
 104 };
 105 #endif
 106
 107 #ifdef CONFIG_ARCH_OMAP1510
 108 static struct gpio_bank gpio_bank_1510[2] = {
 109         { OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
 110         { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
 111 };
 112 #endif
 113
 114 #ifdef CONFIG_ARCH_OMAP730
 115 static struct gpio_bank gpio_bank_730[7] = {
 116         { OMAP_MPUIO_BASE,     INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
 117         { OMAP730_GPIO1_BASE,  INT_GPIO_BANK1,      IH_GPIO_BASE,       METHOD_GPIO_730 },
 118         { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
 119         { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
 120         { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
 121         { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
 122         { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
 123 };
 124 #endif
 125
 126 static struct gpio_bank *gpio_bank;
 127 static int gpio_bank_count;
 128
 129 static inline struct gpio_bank *get_gpio_bank(int gpio)
 130 {
 131 #ifdef CONFIG_ARCH_OMAP1510
 132         if (cpu_is_omap1510()) {
 133                 if (OMAP_GPIO_IS_MPUIO(gpio))
 134                         return &gpio_bank[0];
 135                 return &gpio_bank[1];
 136         }
 137 #endif
 138 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 139         if (cpu_is_omap1610() || cpu_is_omap1710() || cpu_is_omap5912()) {
 140                 if (OMAP_GPIO_IS_MPUIO(gpio))
 141                         return &gpio_bank[0];
 142                 return &gpio_bank[1 + (gpio >> 4)];
 143         }
 144 #endif
 145 #ifdef CONFIG_ARCH_OMAP730
 146         if (cpu_is_omap730()) {
 147                 if (OMAP_GPIO_IS_MPUIO(gpio))
 148                         return &gpio_bank[0];
 149                 return &gpio_bank[1 + (gpio >> 5)];
 150         }
 151 #endif
 152 }
 153
 154 static inline int get_gpio_index(int gpio)
 155 {
 156         if (cpu_is_omap730())
 157                 return gpio & 0x1f;
 158         else
 159                 return gpio & 0x0f;
 160 }
 161
 162 static inline int gpio_valid(int gpio)
 163 {
 164         if (gpio < 0)
 165                 return -1;
 166         if (OMAP_GPIO_IS_MPUIO(gpio)) {
 167                 if ((gpio & OMAP_MPUIO_MASK) > 16)
 168                         return -1;
 169                 return 0;
 170         }
 171 #ifdef CONFIG_ARCH_OMAP1510
 172         if (cpu_is_omap1510() && gpio < 16)
 173                 return 0;
 174 #endif
 175 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 176         if ((cpu_is_omap1610() || cpu_is_omap1710() || cpu_is_omap5912()) && gpio < 64)
 177                 return 0;
 178 #endif
 179 #ifdef CONFIG_ARCH_OMAP730
 180         if (cpu_is_omap730() && gpio < 192)
 181                 return 0;
 182 #endif
 183         return -1;
 184 }
 185
 186 static int check_gpio(int gpio)
 187 {
 188         if (unlikely(gpio_valid(gpio)) < 0) {
 189                 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
 190                 dump_stack();
 191                 return -1;
 192         }
 193         return 0;
 194 }
 195
 196 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 197 {
 198         u32 reg = bank->base;
 199         u32 l;
 200
 201         switch (bank->method) {
 202         case METHOD_MPUIO:
 203                 reg += OMAP_MPUIO_IO_CNTL;
 204                 break;
 205         case METHOD_GPIO_1510:
 206                 reg += OMAP1510_GPIO_DIR_CONTROL;
 207                 break;
 208         case METHOD_GPIO_1610:
 209                 reg += OMAP1610_GPIO_DIRECTION;
 210                 break;
 211         case METHOD_GPIO_730:
 212                 reg += OMAP730_GPIO_DIR_CONTROL;
 213                 break;
 214         }
 215         l = __raw_readl(reg);
 216         if (is_input)
 217                 l |= 1 << gpio;
 218         else
 219                 l &= ~(1 << gpio);
 220         __raw_writel(l, reg);
 221 }
 222
 223 void omap_set_gpio_direction(int gpio, int is_input)
 224 {
 225         struct gpio_bank *bank;
 226
 227         if (check_gpio(gpio) < 0)
 228                 return;
 229         bank = get_gpio_bank(gpio);
 230         spin_lock(&bank->lock);
 231         _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
 232         spin_unlock(&bank->lock);
 233 }
 234
 235 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 236 {
 237         u32 reg = bank->base;
 238         u32 l = 0;
 239
 240         switch (bank->method) {
 241         case METHOD_MPUIO:
 242                 reg += OMAP_MPUIO_OUTPUT;
 243                 l = __raw_readl(reg);
 244                 if (enable)
 245                         l |= 1 << gpio;
 246                 else
 247                         l &= ~(1 << gpio);
 248                 break;
 249         case METHOD_GPIO_1510:
 250                 reg += OMAP1510_GPIO_DATA_OUTPUT;
 251                 l = __raw_readl(reg);
 252                 if (enable)
 253                         l |= 1 << gpio;
 254                 else
 255                         l &= ~(1 << gpio);
 256                 break;
 257         case METHOD_GPIO_1610:
 258                 if (enable)
 259                         reg += OMAP1610_GPIO_SET_DATAOUT;
 260                 else
 261                         reg += OMAP1610_GPIO_CLEAR_DATAOUT;
 262                 l = 1 << gpio;
 263                 break;
 264         case METHOD_GPIO_730:
 265                 reg += OMAP730_GPIO_DATA_OUTPUT;
 266                 l = __raw_readl(reg);
 267                 if (enable)
 268                         l |= 1 << gpio;
 269                 else
 270                         l &= ~(1 << gpio);
 271                 break;
 272         default:
 273                 BUG();
 274                 return;
 275         }
 276         __raw_writel(l, reg);
 277 }
 278
 279 void omap_set_gpio_dataout(int gpio, int enable)
 280 {
 281         struct gpio_bank *bank;
 282
 283         if (check_gpio(gpio) < 0)
 284                 return;
 285         bank = get_gpio_bank(gpio);
 286         spin_lock(&bank->lock);
 287         _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
 288         spin_unlock(&bank->lock);
 289 }
 290
 291 int omap_get_gpio_datain(int gpio)
 292 {
 293         struct gpio_bank *bank;
 294         u32 reg;
 295
 296         if (check_gpio(gpio) < 0)
 297                 return -1;
 298         bank = get_gpio_bank(gpio);
 299         reg = bank->base;
 300         switch (bank->method) {
 301         case METHOD_MPUIO:
 302                 reg += OMAP_MPUIO_INPUT_LATCH;
 303                 break;
 304         case METHOD_GPIO_1510:
 305                 reg += OMAP1510_GPIO_DATA_INPUT;
 306                 break;
 307         case METHOD_GPIO_1610:
 308                 reg += OMAP1610_GPIO_DATAIN;
 309                 break;
 310         default:
 311                 BUG();
 312                 return -1;
 313         }
 314         return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
 315 }
 316
 317 static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge)
 318 {
 319         u32 reg = bank->base;
 320         u32 l;
 321
 322         switch (bank->method) {
 323         case METHOD_MPUIO:
 324                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
 325                 l = __raw_readl(reg);
 326                 if (edge == OMAP_GPIO_RISING_EDGE)
 327                         l |= 1 << gpio;
 328                 else
 329                         l &= ~(1 << gpio);
 330                 __raw_writel(l, reg);
 331                 break;
 332         case METHOD_GPIO_1510:
 333                 reg += OMAP1510_GPIO_INT_CONTROL;
 334                 l = __raw_readl(reg);
 335                 if (edge == OMAP_GPIO_RISING_EDGE)
 336                         l |= 1 << gpio;
 337                 else
 338                         l &= ~(1 << gpio);
 339                 __raw_writel(l, reg);
 340                 break;
 341         case METHOD_GPIO_1610:
 342                 edge &= 0x03;
 343                 if (gpio & 0x08)
 344                         reg += OMAP1610_GPIO_EDGE_CTRL2;
 345                 else
 346                         reg += OMAP1610_GPIO_EDGE_CTRL1;
 347                 gpio &= 0x07;
 348                 l = __raw_readl(reg);
 349                 l &= ~(3 << (gpio << 1));
 350                 l |= edge << (gpio << 1);
 351                 __raw_writel(l, reg);
 352                 break;
 353         case METHOD_GPIO_730:
 354                 reg += OMAP730_GPIO_INT_CONTROL;
 355                 l = __raw_readl(reg);
 356                 if (edge == OMAP_GPIO_RISING_EDGE)
 357                         l |= 1 << gpio;
 358                 else
 359                         l &= ~(1 << gpio);
 360                 __raw_writel(l, reg);
 361                 break;
 362         default:
 363                 BUG();
 364                 return;
 365         }
 366 }
 367
 368 void omap_set_gpio_edge_ctrl(int gpio, int edge)
 369 {
 370         struct gpio_bank *bank;
 371
 372         if (check_gpio(gpio) < 0)
 373                 return;
 374         bank = get_gpio_bank(gpio);
 375         spin_lock(&bank->lock);
 376         _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), edge);
 377         spin_unlock(&bank->lock);
 378 }
 379
 380
 381 static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio)
 382 {
 383         u32 reg = bank->base, l;
 384
 385         switch (bank->method) {
 386         case METHOD_MPUIO:
 387                 l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE);
 388                 return (l & (1 << gpio)) ?
 389                         OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
 390         case METHOD_GPIO_1510:
 391                 l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL);
 392                 return (l & (1 << gpio)) ?
 393                         OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
 394         case METHOD_GPIO_1610:
 395                 if (gpio & 0x08)
 396                         reg += OMAP1610_GPIO_EDGE_CTRL2;
 397                 else
 398                         reg += OMAP1610_GPIO_EDGE_CTRL1;
 399                 return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03;
 400         case METHOD_GPIO_730:
 401                 l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL);
 402                 return (l & (1 << gpio)) ?
 403                         OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE;
 404         default:
 405                 BUG();
 406                 return -1;
 407         }
 408 }
 409
 410 static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
 411 {
 412         u32 reg = bank->base;
 413
 414         switch (bank->method) {
 415         case METHOD_MPUIO:
 416                 /* MPUIO irqstatus cannot be cleared one bit at a time,
 417                  * so do nothing here */
 418                 return;
 419         case METHOD_GPIO_1510:
 420                 reg += OMAP1510_GPIO_INT_STATUS;
 421                 break;
 422         case METHOD_GPIO_1610:
 423                 reg += OMAP1610_GPIO_IRQSTATUS1;
 424                 break;
 425         case METHOD_GPIO_730:
 426                 reg += OMAP730_GPIO_INT_STATUS;
 427                 break;
 428         default:
 429                 BUG();
 430                 return;
 431         }
 432         __raw_writel(1 << get_gpio_index(gpio), reg);
 433 }
 434
 435 static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 436 {
 437         u32 reg = bank->base;
 438         u32 l;
 439
 440         switch (bank->method) {
 441         case METHOD_MPUIO:
 442                 reg += OMAP_MPUIO_GPIO_MASKIT;
 443                 l = __raw_readl(reg);
 444                 if (enable)
 445                         l &= ~(1 << gpio);
 446                 else
 447                         l |= 1 << gpio;
 448                 break;
 449         case METHOD_GPIO_1510:
 450                 reg += OMAP1510_GPIO_INT_MASK;
 451                 l = __raw_readl(reg);
 452                 if (enable)
 453                         l &= ~(1 << gpio);
 454                 else
 455                         l |= 1 << gpio;
 456                 break;
 457         case METHOD_GPIO_1610:
 458                 if (enable) {
 459                         reg += OMAP1610_GPIO_SET_IRQENABLE1;
 460                         _clear_gpio_irqstatus(bank, gpio);
 461                 } else
 462                         reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
 463                 l = 1 << gpio;
 464                 break;
 465         case METHOD_GPIO_730:
 466                 reg += OMAP730_GPIO_INT_MASK;
 467                 l = __raw_readl(reg);
 468                 if (enable)
 469                         l &= ~(1 << gpio);
 470                 else
 471                         l |= 1 << gpio;
 472                 break;
 473         default:
 474                 BUG();
 475                 return;
 476         }
 477         __raw_writel(l, reg);
 478 }
 479
 480 int omap_request_gpio(int gpio)
 481 {
 482         struct gpio_bank *bank;
 483
 484         if (check_gpio(gpio) < 0)
 485                 return -EINVAL;
 486
 487         bank = get_gpio_bank(gpio);
 488         spin_lock(&bank->lock);
 489         if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
 490                 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
 491                 dump_stack();
 492                 spin_unlock(&bank->lock);
 493                 return -1;
 494         }
 495         bank->reserved_map |= (1 << get_gpio_index(gpio));
 496 #ifdef CONFIG_ARCH_OMAP1510
 497         if (bank->method == METHOD_GPIO_1510) {
 498                 u32 reg;
 499
 500                 /* Claim the pin for the ARM */
 501                 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
 502                 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
 503         }
 504 #endif
 505         spin_unlock(&bank->lock);
 506
 507         return 0;
 508 }
 509
 510 void omap_free_gpio(int gpio)
 511 {
 512         struct gpio_bank *bank;
 513
 514         if (check_gpio(gpio) < 0)
 515                 return;
 516         bank = get_gpio_bank(gpio);
 517         spin_lock(&bank->lock);
 518         if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
 519                 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
 520                 dump_stack();
 521                 spin_unlock(&bank->lock);
 522                 return;
 523         }
 524         bank->reserved_map &= ~(1 << get_gpio_index(gpio));
 525         _set_gpio_direction(bank, get_gpio_index(gpio), 1);
 526         _set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
 527         spin_unlock(&bank->lock);
 528 }
 529
 530 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
 531                              struct pt_regs *regs)
 532 {
 533         u32 isr_reg = 0;
 534         struct gpio_bank *bank = (struct gpio_bank *) desc->data;
 535
 536         /*
 537          * Acknowledge the parent IRQ.
 538          */
 539         desc->chip->ack(irq);
 540
 541         /* Since the level 1 GPIO interrupt cascade (IRQ14) is configured as
 542          * edge-sensitive, we need to unmask it here in order to avoid missing
 543          * any additional GPIO interrupts that might occur after the last time
 544          * we check for pending GPIO interrupts here.
 545          * We are relying on the fact that this interrupt handler was installed
 546          * with the SA_INTERRUPT flag so that interrupts are disabled at the
 547          * CPU while it is executing.
 548          */
 549         desc->chip->unmask(irq);
 550
 551         if (bank->method == METHOD_MPUIO)
 552                 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
 553 #ifdef CONFIG_ARCH_OMAP1510
 554         if (bank->method == METHOD_GPIO_1510)
 555                 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
 556 #endif
 557 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 558         if (bank->method == METHOD_GPIO_1610)
 559                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
 560 #endif
 561 #ifdef CONFIG_ARCH_OMAP730
 562         if (bank->method == METHOD_GPIO_730)
 563                 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
 564 #endif
 565         for (;;) {
 566                 u32 isr = __raw_readl(isr_reg);
 567                 unsigned int gpio_irq;
 568
 569                 if (!isr)
 570                         break;
 571                 gpio_irq = bank->virtual_irq_start;
 572
 573                 for (; isr != 0; isr >>= 1, gpio_irq++) {
 574                         if (isr & 1) {
 575                                 struct irqdesc *d = irq_desc + gpio_irq;
 576                                 d->handle(gpio_irq, d, regs);
 577                         }
 578                 }
 579         }
 580 }
 581
 582 static void gpio_ack_irq(unsigned int irq)
 583 {
 584         unsigned int gpio = irq - IH_GPIO_BASE;
 585         struct gpio_bank *bank = get_gpio_bank(gpio);
 586
 587 #ifdef CONFIG_ARCH_OMAP1510
 588         if (bank->method == METHOD_GPIO_1510)
 589                 __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1510_GPIO_INT_STATUS);
 590 #endif
 591 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 592         if (bank->method == METHOD_GPIO_1610)
 593                 __raw_writew(1 << (gpio & 0x0f), bank->base + OMAP1610_GPIO_IRQSTATUS1);
 594 #endif
 595 #ifdef CONFIG_ARCH_OMAP730
 596         if (bank->method == METHOD_GPIO_730)
 597                 __raw_writel(1 << (gpio & 0x1f), bank->base + OMAP730_GPIO_INT_STATUS);
 598 #endif
 599 }
 600
 601 static void gpio_mask_irq(unsigned int irq)
 602 {
 603         unsigned int gpio = irq - IH_GPIO_BASE;
 604         struct gpio_bank *bank = get_gpio_bank(gpio);
 605
 606         _set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
 607 }
 608
 609 static void gpio_unmask_irq(unsigned int irq)
 610 {
 611         unsigned int gpio = irq - IH_GPIO_BASE;
 612         struct gpio_bank *bank = get_gpio_bank(gpio);
 613
 614         if (_get_gpio_edge_ctrl(bank, get_gpio_index(gpio)) == OMAP_GPIO_NO_EDGE) {
 615                 printk(KERN_ERR "OMAP GPIO %d: trying to enable GPIO IRQ while no edge is set\n",
 616                        gpio);
 617                 _set_gpio_edge_ctrl(bank, get_gpio_index(gpio), OMAP_GPIO_RISING_EDGE);
 618         }
 619         _set_gpio_irqenable(bank, get_gpio_index(gpio), 1);
 620 }
 621
 622 static void mpuio_ack_irq(unsigned int irq)
 623 {
 624         /* The ISR is reset automatically, so do nothing here. */
 625 }
 626
 627 static void mpuio_mask_irq(unsigned int irq)
 628 {
 629         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
 630         struct gpio_bank *bank = get_gpio_bank(gpio);
 631
 632         _set_gpio_irqenable(bank, get_gpio_index(gpio), 0);
 633 }
 634
 635 static void mpuio_unmask_irq(unsigned int irq)
 636 {
 637         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
 638         struct gpio_bank *bank = get_gpio_bank(gpio);
 639
 640         _set_gpio_irqenable(bank, get_gpio_index(gpio), 1);
 641 }
 642
 643 static struct irqchip gpio_irq_chip = {
 644         .ack    = gpio_ack_irq,
 645         .mask   = gpio_mask_irq,
 646         .unmask = gpio_unmask_irq,
 647 };
 648
 649 static struct irqchip mpuio_irq_chip = {
 650         .ack    = mpuio_ack_irq,
 651         .mask   = mpuio_mask_irq,
 652         .unmask = mpuio_unmask_irq
 653 };
 654
 655 static int initialized = 0;
 656
 657 static int __init _omap_gpio_init(void)
 658 {
 659         int i;
 660         struct gpio_bank *bank;
 661
 662         initialized = 1;
 663
 664 #ifdef CONFIG_ARCH_OMAP1510
 665         if (cpu_is_omap1510()) {
 666                 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
 667                 gpio_bank_count = 2;
 668                 gpio_bank = gpio_bank_1510;
 669         }
 670 #endif
 671 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 672         if (cpu_is_omap1610() || cpu_is_omap1710() || cpu_is_omap5912()) {
 673                 int rev;
 674
 675                 gpio_bank_count = 5;
 676                 gpio_bank = gpio_bank_1610;
 677                 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
 678                 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
 679                        (rev >> 4) & 0x0f, rev & 0x0f);
 680         }
 681 #endif
 682 #ifdef CONFIG_ARCH_OMAP730
 683         if (cpu_is_omap730()) {
 684                 printk(KERN_INFO "OMAP730 GPIO hardware\n");
 685                 gpio_bank_count = 7;
 686                 gpio_bank = gpio_bank_730;
 687         }
 688 #endif
 689         for (i = 0; i < gpio_bank_count; i++) {
 690                 int j, gpio_count = 16;
 691
 692                 bank = &gpio_bank[i];
 693                 bank->reserved_map = 0;
 694                 bank->base = IO_ADDRESS(bank->base);
 695                 spin_lock_init(&bank->lock);
 696                 if (bank->method == METHOD_MPUIO) {
 697                         omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
 698                 }
 699 #ifdef CONFIG_ARCH_OMAP1510
 700                 if (bank->method == METHOD_GPIO_1510) {
 701                         __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
 702                         __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
 703                 }
 704 #endif
 705 #if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP1710) || defined(CONFIG_ARCH_OMAP5912)
 706                 if (bank->method == METHOD_GPIO_1610) {
 707                         __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
 708                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
 709                 }
 710 #endif
 711 #ifdef CONFIG_ARCH_OMAP730
 712                 if (bank->method == METHOD_GPIO_730) {
 713                         __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
 714                         __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
 715
 716                         gpio_count = 32; /* 730 has 32-bit GPIOs */
 717                 }
 718 #endif
 719                 for (j = bank->virtual_irq_start;
 720                      j < bank->virtual_irq_start + gpio_count; j++) {
 721                         if (bank->method == METHOD_MPUIO)
 722                                 set_irq_chip(j, &mpuio_irq_chip);
 723                         else
 724                                 set_irq_chip(j, &gpio_irq_chip);
 725                         set_irq_handler(j, do_level_IRQ);
 726                         set_irq_flags(j, IRQF_VALID);
 727                 }
 728                 set_irq_chained_handler(bank->irq, gpio_irq_handler);
 729                 set_irq_data(bank->irq, bank);
 730         }
 731
 732         /* Enable system clock for GPIO module.
 733          * The CAM_CLK_CTRL *is* really the right place. */
 734         if (cpu_is_omap1610() || cpu_is_omap1710())
 735                 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
 736
 737         return 0;
 738 }
 739
 740 /*
 741  * This may get called early from board specific init
 742  */
 743 int omap_gpio_init(void)
 744 {
 745         if (!initialized)
 746                 return _omap_gpio_init();
 747         else
 748                 return 0;
 749 }
 750
 751 EXPORT_SYMBOL(omap_request_gpio);
 752 EXPORT_SYMBOL(omap_free_gpio);
 753 EXPORT_SYMBOL(omap_set_gpio_direction);
 754 EXPORT_SYMBOL(omap_set_gpio_dataout);
 755 EXPORT_SYMBOL(omap_get_gpio_datain);
 756 EXPORT_SYMBOL(omap_set_gpio_edge_ctrl);
 757
 758 arch_initcall(omap_gpio_init);