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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / arch / arm / mach-integrator / integrator_cp.c
blob0f5fc786167b62cf35abfd537b36b5ada935d561
1 /*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/sysdev.h>
19
20 #include <asm/hardware.h>
21 #include <asm/io.h>
22 #include <asm/irq.h>
23 #include <asm/setup.h>
24 #include <asm/mach-types.h>
25 #include <asm/hardware/amba.h>
26 #include <asm/hardware/amba_kmi.h>
27 #include <asm/hardware/amba_clcd.h>
28 #include <asm/hardware/icst525.h>
29
30 #include <asm/arch/cm.h>
31 #include <asm/arch/lm.h>
32
33 #include <asm/mach/arch.h>
34 #include <asm/mach/flash.h>
35 #include <asm/mach/irq.h>
36 #include <asm/mach/mmc.h>
37 #include <asm/mach/map.h>
38
39 #include "clock.h"
40
41 #define INTCP_PA_MMC_BASE 0x1c000000
42 #define INTCP_PA_AACI_BASE 0x1d000000
43
44 #define INTCP_PA_FLASH_BASE 0x24000000
45 #define INTCP_FLASH_SIZE SZ_32M
46
47 #define INTCP_PA_CLCD_BASE 0xc0000000
48
49 #define INTCP_VA_CIC_BASE 0xf1000040
50 #define INTCP_VA_PIC_BASE 0xf1400000
51 #define INTCP_VA_SIC_BASE 0xfca00000
52
53 #define INTCP_PA_ETH_BASE 0xc8000000
54 #define INTCP_ETH_SIZE 0x10
55
56 #define INTCP_VA_CTRL_BASE 0xfcb00000
57 #define INTCP_FLASHPROG 0x04
58 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
59 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
60
61 /*
62 * Logical Physical
63 * f1000000 10000000 Core module registers
64 * f1100000 11000000 System controller registers
65 * f1200000 12000000 EBI registers
66 * f1300000 13000000 Counter/Timer
67 * f1400000 14000000 Interrupt controller
68 * f1600000 16000000 UART 0
69 * f1700000 17000000 UART 1
70 * f1a00000 1a000000 Debug LEDs
71 * f1b00000 1b000000 GPIO
72 */
73
74 static struct map_desc intcp_io_desc[] __initdata = {
75 { IO_ADDRESS(INTEGRATOR_HDR_BASE), INTEGRATOR_HDR_BASE, SZ_4K, MT_DEVICE },
76 { IO_ADDRESS(INTEGRATOR_SC_BASE), INTEGRATOR_SC_BASE, SZ_4K, MT_DEVICE },
77 { IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
78 { IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
79 { IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
80 { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
81 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
82 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
83 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
84 { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
85 { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
86 { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
87 };
88
89 static void __init intcp_map_io(void)
90 {
91 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
92 }
93
94 #define cic_writel __raw_writel
95 #define cic_readl __raw_readl
96 #define pic_writel __raw_writel
97 #define pic_readl __raw_readl
98 #define sic_writel __raw_writel
99 #define sic_readl __raw_readl
100
101 static void cic_mask_irq(unsigned int irq)
102 {
103 irq -= IRQ_CIC_START;
104 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
105 }
106
107 static void cic_unmask_irq(unsigned int irq)
108 {
109 irq -= IRQ_CIC_START;
110 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
111 }
112
113 static struct irqchip cic_chip = {
114 .ack = cic_mask_irq,
115 .mask = cic_mask_irq,
116 .unmask = cic_unmask_irq,
117 };
118
119 static void pic_mask_irq(unsigned int irq)
120 {
121 irq -= IRQ_PIC_START;
122 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
123 }
124
125 static void pic_unmask_irq(unsigned int irq)
126 {
127 irq -= IRQ_PIC_START;
128 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
129 }
130
131 static struct irqchip pic_chip = {
132 .ack = pic_mask_irq,
133 .mask = pic_mask_irq,
134 .unmask = pic_unmask_irq,
135 };
136
137 static void sic_mask_irq(unsigned int irq)
138 {
139 irq -= IRQ_SIC_START;
140 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
141 }
142
143 static void sic_unmask_irq(unsigned int irq)
144 {
145 irq -= IRQ_SIC_START;
146 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
147 }
148
149 static struct irqchip sic_chip = {
150 .ack = sic_mask_irq,
151 .mask = sic_mask_irq,
152 .unmask = sic_unmask_irq,
153 };
154
155 static void
156 sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
157 {
158 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
159
160 if (status == 0) {
161 do_bad_IRQ(irq, desc, regs);
162 return;
163 }
164
165 do {
166 irq = ffs(status) - 1;
167 status &= ~(1 << irq);
168
169 irq += IRQ_SIC_START;
170
171 desc = irq_desc + irq;
172 desc->handle(irq, desc, regs);
173 } while (status);
174 }
175
176 static void __init intcp_init_irq(void)
177 {
178 unsigned int i;
179
180 /*
181 * Disable all interrupt sources
182 */
183 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
184 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
185
186 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
187 if (i == 11)
188 i = 22;
189 if (i == IRQ_CP_CPPLDINT)
190 i++;
191 if (i == 29)
192 break;
193 set_irq_chip(i, &pic_chip);
194 set_irq_handler(i, do_level_IRQ);
195 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
196 }
197
198 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
199 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
200
201 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
202 set_irq_chip(i, &cic_chip);
203 set_irq_handler(i, do_level_IRQ);
204 set_irq_flags(i, IRQF_VALID);
205 }
206
207 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
208 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
209
210 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
211 set_irq_chip(i, &sic_chip);
212 set_irq_handler(i, do_level_IRQ);
213 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
214 }
215
216 set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
217 pic_unmask_irq(IRQ_CP_CPPLDINT);
218 }
219
220 /*
221 * Clock handling
222 */
223 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
224 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
225
226 static const struct icst525_params cp_auxvco_params = {
227 .ref = 24000,
228 .vco_max = 320000,
229 .vd_min = 8,
230 .vd_max = 263,
231 .rd_min = 3,
232 .rd_max = 65,
233 };
234
235 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
236 {
237 u32 val;
238
239 val = readl(CM_AUXOSC) & ~0x7ffff;
240 val |= vco.v | (vco.r << 9) | (vco.s << 16);
241
242 writel(0xa05f, CM_LOCK);
243 writel(val, CM_AUXOSC);
244 writel(0, CM_LOCK);
245 }
246
247 static struct clk cp_clcd_clk = {
248 .name = "CLCDCLK",
249 .params = &cp_auxvco_params,
250 .setvco = cp_auxvco_set,
251 };
252
253 static struct clk cp_mmci_clk = {
254 .name = "MCLK",
255 .rate = 14745600,
256 };
257
258 /*
259 * Flash handling.
260 */
261 static int intcp_flash_init(void)
262 {
263 u32 val;
264
265 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
266 val |= CINTEGRATOR_FLASHPROG_FLWREN;
267 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
268
269 return 0;
270 }
271
272 static void intcp_flash_exit(void)
273 {
274 u32 val;
275
276 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
277 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
278 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
279 }
280
281 static void intcp_flash_set_vpp(int on)
282 {
283 u32 val;
284
285 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
286 if (on)
287 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
288 else
289 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
290 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
291 }
292
293 static struct flash_platform_data intcp_flash_data = {
294 .map_name = "cfi_probe",
295 .width = 4,
296 .init = intcp_flash_init,
297 .exit = intcp_flash_exit,
298 .set_vpp = intcp_flash_set_vpp,
299 };
300
301 static struct resource intcp_flash_resource = {
302 .start = INTCP_PA_FLASH_BASE,
303 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
304 .flags = IORESOURCE_MEM,
305 };
306
307 static struct platform_device intcp_flash_device = {
308 .name = "armflash",
309 .id = 0,
310 .dev = {
311 .platform_data = &intcp_flash_data,
312 },
313 .num_resources = 1,
314 .resource = &intcp_flash_resource,
315 };
316
317 static struct resource smc91x_resources[] = {
318 [0] = {
319 .start = INTCP_PA_ETH_BASE,
320 .end = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
321 .flags = IORESOURCE_MEM,
322 },
323 [1] = {
324 .start = IRQ_CP_ETHINT,
325 .end = IRQ_CP_ETHINT,
326 .flags = IORESOURCE_IRQ,
327 },
328 };
329
330 static struct platform_device smc91x_device = {
331 .name = "smc91x",
332 .id = 0,
333 .num_resources = ARRAY_SIZE(smc91x_resources),
334 .resource = smc91x_resources,
335 };
336
337 static struct platform_device *intcp_devs[] __initdata = {
338 &intcp_flash_device,
339 &smc91x_device,
340 };
341
342 /*
343 * It seems that the card insertion interrupt remains active after
344 * we've acknowledged it. We therefore ignore the interrupt, and
345 * rely on reading it from the SIC. This also means that we must
346 * clear the latched interrupt.
347 */
348 static unsigned int mmc_status(struct device *dev)
349 {
350 unsigned int status = readl(0xfca00004);
351 writel(8, 0xfcb00008);
352
353 return status & 8;
354 }
355
356 static struct mmc_platform_data mmc_data = {
357 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
358 .status = mmc_status,
359 };
360
361 static struct amba_device mmc_device = {
362 .dev = {
363 .bus_id = "mb:1c",
364 .platform_data = &mmc_data,
365 },
366 .res = {
367 .start = INTCP_PA_MMC_BASE,
368 .end = INTCP_PA_MMC_BASE + SZ_4K - 1,
369 .flags = IORESOURCE_MEM,
370 },
371 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
372 .periphid = 0,
373 };
374
375 static struct amba_device aaci_device = {
376 .dev = {
377 .bus_id = "mb:1d",
378 },
379 .res = {
380 .start = INTCP_PA_AACI_BASE,
381 .end = INTCP_PA_AACI_BASE + SZ_4K - 1,
382 .flags = IORESOURCE_MEM,
383 },
384 .irq = { IRQ_CP_AACIINT, NO_IRQ },
385 .periphid = 0,
386 };
387
388
389 /*
390 * CLCD support
391 */
392 static struct clcd_panel vga = {
393 .mode = {
394 .name = "VGA",
395 .refresh = 60,
396 .xres = 640,
397 .yres = 480,
398 .pixclock = 39721,
399 .left_margin = 40,
400 .right_margin = 24,
401 .upper_margin = 32,
402 .lower_margin = 11,
403 .hsync_len = 96,
404 .vsync_len = 2,
405 .sync = 0,
406 .vmode = FB_VMODE_NONINTERLACED,
407 },
408 .width = -1,
409 .height = -1,
410 .tim2 = TIM2_BCD | TIM2_IPC,
411 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
412 .bpp = 16,
413 .grayscale = 0,
414 };
415
416 /*
417 * Ensure VGA is selected.
418 */
419 static void cp_clcd_enable(struct clcd_fb *fb)
420 {
421 cm_control(CM_CTRL_LCDMUXSEL_MASK, CM_CTRL_LCDMUXSEL_VGA);
422 }
423
424 static unsigned long framesize = SZ_1M;
425
426 static int cp_clcd_setup(struct clcd_fb *fb)
427 {
428 dma_addr_t dma;
429
430 fb->panel = &vga;
431
432 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
433 &dma, GFP_KERNEL);
434 if (!fb->fb.screen_base) {
435 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
436 return -ENOMEM;
437 }
438
439 fb->fb.fix.smem_start = dma;
440 fb->fb.fix.smem_len = framesize;
441
442 return 0;
443 }
444
445 static void cp_clcd_remove(struct clcd_fb *fb)
446 {
447 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
448 fb->fb.screen_base, fb->fb.fix.smem_start);
449 }
450
451 static struct clcd_board clcd_data = {
452 .name = "Integrator/CP",
453 .check = clcdfb_check,
454 .decode = clcdfb_decode,
455 .enable = cp_clcd_enable,
456 .setup = cp_clcd_setup,
457 .remove = cp_clcd_remove,
458 };
459
460 static struct amba_device clcd_device = {
461 .dev = {
462 .bus_id = "mb:c0",
463 .coherent_dma_mask = ~0,
464 .platform_data = &clcd_data,
465 },
466 .res = {
467 .start = INTCP_PA_CLCD_BASE,
468 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 .dma_mask = ~0,
472 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
473 .periphid = 0,
474 };
475
476 static struct amba_device *amba_devs[] __initdata = {
477 &mmc_device,
478 &aaci_device,
479 &clcd_device,
480 };
481
482 static void __init intcp_init(void)
483 {
484 int i;
485
486 clk_register(&cp_clcd_clk);
487 clk_register(&cp_mmci_clk);
488
489 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
490
491 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
492 struct amba_device *d = amba_devs[i];
493 amba_device_register(d, &iomem_resource);
494 }
495 }
496
497 #define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
498
499 static void __init intcp_init_time(void)
500 {
501 integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
502 }
503
504 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
505 MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
506 BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
507 BOOT_PARAMS(0x00000100)
508 MAPIO(intcp_map_io)
509 INITIRQ(intcp_init_irq)
510 INITTIME(intcp_init_time)
511 INIT_MACHINE(intcp_init)
512 MACHINE_END
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