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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / scsi / sata_nv.c
blobaef957b523f9982bbe141c2be545680345e8e16e
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
10 * by reference.
11 *
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
22 *
23 * 0.03
24 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
25 * mmio_base, which is only set for the CK804/MCP04 case.
26 *
27 * 0.02
28 * - Added support for CK804 SATA controller.
29 *
30 * 0.01
31 * - Initial revision.
32 */
33
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include "scsi.h"
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.03"
48
49 #define NV_PORTS 2
50 #define NV_PIO_MASK 0x1f
51 #define NV_MWDMA_MASK 0x07
52 #define NV_UDMA_MASK 0x7f
53 #define NV_PORT0_SCR_REG_OFFSET 0x00
54 #define NV_PORT1_SCR_REG_OFFSET 0x40
55
56 #define NV_INT_STATUS 0x10
57 #define NV_INT_STATUS_CK804 0x440
58 #define NV_INT_STATUS_PDEV_INT 0x01
59 #define NV_INT_STATUS_PDEV_PM 0x02
60 #define NV_INT_STATUS_PDEV_ADDED 0x04
61 #define NV_INT_STATUS_PDEV_REMOVED 0x08
62 #define NV_INT_STATUS_SDEV_INT 0x10
63 #define NV_INT_STATUS_SDEV_PM 0x20
64 #define NV_INT_STATUS_SDEV_ADDED 0x40
65 #define NV_INT_STATUS_SDEV_REMOVED 0x80
66 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
67 NV_INT_STATUS_PDEV_REMOVED)
68 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
69 NV_INT_STATUS_SDEV_REMOVED)
70 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
71 NV_INT_STATUS_SDEV_HOTPLUG)
72
73 #define NV_INT_ENABLE 0x11
74 #define NV_INT_ENABLE_CK804 0x441
75 #define NV_INT_ENABLE_PDEV_MASK 0x01
76 #define NV_INT_ENABLE_PDEV_PM 0x02
77 #define NV_INT_ENABLE_PDEV_ADDED 0x04
78 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
79 #define NV_INT_ENABLE_SDEV_MASK 0x10
80 #define NV_INT_ENABLE_SDEV_PM 0x20
81 #define NV_INT_ENABLE_SDEV_ADDED 0x40
82 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
83 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
84 NV_INT_ENABLE_PDEV_REMOVED)
85 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
86 NV_INT_ENABLE_SDEV_REMOVED)
87 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
88 NV_INT_ENABLE_SDEV_HOTPLUG)
89
90 #define NV_INT_CONFIG 0x12
91 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
92
93 // For PCI config register 20
94 #define NV_MCP_SATA_CFG_20 0x50
95 #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
96
97 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
98 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
99 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
100 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
101 static void nv_host_stop (struct ata_host_set *host_set);
102 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
103 static void nv_disable_hotplug(struct ata_host_set *host_set);
104 static void nv_check_hotplug(struct ata_host_set *host_set);
105 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
106 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
107 static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
108
109 enum nv_host_type
110 {
111 NFORCE2,
112 NFORCE3,
113 CK804
114 };
115
116 static struct pci_device_id nv_pci_tbl[] = {
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
131 { 0, } /* terminate list */
132 };
133
134 #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
135
136 struct nv_host_desc
137 {
138 enum nv_host_type host_type;
139 unsigned long host_flags;
140 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
141 void (*disable_hotplug)(struct ata_host_set *host_set);
142 void (*check_hotplug)(struct ata_host_set *host_set);
143
144 };
145 static struct nv_host_desc nv_device_tbl[] = {
146 {
147 .host_type = NFORCE2,
148 .host_flags = 0x00000000,
149 .enable_hotplug = nv_enable_hotplug,
150 .disable_hotplug= nv_disable_hotplug,
151 .check_hotplug = nv_check_hotplug,
152 },
153 {
154 .host_type = NFORCE3,
155 .host_flags = 0x00000000,
156 .enable_hotplug = nv_enable_hotplug,
157 .disable_hotplug= nv_disable_hotplug,
158 .check_hotplug = nv_check_hotplug,
159 },
160 { .host_type = CK804,
161 .host_flags = NV_HOST_FLAGS_SCR_MMIO,
162 .enable_hotplug = nv_enable_hotplug_ck804,
163 .disable_hotplug= nv_disable_hotplug_ck804,
164 .check_hotplug = nv_check_hotplug_ck804,
165 },
166 };
167
168 struct nv_host
169 {
170 struct nv_host_desc *host_desc;
171 };
172
173 static struct pci_driver nv_pci_driver = {
174 .name = DRV_NAME,
175 .id_table = nv_pci_tbl,
176 .probe = nv_init_one,
177 .remove = ata_pci_remove_one,
178 };
179
180 static Scsi_Host_Template nv_sht = {
181 .module = THIS_MODULE,
182 .name = DRV_NAME,
183 .ioctl = ata_scsi_ioctl,
184 .queuecommand = ata_scsi_queuecmd,
185 .eh_strategy_handler = ata_scsi_error,
186 .can_queue = ATA_DEF_QUEUE,
187 .this_id = ATA_SHT_THIS_ID,
188 .sg_tablesize = LIBATA_MAX_PRD,
189 .max_sectors = ATA_MAX_SECTORS,
190 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
191 .emulated = ATA_SHT_EMULATED,
192 .use_clustering = ATA_SHT_USE_CLUSTERING,
193 .proc_name = DRV_NAME,
194 .dma_boundary = ATA_DMA_BOUNDARY,
195 .slave_configure = ata_scsi_slave_config,
196 .bios_param = ata_std_bios_param,
197 };
198
199 static struct ata_port_operations nv_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = ata_tf_load,
202 .tf_read = ata_tf_read,
203 .exec_command = ata_exec_command,
204 .check_status = ata_check_status,
205 .dev_select = ata_std_dev_select,
206 .phy_reset = sata_phy_reset,
207 .bmdma_setup = ata_bmdma_setup,
208 .bmdma_start = ata_bmdma_start,
209 .qc_prep = ata_qc_prep,
210 .qc_issue = ata_qc_issue_prot,
211 .eng_timeout = ata_eng_timeout,
212 .irq_handler = nv_interrupt,
213 .irq_clear = ata_bmdma_irq_clear,
214 .scr_read = nv_scr_read,
215 .scr_write = nv_scr_write,
216 .port_start = ata_port_start,
217 .port_stop = ata_port_stop,
218 .host_stop = nv_host_stop,
219 };
220
221 static struct ata_port_info nv_port_info = {
222 .sht = &nv_sht,
223 .host_flags = ATA_FLAG_SATA |
224 ATA_FLAG_SATA_RESET |
225 ATA_FLAG_SRST |
226 ATA_FLAG_NO_LEGACY,
227 .pio_mask = NV_PIO_MASK,
228 .mwdma_mask = NV_MWDMA_MASK,
229 .udma_mask = NV_UDMA_MASK,
230 .port_ops = &nv_ops,
231 };
232
233 MODULE_AUTHOR("NVIDIA");
234 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
235 MODULE_LICENSE("GPL");
236 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
237
238 irqreturn_t nv_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
239 {
240 struct ata_host_set *host_set = dev_instance;
241 struct nv_host *host = host_set->private_data;
242 unsigned int i;
243 unsigned int handled = 0;
244 unsigned long flags;
245
246 spin_lock_irqsave(&host_set->lock, flags);
247
248 for (i = 0; i < host_set->n_ports; i++) {
249 struct ata_port *ap;
250
251 ap = host_set->ports[i];
252 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
253 struct ata_queued_cmd *qc;
254
255 qc = ata_qc_from_tag(ap, ap->active_tag);
256 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
257 handled += ata_host_intr(ap, qc);
258 }
259
260 }
261
262 if (host->host_desc->check_hotplug)
263 host->host_desc->check_hotplug(host_set);
264
265 spin_unlock_irqrestore(&host_set->lock, flags);
266
267 return IRQ_RETVAL(handled);
268 }
269
270 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
271 {
272 struct ata_host_set *host_set = ap->host_set;
273 struct nv_host *host = host_set->private_data;
274
275 if (sc_reg > SCR_CONTROL)
276 return 0xffffffffU;
277
278 if (host->host_desc->host_flags & NV_HOST_FLAGS_SCR_MMIO)
279 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
280 else
281 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
282 }
283
284 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
285 {
286 struct ata_host_set *host_set = ap->host_set;
287 struct nv_host *host = host_set->private_data;
288
289 if (sc_reg > SCR_CONTROL)
290 return;
291
292 if (host->host_desc->host_flags & NV_HOST_FLAGS_SCR_MMIO)
293 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
294 else
295 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
296 }
297
298 static void nv_host_stop (struct ata_host_set *host_set)
299 {
300 struct nv_host *host = host_set->private_data;
301
302 // Disable hotplug event interrupts.
303 if (host->host_desc->disable_hotplug)
304 host->host_desc->disable_hotplug(host_set);
305
306 kfree(host);
307 }
308
309 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
310 {
311 static int printed_version = 0;
312 struct nv_host *host;
313 struct ata_port_info *ppi;
314 struct ata_probe_ent *probe_ent = NULL;
315 int rc;
316
317 if (!printed_version++)
318 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
319
320 rc = pci_enable_device(pdev);
321 if (rc)
322 return rc;
323
324 rc = pci_request_regions(pdev, DRV_NAME);
325 if (rc)
326 goto err_out;
327
328 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
329 if (rc)
330 goto err_out_regions;
331 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
332 if (rc)
333 goto err_out_regions;
334
335 ppi = &nv_port_info;
336 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
337 if (!probe_ent) {
338 rc = -ENOMEM;
339 goto err_out_regions;
340 }
341
342 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
343 if (!host) {
344 rc = -ENOMEM;
345 goto err_out_free_ent;
346 }
347
348 host->host_desc = &nv_device_tbl[ent->driver_data];
349
350 probe_ent->private_data = host;
351
352 if (host->host_desc->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
353 unsigned long base;
354
355 probe_ent->mmio_base = ioremap(pci_resource_start(pdev, 5),
356 pci_resource_len(pdev, 5));
357 if (probe_ent->mmio_base == NULL)
358 goto err_out_iounmap;
359
360 base = (unsigned long)probe_ent->mmio_base;
361
362 probe_ent->port[0].scr_addr =
363 base + NV_PORT0_SCR_REG_OFFSET;
364 probe_ent->port[1].scr_addr =
365 base + NV_PORT1_SCR_REG_OFFSET;
366 } else {
367
368 probe_ent->port[0].scr_addr =
369 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
370 probe_ent->port[1].scr_addr =
371 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
372 }
373
374 pci_set_master(pdev);
375
376 // Enable hotplug event interrupts.
377 if (host->host_desc->enable_hotplug)
378 host->host_desc->enable_hotplug(probe_ent);
379
380 rc = ata_device_add(probe_ent);
381 if (rc != NV_PORTS)
382 goto err_out_iounmap;
383
384 kfree(probe_ent);
385
386 return 0;
387
388 err_out_iounmap:
389 if (host->host_desc->host_flags & NV_HOST_FLAGS_SCR_MMIO)
390 iounmap(probe_ent->mmio_base);
391
392 err_out_free_ent:
393 kfree(probe_ent);
394
395 err_out_regions:
396 pci_release_regions(pdev);
397
398 err_out:
399 pci_disable_device(pdev);
400 return rc;
401 }
402
403 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
404 {
405 u8 intr_mask;
406
407 outb(NV_INT_STATUS_HOTPLUG,
408 probe_ent->port[0].scr_addr + NV_INT_STATUS);
409
410 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
411 intr_mask |= NV_INT_ENABLE_HOTPLUG;
412
413 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
414 }
415
416 static void nv_disable_hotplug(struct ata_host_set *host_set)
417 {
418 u8 intr_mask;
419
420 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
421
422 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
423
424 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
425 }
426
427 static void nv_check_hotplug(struct ata_host_set *host_set)
428 {
429 u8 intr_status;
430
431 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
432
433 // Clear interrupt status.
434 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
435
436 if (intr_status & NV_INT_STATUS_HOTPLUG) {
437 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
438 printk(KERN_WARNING "nv_sata: "
439 "Primary device added\n");
440
441 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
442 printk(KERN_WARNING "nv_sata: "
443 "Primary device removed\n");
444
445 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
446 printk(KERN_WARNING "nv_sata: "
447 "Secondary device added\n");
448
449 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
450 printk(KERN_WARNING "nv_sata: "
451 "Secondary device removed\n");
452 }
453 }
454
455 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
456 {
457 u8 intr_mask;
458 u8 regval;
459
460 pci_read_config_byte(probe_ent->pdev, NV_MCP_SATA_CFG_20, &regval);
461 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
462 pci_write_config_byte(probe_ent->pdev, NV_MCP_SATA_CFG_20, regval);
463
464 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
465
466 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
467 intr_mask |= NV_INT_ENABLE_HOTPLUG;
468
469 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
470 }
471
472 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
473 {
474 u8 intr_mask;
475 u8 regval;
476
477 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
478
479 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
480
481 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
482
483 pci_read_config_byte(host_set->pdev, NV_MCP_SATA_CFG_20, &regval);
484 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
485 pci_write_config_byte(host_set->pdev, NV_MCP_SATA_CFG_20, regval);
486 }
487
488 static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
489 {
490 u8 intr_status;
491
492 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
493
494 // Clear interrupt status.
495 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
496
497 if (intr_status & NV_INT_STATUS_HOTPLUG) {
498 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
499 printk(KERN_WARNING "nv_sata: "
500 "Primary device added\n");
501
502 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
503 printk(KERN_WARNING "nv_sata: "
504 "Primary device removed\n");
505
506 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
507 printk(KERN_WARNING "nv_sata: "
508 "Secondary device added\n");
509
510 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
511 printk(KERN_WARNING "nv_sata: "
512 "Secondary device removed\n");
513 }
514 }
515
516 static int __init nv_init(void)
517 {
518 return pci_module_init(&nv_pci_driver);
519 }
520
521 static void __exit nv_exit(void)
522 {
523 pci_unregister_driver(&nv_pci_driver);
524 }
525
526 module_init(nv_init);
527 module_exit(nv_exit);
MOXA 2.6.9 from sdlinux-moxaart.tgz