?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / scsi / ata_piix.c
blobadad8d394992ca71e6fe79f9a2da58df2619fd0e
1 /*
2
3 ata_piix.c - Intel PATA/SATA controllers
4
5 Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 Please ALWAYS copy linux-ide@vger.kernel.org
7 on emails.
8
9
10 Copyright 2003-2004 Red Hat Inc
11 Copyright 2003-2004 Jeff Garzik
12
13
14 Copyright header from piix.c:
15
16 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
17 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
18 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
19
20 May be copied or modified under the terms of the GNU General Public License
21
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include "scsi.h"
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
33
34 #define DRV_NAME "ata_piix"
35 #define DRV_VERSION "1.02"
36
37 enum {
38 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
39 ICH5_PMR = 0x90, /* port mapping register */
40 ICH5_PCS = 0x92, /* port control and status */
41
42 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
43 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
44 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
45
46 /* combined mode. if set, PATA is channel 0.
47 * if clear, PATA is channel 1.
48 */
49 PIIX_COMB_PATA_P0 = (1 << 1),
50 PIIX_COMB = (1 << 2), /* combined mode enabled? */
51
52 PIIX_PORT_PRESENT = (1 << 0),
53 PIIX_PORT_ENABLED = (1 << 4),
54
55 PIIX_80C_PRI = (1 << 5) | (1 << 4),
56 PIIX_80C_SEC = (1 << 7) | (1 << 6),
57
58 ich5_pata = 0,
59 ich5_sata = 1,
60 piix4_pata = 2,
61 ich6_sata = 3,
62 ich6_sata_rm = 4,
63 };
64
65 static int piix_init_one (struct pci_dev *pdev,
66 const struct pci_device_id *ent);
67
68 static void piix_pata_phy_reset(struct ata_port *ap);
69 static void piix_sata_phy_reset(struct ata_port *ap);
70 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
71 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
72
73 static unsigned int in_module_init = 1;
74
75 static struct pci_device_id piix_pci_tbl[] = {
76 #ifdef ATA_ENABLE_PATA
77 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
78 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
79 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
80 #endif
81
82 /* NOTE: The following PCI ids must be kept in sync with the
83 * list in drivers/pci/quirks.c.
84 */
85
86 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
87 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
88 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
89 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
90 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
91 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
92 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
93
94 { } /* terminate list */
95 };
96
97 static struct pci_driver piix_pci_driver = {
98 .name = DRV_NAME,
99 .id_table = piix_pci_tbl,
100 .probe = piix_init_one,
101 .remove = ata_pci_remove_one,
102 };
103
104 static Scsi_Host_Template piix_sht = {
105 .module = THIS_MODULE,
106 .name = DRV_NAME,
107 .ioctl = ata_scsi_ioctl,
108 .queuecommand = ata_scsi_queuecmd,
109 .eh_strategy_handler = ata_scsi_error,
110 .can_queue = ATA_DEF_QUEUE,
111 .this_id = ATA_SHT_THIS_ID,
112 .sg_tablesize = LIBATA_MAX_PRD,
113 .max_sectors = ATA_MAX_SECTORS,
114 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
115 .emulated = ATA_SHT_EMULATED,
116 .use_clustering = ATA_SHT_USE_CLUSTERING,
117 .proc_name = DRV_NAME,
118 .dma_boundary = ATA_DMA_BOUNDARY,
119 .slave_configure = ata_scsi_slave_config,
120 .bios_param = ata_std_bios_param,
121 };
122
123 static struct ata_port_operations piix_pata_ops = {
124 .port_disable = ata_port_disable,
125 .set_piomode = piix_set_piomode,
126 .set_dmamode = piix_set_dmamode,
127
128 .tf_load = ata_tf_load,
129 .tf_read = ata_tf_read,
130 .check_status = ata_check_status,
131 .exec_command = ata_exec_command,
132 .dev_select = ata_std_dev_select,
133
134 .phy_reset = piix_pata_phy_reset,
135
136 .bmdma_setup = ata_bmdma_setup,
137 .bmdma_start = ata_bmdma_start,
138 .qc_prep = ata_qc_prep,
139 .qc_issue = ata_qc_issue_prot,
140
141 .eng_timeout = ata_eng_timeout,
142
143 .irq_handler = ata_interrupt,
144 .irq_clear = ata_bmdma_irq_clear,
145
146 .port_start = ata_port_start,
147 .port_stop = ata_port_stop,
148 };
149
150 static struct ata_port_operations piix_sata_ops = {
151 .port_disable = ata_port_disable,
152
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
158
159 .phy_reset = piix_sata_phy_reset,
160
161 .bmdma_setup = ata_bmdma_setup,
162 .bmdma_start = ata_bmdma_start,
163 .qc_prep = ata_qc_prep,
164 .qc_issue = ata_qc_issue_prot,
165
166 .eng_timeout = ata_eng_timeout,
167
168 .irq_handler = ata_interrupt,
169 .irq_clear = ata_bmdma_irq_clear,
170
171 .port_start = ata_port_start,
172 .port_stop = ata_port_stop,
173 };
174
175 static struct ata_port_info piix_port_info[] = {
176 /* ich5_pata */
177 {
178 .sht = &piix_sht,
179 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
180 PIIX_FLAG_CHECKINTR,
181 .pio_mask = 0x1f, /* pio0-4 */
182 #if 0
183 .mwdma_mask = 0x06, /* mwdma1-2 */
184 #else
185 .mwdma_mask = 0x00, /* mwdma broken */
186 #endif
187 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
188 .port_ops = &piix_pata_ops,
189 },
190
191 /* ich5_sata */
192 {
193 .sht = &piix_sht,
194 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
195 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
196 .pio_mask = 0x1f, /* pio0-4 */
197 .mwdma_mask = 0x07, /* mwdma0-2 */
198 .udma_mask = 0x7f, /* udma0-6 */
199 .port_ops = &piix_sata_ops,
200 },
201
202 /* piix4_pata */
203 {
204 .sht = &piix_sht,
205 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
206 .pio_mask = 0x1f, /* pio0-4 */
207 #if 0
208 .mwdma_mask = 0x06, /* mwdma1-2 */
209 #else
210 .mwdma_mask = 0x00, /* mwdma broken */
211 #endif
212 .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
213 .port_ops = &piix_pata_ops,
214 },
215
216 /* ich6_sata */
217 {
218 .sht = &piix_sht,
219 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
220 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
221 ATA_FLAG_SLAVE_POSS,
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = 0x7f, /* udma0-6 */
225 .port_ops = &piix_sata_ops,
226 },
227
228 /* ich6_sata_rm */
229 {
230 .sht = &piix_sht,
231 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
232 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
233 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = 0x7f, /* udma0-6 */
237 .port_ops = &piix_sata_ops,
238 },
239 };
240
241 static struct pci_bits piix_enable_bits[] = {
242 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
243 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
244 };
245
246 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
247 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
248 MODULE_LICENSE("GPL");
249 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
250
251 /**
252 * piix_pata_cbl_detect - Probe host controller cable detect info
253 * @ap: Port for which cable detect info is desired
254 *
255 * Read 80c cable indicator from SATA PCI device's PCI config
256 * register. This register is normally set by firmware (BIOS).
257 *
258 * LOCKING:
259 * None (inherited from caller).
260 */
261 static void piix_pata_cbl_detect(struct ata_port *ap)
262 {
263 struct pci_dev *pdev = ap->host_set->pdev;
264 u8 tmp, mask;
265
266 /* no 80c support in host controller? */
267 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
268 goto cbl40;
269
270 /* check BIOS cable detect results */
271 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
272 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
273 if ((tmp & mask) == 0)
274 goto cbl40;
275
276 ap->cbl = ATA_CBL_PATA80;
277 return;
278
279 cbl40:
280 ap->cbl = ATA_CBL_PATA40;
281 ap->udma_mask &= ATA_UDMA_MASK_40C;
282 }
283
284 /**
285 * piix_pata_phy_reset - Probe specified port on PATA host controller
286 * @ap: Port to probe
287 *
288 * Probe PATA phy.
289 *
290 * LOCKING:
291 * None (inherited from caller).
292 */
293
294 static void piix_pata_phy_reset(struct ata_port *ap)
295 {
296 if (!pci_test_config_bits(ap->host_set->pdev,
297 &piix_enable_bits[ap->port_no])) {
298 ata_port_disable(ap);
299 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
300 return;
301 }
302
303 piix_pata_cbl_detect(ap);
304
305 ata_port_probe(ap);
306
307 ata_bus_reset(ap);
308 }
309
310 /**
311 * piix_sata_probe - Probe PCI device for present SATA devices
312 * @ap: Port associated with the PCI device we wish to probe
313 *
314 * Reads SATA PCI device's PCI config register Port Configuration
315 * and Status (PCS) to determine port and device availability.
316 *
317 * LOCKING:
318 * None (inherited from caller).
319 *
320 * RETURNS:
321 * Non-zero if device detected, zero otherwise.
322 */
323 static int piix_sata_probe (struct ata_port *ap)
324 {
325 struct pci_dev *pdev = ap->host_set->pdev;
326 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
327 int orig_mask, mask, i;
328 u8 pcs;
329
330 mask = (PIIX_PORT_PRESENT << ap->port_no) |
331 (PIIX_PORT_ENABLED << ap->port_no);
332
333 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
334 orig_mask = (int) pcs & 0xff;
335
336 /* TODO: this is vaguely wrong for ICH6 combined mode,
337 * where only two of the four SATA ports are mapped
338 * onto a single ATA channel. It is also vaguely inaccurate
339 * for ICH5, which has only two ports. However, this is ok,
340 * as further device presence detection code will handle
341 * any false positives produced here.
342 */
343
344 for (i = 0; i < 4; i++) {
345 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
346
347 if ((orig_mask & mask) == mask)
348 if (combined || (i == ap->port_no))
349 return 1;
350 }
351
352 return 0;
353 }
354
355 /**
356 * piix_sata_phy_reset - Probe specified port on SATA host controller
357 * @ap: Port to probe
358 *
359 * Probe SATA phy.
360 *
361 * LOCKING:
362 * None (inherited from caller).
363 */
364
365 static void piix_sata_phy_reset(struct ata_port *ap)
366 {
367 if (!piix_sata_probe(ap)) {
368 ata_port_disable(ap);
369 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
370 return;
371 }
372
373 ap->cbl = ATA_CBL_SATA;
374
375 ata_port_probe(ap);
376
377 ata_bus_reset(ap);
378 }
379
380 /**
381 * piix_set_piomode - Initialize host controller PATA PIO timings
382 * @ap: Port whose timings we are configuring
383 * @adev: um
384 * @pio: PIO mode, 0 - 4
385 *
386 * Set PIO mode for device, in host controller PCI config space.
387 *
388 * LOCKING:
389 * None (inherited from caller).
390 */
391
392 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
393 {
394 unsigned int pio = adev->pio_mode - XFER_PIO_0;
395 struct pci_dev *dev = ap->host_set->pdev;
396 unsigned int is_slave = (adev->devno != 0);
397 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
398 unsigned int slave_port = 0x44;
399 u16 master_data;
400 u8 slave_data;
401
402 static const /* ISP RTC */
403 u8 timings[][2] = { { 0, 0 },
404 { 0, 0 },
405 { 1, 0 },
406 { 2, 1 },
407 { 2, 3 }, };
408
409 pci_read_config_word(dev, master_port, &master_data);
410 if (is_slave) {
411 master_data |= 0x4000;
412 /* enable PPE, IE and TIME */
413 master_data |= 0x0070;
414 pci_read_config_byte(dev, slave_port, &slave_data);
415 slave_data &= (ap->port_no ? 0x0f : 0xf0);
416 slave_data |=
417 (timings[pio][0] << 2) |
418 (timings[pio][1] << (ap->port_no ? 4 : 0));
419 } else {
420 master_data &= 0xccf8;
421 /* enable PPE, IE and TIME */
422 master_data |= 0x0007;
423 master_data |=
424 (timings[pio][0] << 12) |
425 (timings[pio][1] << 8);
426 }
427 pci_write_config_word(dev, master_port, master_data);
428 if (is_slave)
429 pci_write_config_byte(dev, slave_port, slave_data);
430 }
431
432 /**
433 * piix_set_dmamode - Initialize host controller PATA PIO timings
434 * @ap: Port whose timings we are configuring
435 * @adev: um
436 * @udma: udma mode, 0 - 6
437 *
438 * Set UDMA mode for device, in host controller PCI config space.
439 *
440 * LOCKING:
441 * None (inherited from caller).
442 */
443
444 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
445 {
446 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
447 struct pci_dev *dev = ap->host_set->pdev;
448 u8 maslave = ap->port_no ? 0x42 : 0x40;
449 u8 speed = udma;
450 unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
451 int a_speed = 3 << (drive_dn * 4);
452 int u_flag = 1 << drive_dn;
453 int v_flag = 0x01 << drive_dn;
454 int w_flag = 0x10 << drive_dn;
455 int u_speed = 0;
456 int sitre;
457 u16 reg4042, reg4a;
458 u8 reg48, reg54, reg55;
459
460 pci_read_config_word(dev, maslave, &reg4042);
461 DPRINTK("reg4042 = 0x%04x\n", reg4042);
462 sitre = (reg4042 & 0x4000) ? 1 : 0;
463 pci_read_config_byte(dev, 0x48, &reg48);
464 pci_read_config_word(dev, 0x4a, &reg4a);
465 pci_read_config_byte(dev, 0x54, &reg54);
466 pci_read_config_byte(dev, 0x55, &reg55);
467
468 switch(speed) {
469 case XFER_UDMA_4:
470 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
471 case XFER_UDMA_6:
472 case XFER_UDMA_5:
473 case XFER_UDMA_3:
474 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
475 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
476 case XFER_MW_DMA_2:
477 case XFER_MW_DMA_1: break;
478 default:
479 BUG();
480 return;
481 }
482
483 if (speed >= XFER_UDMA_0) {
484 if (!(reg48 & u_flag))
485 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
486 if (speed == XFER_UDMA_5) {
487 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
488 } else {
489 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
490 }
491 if ((reg4a & a_speed) != u_speed)
492 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
493 if (speed > XFER_UDMA_2) {
494 if (!(reg54 & v_flag))
495 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
496 } else
497 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
498 } else {
499 if (reg48 & u_flag)
500 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
501 if (reg4a & a_speed)
502 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
503 if (reg54 & v_flag)
504 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
505 if (reg55 & w_flag)
506 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
507 }
508 }
509
510 /* move to PCI layer, integrate w/ MSI stuff */
511 static void pci_enable_intx(struct pci_dev *pdev)
512 {
513 u16 pci_command;
514
515 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
516 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
517 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
518 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
519 }
520 }
521
522 #define AHCI_PCI_BAR 5
523 #define AHCI_GLOBAL_CTL 0x04
524 #define AHCI_ENABLE (1 << 31)
525 static int piix_disable_ahci(struct pci_dev *pdev)
526 {
527 void *mmio;
528 unsigned long addr;
529 u32 tmp;
530 int rc = 0;
531
532 /* BUG: pci_enable_device has not yet been called. This
533 * works because this device is usually set up by BIOS.
534 */
535
536 addr = pci_resource_start(pdev, AHCI_PCI_BAR);
537 if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
538 return 0;
539
540 mmio = ioremap(addr, 64);
541 if (!mmio)
542 return -ENOMEM;
543
544 tmp = readl(mmio + AHCI_GLOBAL_CTL);
545 if (tmp & AHCI_ENABLE) {
546 tmp &= ~AHCI_ENABLE;
547 writel(tmp, mmio + AHCI_GLOBAL_CTL);
548
549 tmp = readl(mmio + AHCI_GLOBAL_CTL);
550 if (tmp & AHCI_ENABLE)
551 rc = -EIO;
552 }
553
554 iounmap(mmio);
555 return rc;
556 }
557
558 /**
559 * piix_init_one - Register PIIX ATA PCI device with kernel services
560 * @pdev: PCI device to register
561 * @ent: Entry in piix_pci_tbl matching with @pdev
562 *
563 * Called from kernel PCI layer. We probe for combined mode (sigh),
564 * and then hand over control to libata, for it to do the rest.
565 *
566 * LOCKING:
567 * Inherited from PCI layer (may sleep).
568 *
569 * RETURNS:
570 * Zero on success, or -ERRNO value.
571 */
572
573 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
574 {
575 static int printed_version;
576 struct ata_port_info *port_info[2];
577 unsigned int combined = 0, n_ports = 1;
578 unsigned int pata_chan = 0, sata_chan = 0;
579
580 if (!printed_version++)
581 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
582
583 /* no hotplugging support (FIXME) */
584 if (!in_module_init)
585 return -ENODEV;
586
587 port_info[0] = &piix_port_info[ent->driver_data];
588 port_info[1] = NULL;
589
590 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
591 int rc = piix_disable_ahci(pdev);
592 if (rc)
593 return rc;
594 }
595
596 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
597 u8 tmp;
598 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
599
600 if (tmp & PIIX_COMB) {
601 combined = 1;
602 if (tmp & PIIX_COMB_PATA_P0)
603 sata_chan = 1;
604 else
605 pata_chan = 1;
606 }
607 }
608
609 /* On ICH5, some BIOSen disable the interrupt using the
610 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
611 * On ICH6, this bit has the same effect, but only when
612 * MSI is disabled (and it is disabled, as we don't use
613 * message-signalled interrupts currently).
614 */
615 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
616 pci_enable_intx(pdev);
617
618 if (combined) {
619 port_info[sata_chan] = &piix_port_info[ent->driver_data];
620 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
621 port_info[pata_chan] = &piix_port_info[ich5_pata];
622 n_ports++;
623
624 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
625 }
626
627 return ata_pci_init_one(pdev, port_info, n_ports);
628 }
629
630 /**
631 * piix_init -
632 *
633 * LOCKING:
634 *
635 * RETURNS:
636 *
637 */
638
639 static int __init piix_init(void)
640 {
641 int rc;
642
643 DPRINTK("pci_module_init\n");
644 rc = pci_module_init(&piix_pci_driver);
645 if (rc)
646 return rc;
647
648 in_module_init = 0;
649
650 DPRINTK("done\n");
651 return 0;
652 }
653
654 /**
655 * piix_exit -
656 *
657 * LOCKING:
658 *
659 */
660
661 static void __exit piix_exit(void)
662 {
663 pci_unregister_driver(&piix_pci_driver);
664 }
665
666 module_init(piix_init);
667 module_exit(piix_exit);
668
MOXA 2.6.9 from sdlinux-moxaart.tgz