2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit
quirk_passive_release(struct pci_dev
*dev
)
28 struct pci_dev
*d
= NULL
;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d
= pci_find_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
34 pci_read_config_byte(d
, 0x82, &dlc
);
36 printk(KERN_ERR
"PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d
));
38 pci_write_config_byte(d
, 0x82, dlc
);
42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
48 This appears to be BIOS not version dependent. So presumably there is a
50 int isa_dma_bridge_buggy
; /* Exported */
52 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
54 if (!isa_dma_bridge_buggy
) {
55 isa_dma_bridge_buggy
=1;
56 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
74 * Chipsets where PCI->PCI transfers vanish or hang
76 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
78 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
79 printk(KERN_INFO
"Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems
|= PCIPCI_FAIL
;
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
87 * Triton requires workarounds to be used by the drivers
89 static void __devinit
quirk_triton(struct pci_dev
*dev
)
91 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
92 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems
|= PCIPCI_TRITON
;
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
108 * Updated based on further information from the site and also on
109 * information provided by VIA
111 static void __devinit
quirk_vialatency(struct pci_dev
*dev
)
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
119 p
= pci_find_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
121 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev
< 0x40 || rev
> 0x42)
127 p
= pci_find_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
128 if (p
==NULL
) /* No problem parts */
130 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
131 /* Check for buggy part revisions */
132 if (rev
< 0x10 || rev
> 0x12)
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
149 pci_read_config_byte(dev
, 0x76, &busarb
);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
154 pci_write_config_byte(dev
, 0x76, busarb
);
155 printk(KERN_INFO
"Applying VIA southbridge workaround.\n");
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
162 * VIA Apollo VP3 needs ETBF on BT848/878
164 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
166 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
167 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
168 pci_pci_problems
|= PCIPCI_VIAETBF
;
171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
173 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
175 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
176 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
177 pci_pci_problems
|= PCIPCI_VSFX
;
180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
183 * Ali Magik requires workarounds to be used by the drivers
184 * that DMA to AGP space. Latency must be set to 0xA and triton
185 * workaround applied too
186 * [Info kindly provided by ALi]
188 static void __init
quirk_alimagik(struct pci_dev
*dev
)
190 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
191 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
199 * Natoma has some interesting boundary conditions with Zoran stuff
202 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
204 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
205 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
206 pci_pci_problems
|= PCIPCI_NATOMA
;
209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
217 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
218 * If it's needed, re-allocate the region.
220 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
222 struct resource
*r
= &dev
->resource
[0];
224 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
229 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
232 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
, unsigned size
, int nr
)
236 struct resource
*res
= dev
->resource
+ nr
;
238 res
->name
= pci_name(dev
);
240 res
->end
= region
+ size
- 1;
241 res
->flags
= IORESOURCE_IO
;
242 pci_claim_resource(dev
, nr
);
247 * ATI Northbridge setups MCE the processor if you even
248 * read somewhere between 0x3b0->0x3bb or read 0x3d3
250 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
252 printk(KERN_INFO
"ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
253 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
254 request_region(0x3b0, 0x0C, "RadeonIGP");
255 request_region(0x3d3, 0x01, "RadeonIGP");
257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
260 * Let's make the southbridge information explicit instead
261 * of having to worry about people probing the ACPI areas,
262 * for example.. (Yes, it happens, and if you read the wrong
263 * ACPI register it will put the machine to sleep with no
264 * way of waking it up again. Bummer).
266 * ALI M7101: Two IO regions pointed to by words at
267 * 0xE0 (64 bytes of ACPI registers)
268 * 0xE2 (32 bytes of SMB registers)
270 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
274 pci_read_config_word(dev
, 0xE0, ®ion
);
275 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
);
276 pci_read_config_word(dev
, 0xE2, ®ion
);
277 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1);
279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
282 * PIIX4 ACPI: Two IO regions pointed to by longwords at
283 * 0x40 (64 bytes of ACPI registers)
284 * 0x90 (32 bytes of SMB registers)
286 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
290 pci_read_config_dword(dev
, 0x40, ®ion
);
291 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
);
292 pci_read_config_dword(dev
, 0x90, ®ion
);
293 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1);
295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
298 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
299 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
300 * 0x58 (64 bytes of GPIO I/O space)
302 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
306 pci_read_config_dword(dev
, 0x40, ®ion
);
307 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
);
309 pci_read_config_dword(dev
, 0x58, ®ion
);
310 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1);
312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
323 * VIA ACPI: One IO region pointed to by longword at
324 * 0x48 or 0x20 (256 bytes of ACPI registers)
326 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
331 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
333 pci_read_config_dword(dev
, 0x48, ®ion
);
334 region
&= PCI_BASE_ADDRESS_IO_MASK
;
335 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
);
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
341 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
342 * 0x48 (256 bytes of ACPI registers)
343 * 0x70 (128 bytes of hardware monitoring register)
344 * 0x90 (16 bytes of SMB registers)
346 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
351 quirk_vt82c586_acpi(dev
);
353 pci_read_config_word(dev
, 0x70, &hm
);
354 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
355 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1);
357 pci_read_config_dword(dev
, 0x90, &smb
);
358 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
359 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2);
361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
364 #ifdef CONFIG_X86_IO_APIC
366 #include <asm/io_apic.h>
369 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
370 * devices to the external APIC.
372 * TODO: When we have device-specific interrupt routers,
373 * this code will go away from quirks.
375 static void __devinit
quirk_via_ioapic(struct pci_dev
*dev
)
380 tmp
= 0; /* nothing routed to external APIC */
382 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
384 printk(KERN_INFO
"PCI: %sbling Via external APIC routing\n",
385 tmp
== 0 ? "Disa" : "Ena");
387 /* Offset 0x58: External APIC IRQ output control */
388 pci_write_config_byte (dev
, 0x58, tmp
);
390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
393 * The AMD io apic can hang the box when an apic irq is masked.
394 * We check all revs >= B0 (yet not in the pre production!) as the bug
395 * is currently marked NoFix
397 * We have multiple reports of hangs with this chipset that went away with
398 * noapic specified. For the moment we assume its the errata. We may be wrong
399 * of course. However the advice is demonstrably good even if so..
401 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
405 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
407 printk(KERN_WARNING
"I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
408 printk(KERN_WARNING
" : booting with the \"noapic\" option.\n");
411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
413 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
415 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
420 #define AMD8131_revA0 0x01
421 #define AMD8131_revB0 0x11
422 #define AMD8131_MISC 0x40
423 #define AMD8131_NIOAMODE_BIT 0
424 static void __init
quirk_amd_8131_ioapic(struct pci_dev
*dev
)
426 unsigned char revid
, tmp
;
431 pci_read_config_byte(dev
, PCI_REVISION_ID
, &revid
);
432 if (revid
== AMD8131_revA0
|| revid
== AMD8131_revB0
) {
433 printk(KERN_INFO
"Fixing up AMD8131 IOAPIC mode\n");
434 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
435 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
436 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_APIC
, quirk_amd_8131_ioapic
);
441 #endif /* CONFIG_X86_IO_APIC */
445 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
446 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
447 * when written, it makes an internal connection to the PIC.
448 * For these devices, this register is defined to be 4 bits wide.
449 * Normally this is fine. However for IO-APIC motherboards, or
450 * non-x86 architectures (yes Via exists on PPC among other places),
451 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
452 * interrupts delivered properly.
454 * TODO: When we have device-specific interrupt routers,
455 * quirk_via_irqpic will go away from quirks.
459 * FIXME: it is questionable that quirk_via_acpi
460 * is needed. It shows up as an ISA bridge, and does not
461 * support the PCI_INTERRUPT_LINE register at all. Therefore
462 * it seems like setting the pci_dev's 'irq' to the
463 * value of the ACPI SCI interrupt is only done for convenience.
466 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
469 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
472 pci_read_config_byte(d
, 0x42, &irq
);
474 if (irq
&& (irq
!= 2))
477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
480 static void __devinit
quirk_via_irqpic(struct pci_dev
*dev
)
482 u8 irq
, new_irq
= dev
->irq
& 0xf;
484 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
486 if (new_irq
!= irq
) {
487 printk(KERN_INFO
"PCI: Via IRQ fixup for %s, from %d to %d\n",
488 pci_name(dev
), irq
, new_irq
);
491 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_2
, quirk_via_irqpic
);
495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_5
, quirk_via_irqpic
);
496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_6
, quirk_via_irqpic
);
500 * PIIX3 USB: We have to disable USB interrupts that are
501 * hardwired to PIRQD# and may be shared with an
504 * Legacy Support Register (LEGSUP):
505 * bit13: USB PIRQ Enable (USBPIRQDEN),
506 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
508 * We mask out all r/wc bits, too.
510 static void __devinit
quirk_piix3_usb(struct pci_dev
*dev
)
514 pci_read_config_word(dev
, 0xc0, &legsup
);
516 pci_write_config_word(dev
, 0xc0, legsup
);
518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_2
, quirk_piix3_usb
);
519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_2
, quirk_piix3_usb
);
522 * VIA VT82C598 has its device ID settable and many BIOSes
523 * set it to the ID of VT82C597 for backward compatibility.
524 * We need to switch it off to be able to recognize the real
527 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
529 pci_write_config_byte(dev
, 0xfc, 0);
530 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
535 * CardBus controllers have a legacy base address that enables them
536 * to respond as i82365 pcmcia controllers. We don't want them to
537 * do this even if the Linux CardBus driver is not loaded, because
538 * the Linux i82365 driver does not (and should not) handle CardBus.
540 static void __devinit
quirk_cardbus_legacy(struct pci_dev
*dev
)
542 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
544 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
546 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
549 * Following the PCI ordering rules is optional on the AMD762. I'm not
550 * sure what the designers were smoking but let's not inhale...
552 * To be fair to AMD, it follows the spec by default, its BIOS people
555 static void __devinit
quirk_amd_ordering(struct pci_dev
*dev
)
558 pci_read_config_dword(dev
, 0x4C, &pcic
);
561 printk(KERN_WARNING
"BIOS failed to enable PCI standards compliance, fixing this error.\n");
562 pci_write_config_dword(dev
, 0x4C, pcic
);
563 pci_read_config_dword(dev
, 0x84, &pcic
);
564 pcic
|= (1<<23); /* Required in this mode */
565 pci_write_config_dword(dev
, 0x84, pcic
);
568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
571 * DreamWorks provided workaround for Dunord I-3000 problem
573 * This card decodes and responds to addresses not apparently
574 * assigned to it. We force a larger allocation to ensure that
575 * nothing gets put too close to it.
577 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
579 struct resource
*r
= &dev
->resource
[1];
583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
586 * i82380FB mobile docking controller: its PCI-to-PCI bridge
587 * is subtractive decoding (transparent), and does indicate this
588 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
591 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
593 dev
->transparent
= 1;
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
599 * Common misconfiguration of the MediaGX/Geode PCI master that will
600 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
601 * datasheets found at http://www.national.com/ds/GX for info on what
602 * these bits do. <christer@weinigel.se>
604 static void __init
quirk_mediagx_master(struct pci_dev
*dev
)
607 pci_read_config_byte(dev
, 0x41, ®
);
610 printk(KERN_INFO
"PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
611 pci_write_config_byte(dev
, 0x41, reg
);
614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
617 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
618 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
619 * secondary channels respectively). If the device reports Compatible mode
620 * but does use BAR0-3 for address decoding, we assume that firmware has
621 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
622 * Exceptions (if they exist) must be handled in chip/architecture specific
625 * Note: for non x86 people. You may need an arch specific quirk to handle
626 * moving IDE devices to native mode as well. Some plug in card devices power
627 * up in compatible mode and assume the BIOS will adjust them.
629 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
630 * we do now ? We don't want is pci_enable_device to come along
631 * and assign new resources. Both approaches work for that.
633 static void __devinit
quirk_ide_bases(struct pci_dev
*dev
)
635 struct resource
*res
;
636 int first_bar
= 2, last_bar
= 0;
638 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
641 res
= &dev
->resource
[0];
643 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
644 if (!(dev
->class & 1) && (res
[0].flags
|| res
[1].flags
)) {
645 res
[0].start
= res
[0].end
= res
[0].flags
= 0;
646 res
[1].start
= res
[1].end
= res
[1].flags
= 0;
651 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
652 if (!(dev
->class & 4) && (res
[2].flags
|| res
[3].flags
)) {
653 res
[2].start
= res
[2].end
= res
[2].flags
= 0;
654 res
[3].start
= res
[3].end
= res
[3].flags
= 0;
661 printk(KERN_INFO
"PCI: Ignoring BAR%d-%d of IDE controller %s\n",
662 first_bar
, last_bar
, pci_name(dev
));
664 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_ide_bases
);
667 * Ensure C0 rev restreaming is off. This is normally done by
668 * the BIOS but in the odd case it is not the results are corruption
669 * hence the presence of a Linux check
671 static void __init
quirk_disable_pxb(struct pci_dev
*pdev
)
676 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
677 if (rev
!= 0x04) /* Only C0 requires this */
679 pci_read_config_word(pdev
, 0x40, &config
);
680 if (config
& (1<<6)) {
682 pci_write_config_word(pdev
, 0x40, config
);
683 printk(KERN_INFO
"PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
689 * VIA northbridges care about PCI_INTERRUPT_LINE
691 int interrupt_line_quirk
;
693 static void __devinit
quirk_via_bridge(struct pci_dev
*pdev
)
696 interrupt_line_quirk
= 1;
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_bridge
);
701 * Serverworks CSB5 IDE does not fully support native mode
703 static void __init
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
706 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
710 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
711 /* need to re-assign BARs for compat mode */
712 quirk_ide_bases(pdev
);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
717 /* This was originally an Alpha specific thing, but it really fits here.
718 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
720 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
722 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
727 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
728 * is not activated. The myth is that Asus said that they do not want the
729 * users to be irritated by just another PCI Device in the Win98 device
730 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
731 * package 2.7.0 for details)
733 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
734 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
735 * becomes necessary to do this tweak in two steps -- I've chosen the Host
738 static int __initdata asus_hides_smbus
= 0;
740 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
742 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
743 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
744 switch(dev
->subsystem_device
) {
745 case 0x8070: /* P4B */
746 case 0x8088: /* P4B533 */
747 case 0x1626: /* L3C notebook */
748 asus_hides_smbus
= 1;
750 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
751 switch(dev
->subsystem_device
) {
752 case 0x80b1: /* P4GE-V */
753 case 0x80b2: /* P4PE */
754 case 0x8093: /* P4B533-V */
755 asus_hides_smbus
= 1;
757 if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
758 switch(dev
->subsystem_device
) {
759 case 0x8030: /* P4T533 */
760 asus_hides_smbus
= 1;
762 if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
763 switch (dev
->subsystem_device
) {
764 case 0x8070: /* P4G8X Deluxe */
765 asus_hides_smbus
= 1;
767 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
768 switch (dev
->subsystem_device
) {
769 case 0x1751: /* M2N notebook */
770 asus_hides_smbus
= 1;
772 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
773 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
774 switch(dev
->subsystem_device
) {
775 case 0x088C: /* HP Compaq nc8000 */
776 case 0x0890: /* HP Compaq nc6000 */
777 asus_hides_smbus
= 1;
779 if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
780 switch (dev
->subsystem_device
) {
781 case 0x12bc: /* HP D330L */
782 asus_hides_smbus
= 1;
786 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
794 static void __init
asus_hides_smbus_lpc(struct pci_dev
*dev
)
798 if (likely(!asus_hides_smbus
))
801 pci_read_config_word(dev
, 0xF2, &val
);
803 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
804 pci_read_config_word(dev
, 0xF2, &val
);
806 printk(KERN_INFO
"PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
808 printk(KERN_INFO
"PCI: Enabled i801 SMBus device\n");
811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
812 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
813 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
818 * SiS 96x south bridge: BIOS typically hides SMBus device...
820 static void __init
quirk_sis_96x_smbus(struct pci_dev
*dev
)
823 printk(KERN_INFO
"Enabling SiS 96x SMBus.\n");
824 pci_read_config_byte(dev
, 0x77, &val
);
825 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
826 pci_read_config_byte(dev
, 0x77, &val
);
830 * ... This is further complicated by the fact that some SiS96x south
831 * bridges pretend to be 85C503/5513 instead. In that case see if we
832 * spotted a compatible north bridge to make sure.
833 * (pci_find_device doesn't work yet)
835 * We can also enable the sis96x bit in the discovery register..
837 static int __devinitdata sis_96x_compatible
= 0;
839 #define SIS_DETECT_REGISTER 0x40
841 static void __init
quirk_sis_503(struct pci_dev
*dev
)
846 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
847 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
848 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
849 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
850 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
854 /* Make people aware that we changed the config.. */
855 printk(KERN_WARNING
"Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid
, sis_96x_compatible
);
858 * Ok, it now shows up as a 96x.. The 96x quirks are after
859 * the 503 quirk in the quirk table, so they'll automatically
860 * run and enable things like the SMBus device
865 static void __init
quirk_sis_96x_compatible(struct pci_dev
*dev
)
867 sis_96x_compatible
= 1;
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_645
, quirk_sis_96x_compatible
);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_646
, quirk_sis_96x_compatible
);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_648
, quirk_sis_96x_compatible
);
872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_650
, quirk_sis_96x_compatible
);
873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_651
, quirk_sis_96x_compatible
);
874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_735
, quirk_sis_96x_compatible
);
876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
879 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
883 #ifdef CONFIG_X86_IO_APIC
884 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
888 if ((pdev
->class >> 8) != 0xff00)
891 /* the first BAR is the location of the IO APIC...we must
892 * not touch this (and it's already covered by the fixmap), so
893 * forcibly insert it into the resource tree */
894 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
895 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
897 /* The next five BARs all seem to be rubbish, so just clean
899 for (i
=1; i
< 6; i
++) {
900 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
907 #ifdef CONFIG_SCSI_SATA
908 static void __init
quirk_intel_ide_combined(struct pci_dev
*pdev
)
914 * Narrow down to Intel SATA PCI devices.
916 switch (pdev
->device
) {
917 /* PCI ids taken from drivers/scsi/ata_piix.c */
930 /* we do not handle this PCI device */
935 * Read combined mode register.
937 pci_read_config_byte(pdev
, 0x90, &tmp
); /* combined mode reg */
940 tmp
&= 0x6; /* interesting bits 2:1, PATA primary/secondary */
941 if (tmp
== 0x4) /* bits 10x */
942 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
943 else if (tmp
== 0x6) /* bits 11x */
944 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
946 return; /* not in combined mode */
949 tmp
&= 0x3; /* interesting bits 1:0 */
951 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
952 else if (tmp
& (1 << 1))
953 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
955 return; /* not in combined mode */
959 * Read programming interface register.
960 * (Tells us if it's legacy or native mode)
962 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
964 /* if SATA port is in native mode, we're ok. */
968 /* SATA port is in legacy mode. Reserve port so that
969 * IDE driver does not attempt to use it. If request_region
970 * fails, it will be obvious at boot time, so we don't bother
971 * checking return values.
973 if (comb
== (1 << 0))
974 request_region(0x1f0, 8, "libata"); /* port 0 */
976 request_region(0x170, 8, "libata"); /* port 1 */
978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_intel_ide_combined
);
979 #endif /* CONFIG_SCSI_SATA */
981 int pciehp_msi_quirk
;
983 static void __devinit
quirk_pciehp_msi(struct pci_dev
*pdev
)
985 pciehp_msi_quirk
= 1;
987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_SMCH
, quirk_pciehp_msi
);
990 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
993 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
994 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
995 pr_debug(KERN_INFO
"PCI: Calling quirk %p for %s\n", f
->hook
, pci_name(dev
));
1002 extern struct pci_fixup __start_pci_fixups_header
[];
1003 extern struct pci_fixup __end_pci_fixups_header
[];
1004 extern struct pci_fixup __start_pci_fixups_final
[];
1005 extern struct pci_fixup __end_pci_fixups_final
[];
1007 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1009 struct pci_fixup
*start
, *end
;
1012 case pci_fixup_header
:
1013 start
= __start_pci_fixups_header
;
1014 end
= __end_pci_fixups_header
;
1017 case pci_fixup_final
:
1018 start
= __start_pci_fixups_final
;
1019 end
= __end_pci_fixups_final
;
1022 /* stupid compiler warning, you would think with an enum... */
1025 pci_do_fixups(dev
, start
, end
);
1028 EXPORT_SYMBOL(pciehp_msi_quirk
);