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code style scripts/checkpatch.pl (linux-3.9-rc1) formatting
[linux-2.6.34.14-moxart.git] / sound / pci / maestro3.c
blobb56e336767809b250cd508a04d96fd526c130d45
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <sound/core.h>
45 #include <sound/info.h>
46 #include <sound/control.h>
47 #include <sound/pcm.h>
48 #include <sound/mpu401.h>
49 #include <sound/ac97_codec.h>
50 #include <sound/initval.h>
51 #include <asm/byteorder.h>
52
53 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54 MODULE_DESCRIPTION("ESS Maestro3 PCI");
55 MODULE_LICENSE("GPL");
56 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,ES1988},"
58 "{ESS,Allegro PCI},"
59 "{ESS,Allegro-1 PCI},"
60 "{ESS,Canyon3D-2/LE PCI}}");
61 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
62 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
63
64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
67 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
68 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
69
70 module_param_array(index, int, NULL, 0444);
71 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
72 module_param_array(id, charp, NULL, 0444);
73 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
74 module_param_array(enable, bool, NULL, 0444);
75 MODULE_PARM_DESC(enable, "Enable this soundcard.");
76 module_param_array(external_amp, bool, NULL, 0444);
77 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
78 module_param_array(amp_gpio, int, NULL, 0444);
79 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
80
81 #define MAX_PLAYBACKS 2
82 #define MAX_CAPTURES 1
83 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
84
85
86 /*
87 * maestro3 registers
88 */
89
90 /* Allegro PCI configuration registers */
91 #define PCI_LEGACY_AUDIO_CTRL 0x40
92 #define SOUND_BLASTER_ENABLE 0x00000001
93 #define FM_SYNTHESIS_ENABLE 0x00000002
94 #define GAME_PORT_ENABLE 0x00000004
95 #define MPU401_IO_ENABLE 0x00000008
96 #define MPU401_IRQ_ENABLE 0x00000010
97 #define ALIAS_10BIT_IO 0x00000020
98 #define SB_DMA_MASK 0x000000C0
99 #define SB_DMA_0 0x00000040
100 #define SB_DMA_1 0x00000040
101 #define SB_DMA_R 0x00000080
102 #define SB_DMA_3 0x000000C0
103 #define SB_IRQ_MASK 0x00000700
104 #define SB_IRQ_5 0x00000000
105 #define SB_IRQ_7 0x00000100
106 #define SB_IRQ_9 0x00000200
107 #define SB_IRQ_10 0x00000300
108 #define MIDI_IRQ_MASK 0x00003800
109 #define SERIAL_IRQ_ENABLE 0x00004000
110 #define DISABLE_LEGACY 0x00008000
111
112 #define PCI_ALLEGRO_CONFIG 0x50
113 #define SB_ADDR_240 0x00000004
114 #define MPU_ADDR_MASK 0x00000018
115 #define MPU_ADDR_330 0x00000000
116 #define MPU_ADDR_300 0x00000008
117 #define MPU_ADDR_320 0x00000010
118 #define MPU_ADDR_340 0x00000018
119 #define USE_PCI_TIMING 0x00000040
120 #define POSTED_WRITE_ENABLE 0x00000080
121 #define DMA_POLICY_MASK 0x00000700
122 #define DMA_DDMA 0x00000000
123 #define DMA_TDMA 0x00000100
124 #define DMA_PCPCI 0x00000200
125 #define DMA_WBDMA16 0x00000400
126 #define DMA_WBDMA4 0x00000500
127 #define DMA_WBDMA2 0x00000600
128 #define DMA_WBDMA1 0x00000700
129 #define DMA_SAFE_GUARD 0x00000800
130 #define HI_PERF_GP_ENABLE 0x00001000
131 #define PIC_SNOOP_MODE_0 0x00002000
132 #define PIC_SNOOP_MODE_1 0x00004000
133 #define SOUNDBLASTER_IRQ_MASK 0x00008000
134 #define RING_IN_ENABLE 0x00010000
135 #define SPDIF_TEST_MODE 0x00020000
136 #define CLK_MULT_MODE_SELECT_2 0x00040000
137 #define EEPROM_WRITE_ENABLE 0x00080000
138 #define CODEC_DIR_IN 0x00100000
139 #define HV_BUTTON_FROM_GD 0x00200000
140 #define REDUCED_DEBOUNCE 0x00400000
141 #define HV_CTRL_ENABLE 0x00800000
142 #define SPDIF_ENABLE 0x01000000
143 #define CLK_DIV_SELECT 0x06000000
144 #define CLK_DIV_BY_48 0x00000000
145 #define CLK_DIV_BY_49 0x02000000
146 #define CLK_DIV_BY_50 0x04000000
147 #define CLK_DIV_RESERVED 0x06000000
148 #define PM_CTRL_ENABLE 0x08000000
149 #define CLK_MULT_MODE_SELECT 0x30000000
150 #define CLK_MULT_MODE_SHIFT 28
151 #define CLK_MULT_MODE_0 0x00000000
152 #define CLK_MULT_MODE_1 0x10000000
153 #define CLK_MULT_MODE_2 0x20000000
154 #define CLK_MULT_MODE_3 0x30000000
155 #define INT_CLK_SELECT 0x40000000
156 #define INT_CLK_MULT_RESET 0x80000000
157
158 /* M3 */
159 #define INT_CLK_SRC_NOT_PCI 0x00100000
160 #define INT_CLK_MULT_ENABLE 0x80000000
161
162 #define PCI_ACPI_CONTROL 0x54
163 #define PCI_ACPI_D0 0x00000000
164 #define PCI_ACPI_D1 0xB4F70000
165 #define PCI_ACPI_D2 0xB4F7B4F7
166
167 #define PCI_USER_CONFIG 0x58
168 #define EXT_PCI_MASTER_ENABLE 0x00000001
169 #define SPDIF_OUT_SELECT 0x00000002
170 #define TEST_PIN_DIR_CTRL 0x00000004
171 #define AC97_CODEC_TEST 0x00000020
172 #define TRI_STATE_BUFFER 0x00000080
173 #define IN_CLK_12MHZ_SELECT 0x00000100
174 #define MULTI_FUNC_DISABLE 0x00000200
175 #define EXT_MASTER_PAIR_SEL 0x00000400
176 #define PCI_MASTER_SUPPORT 0x00000800
177 #define STOP_CLOCK_ENABLE 0x00001000
178 #define EAPD_DRIVE_ENABLE 0x00002000
179 #define REQ_TRI_STATE_ENABLE 0x00004000
180 #define REQ_LOW_ENABLE 0x00008000
181 #define MIDI_1_ENABLE 0x00010000
182 #define MIDI_2_ENABLE 0x00020000
183 #define SB_AUDIO_SYNC 0x00040000
184 #define HV_CTRL_TEST 0x00100000
185 #define SOUNDBLASTER_TEST 0x00400000
186
187 #define PCI_USER_CONFIG_C 0x5C
188
189 #define PCI_DDMA_CTRL 0x60
190 #define DDMA_ENABLE 0x00000001
191
192
193 /* Allegro registers */
194 #define HOST_INT_CTRL 0x18
195 #define SB_INT_ENABLE 0x0001
196 #define MPU401_INT_ENABLE 0x0002
197 #define ASSP_INT_ENABLE 0x0010
198 #define RING_INT_ENABLE 0x0020
199 #define HV_INT_ENABLE 0x0040
200 #define CLKRUN_GEN_ENABLE 0x0100
201 #define HV_CTRL_TO_PME 0x0400
202 #define SOFTWARE_RESET_ENABLE 0x8000
203
204 /*
205 * should be using the above defines, probably.
206 */
207 #define REGB_ENABLE_RESET 0x01
208 #define REGB_STOP_CLOCK 0x10
209
210 #define HOST_INT_STATUS 0x1A
211 #define SB_INT_PENDING 0x01
212 #define MPU401_INT_PENDING 0x02
213 #define ASSP_INT_PENDING 0x10
214 #define RING_INT_PENDING 0x20
215 #define HV_INT_PENDING 0x40
216
217 #define HARDWARE_VOL_CTRL 0x1B
218 #define SHADOW_MIX_REG_VOICE 0x1C
219 #define HW_VOL_COUNTER_VOICE 0x1D
220 #define SHADOW_MIX_REG_MASTER 0x1E
221 #define HW_VOL_COUNTER_MASTER 0x1F
222
223 #define CODEC_COMMAND 0x30
224 #define CODEC_READ_B 0x80
225
226 #define CODEC_STATUS 0x30
227 #define CODEC_BUSY_B 0x01
228
229 #define CODEC_DATA 0x32
230
231 #define RING_BUS_CTRL_A 0x36
232 #define RAC_PME_ENABLE 0x0100
233 #define RAC_SDFS_ENABLE 0x0200
234 #define LAC_PME_ENABLE 0x0400
235 #define LAC_SDFS_ENABLE 0x0800
236 #define SERIAL_AC_LINK_ENABLE 0x1000
237 #define IO_SRAM_ENABLE 0x2000
238 #define IIS_INPUT_ENABLE 0x8000
239
240 #define RING_BUS_CTRL_B 0x38
241 #define SECOND_CODEC_ID_MASK 0x0003
242 #define SPDIF_FUNC_ENABLE 0x0010
243 #define SECOND_AC_ENABLE 0x0020
244 #define SB_MODULE_INTF_ENABLE 0x0040
245 #define SSPE_ENABLE 0x0040
246 #define M3I_DOCK_ENABLE 0x0080
247
248 #define SDO_OUT_DEST_CTRL 0x3A
249 #define COMMAND_ADDR_OUT 0x0003
250 #define PCM_LR_OUT_LOCAL 0x0000
251 #define PCM_LR_OUT_REMOTE 0x0004
252 #define PCM_LR_OUT_MUTE 0x0008
253 #define PCM_LR_OUT_BOTH 0x000C
254 #define LINE1_DAC_OUT_LOCAL 0x0000
255 #define LINE1_DAC_OUT_REMOTE 0x0010
256 #define LINE1_DAC_OUT_MUTE 0x0020
257 #define LINE1_DAC_OUT_BOTH 0x0030
258 #define PCM_CLS_OUT_LOCAL 0x0000
259 #define PCM_CLS_OUT_REMOTE 0x0040
260 #define PCM_CLS_OUT_MUTE 0x0080
261 #define PCM_CLS_OUT_BOTH 0x00C0
262 #define PCM_RLF_OUT_LOCAL 0x0000
263 #define PCM_RLF_OUT_REMOTE 0x0100
264 #define PCM_RLF_OUT_MUTE 0x0200
265 #define PCM_RLF_OUT_BOTH 0x0300
266 #define LINE2_DAC_OUT_LOCAL 0x0000
267 #define LINE2_DAC_OUT_REMOTE 0x0400
268 #define LINE2_DAC_OUT_MUTE 0x0800
269 #define LINE2_DAC_OUT_BOTH 0x0C00
270 #define HANDSET_OUT_LOCAL 0x0000
271 #define HANDSET_OUT_REMOTE 0x1000
272 #define HANDSET_OUT_MUTE 0x2000
273 #define HANDSET_OUT_BOTH 0x3000
274 #define IO_CTRL_OUT_LOCAL 0x0000
275 #define IO_CTRL_OUT_REMOTE 0x4000
276 #define IO_CTRL_OUT_MUTE 0x8000
277 #define IO_CTRL_OUT_BOTH 0xC000
278
279 #define SDO_IN_DEST_CTRL 0x3C
280 #define STATUS_ADDR_IN 0x0003
281 #define PCM_LR_IN_LOCAL 0x0000
282 #define PCM_LR_IN_REMOTE 0x0004
283 #define PCM_LR_RESERVED 0x0008
284 #define PCM_LR_IN_BOTH 0x000C
285 #define LINE1_ADC_IN_LOCAL 0x0000
286 #define LINE1_ADC_IN_REMOTE 0x0010
287 #define LINE1_ADC_IN_MUTE 0x0020
288 #define MIC_ADC_IN_LOCAL 0x0000
289 #define MIC_ADC_IN_REMOTE 0x0040
290 #define MIC_ADC_IN_MUTE 0x0080
291 #define LINE2_DAC_IN_LOCAL 0x0000
292 #define LINE2_DAC_IN_REMOTE 0x0400
293 #define LINE2_DAC_IN_MUTE 0x0800
294 #define HANDSET_IN_LOCAL 0x0000
295 #define HANDSET_IN_REMOTE 0x1000
296 #define HANDSET_IN_MUTE 0x2000
297 #define IO_STATUS_IN_LOCAL 0x0000
298 #define IO_STATUS_IN_REMOTE 0x4000
299
300 #define SPDIF_IN_CTRL 0x3E
301 #define SPDIF_IN_ENABLE 0x0001
302
303 #define GPIO_DATA 0x60
304 #define GPIO_DATA_MASK 0x0FFF
305 #define GPIO_HV_STATUS 0x3000
306 #define GPIO_PME_STATUS 0x4000
307
308 #define GPIO_MASK 0x64
309 #define GPIO_DIRECTION 0x68
310 #define GPO_PRIMARY_AC97 0x0001
311 #define GPI_LINEOUT_SENSE 0x0004
312 #define GPO_SECONDARY_AC97 0x0008
313 #define GPI_VOL_DOWN 0x0010
314 #define GPI_VOL_UP 0x0020
315 #define GPI_IIS_CLK 0x0040
316 #define GPI_IIS_LRCLK 0x0080
317 #define GPI_IIS_DATA 0x0100
318 #define GPI_DOCKING_STATUS 0x0100
319 #define GPI_HEADPHONE_SENSE 0x0200
320 #define GPO_EXT_AMP_SHUTDOWN 0x1000
321
322 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
323 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
324
325 /* M3 */
326 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
327
328 #define ASSP_INDEX_PORT 0x80
329 #define ASSP_MEMORY_PORT 0x82
330 #define ASSP_DATA_PORT 0x84
331
332 #define MPU401_DATA_PORT 0x98
333 #define MPU401_STATUS_PORT 0x99
334
335 #define CLK_MULT_DATA_PORT 0x9C
336
337 #define ASSP_CONTROL_A 0xA2
338 #define ASSP_0_WS_ENABLE 0x01
339 #define ASSP_CTRL_A_RESERVED1 0x02
340 #define ASSP_CTRL_A_RESERVED2 0x04
341 #define ASSP_CLK_49MHZ_SELECT 0x08
342 #define FAST_PLU_ENABLE 0x10
343 #define ASSP_CTRL_A_RESERVED3 0x20
344 #define DSP_CLK_36MHZ_SELECT 0x40
345
346 #define ASSP_CONTROL_B 0xA4
347 #define RESET_ASSP 0x00
348 #define RUN_ASSP 0x01
349 #define ENABLE_ASSP_CLOCK 0x00
350 #define STOP_ASSP_CLOCK 0x10
351 #define RESET_TOGGLE 0x40
352
353 #define ASSP_CONTROL_C 0xA6
354 #define ASSP_HOST_INT_ENABLE 0x01
355 #define FM_ADDR_REMAP_DISABLE 0x02
356 #define HOST_WRITE_PORT_ENABLE 0x08
357
358 #define ASSP_HOST_INT_STATUS 0xAC
359 #define DSP2HOST_REQ_PIORECORD 0x01
360 #define DSP2HOST_REQ_I2SRATE 0x02
361 #define DSP2HOST_REQ_TIMER 0x04
362
363 /* AC97 registers */
364 /* XXX fix this crap up */
365 /*#define AC97_RESET 0x00*/
366
367 #define AC97_VOL_MUTE_B 0x8000
368 #define AC97_VOL_M 0x1F
369 #define AC97_LEFT_VOL_S 8
370
371 #define AC97_MASTER_VOL 0x02
372 #define AC97_LINE_LEVEL_VOL 0x04
373 #define AC97_MASTER_MONO_VOL 0x06
374 #define AC97_PC_BEEP_VOL 0x0A
375 #define AC97_PC_BEEP_VOL_M 0x0F
376 #define AC97_SROUND_MASTER_VOL 0x38
377 #define AC97_PC_BEEP_VOL_S 1
378
379 /*#define AC97_PHONE_VOL 0x0C
380 #define AC97_MIC_VOL 0x0E*/
381 #define AC97_MIC_20DB_ENABLE 0x40
382
383 /*#define AC97_LINEIN_VOL 0x10
384 #define AC97_CD_VOL 0x12
385 #define AC97_VIDEO_VOL 0x14
386 #define AC97_AUX_VOL 0x16*/
387 #define AC97_PCM_OUT_VOL 0x18
388 /*#define AC97_RECORD_SELECT 0x1A*/
389 #define AC97_RECORD_MIC 0x00
390 #define AC97_RECORD_CD 0x01
391 #define AC97_RECORD_VIDEO 0x02
392 #define AC97_RECORD_AUX 0x03
393 #define AC97_RECORD_MONO_MUX 0x02
394 #define AC97_RECORD_DIGITAL 0x03
395 #define AC97_RECORD_LINE 0x04
396 #define AC97_RECORD_STEREO 0x05
397 #define AC97_RECORD_MONO 0x06
398 #define AC97_RECORD_PHONE 0x07
399
400 /*#define AC97_RECORD_GAIN 0x1C*/
401 #define AC97_RECORD_VOL_M 0x0F
402
403 /*#define AC97_GENERAL_PURPOSE 0x20*/
404 #define AC97_POWER_DOWN_CTRL 0x26
405 #define AC97_ADC_READY 0x0001
406 #define AC97_DAC_READY 0x0002
407 #define AC97_ANALOG_READY 0x0004
408 #define AC97_VREF_ON 0x0008
409 #define AC97_PR0 0x0100
410 #define AC97_PR1 0x0200
411 #define AC97_PR2 0x0400
412 #define AC97_PR3 0x0800
413 #define AC97_PR4 0x1000
414
415 #define AC97_RESERVED1 0x28
416
417 #define AC97_VENDOR_TEST 0x5A
418
419 #define AC97_CLOCK_DELAY 0x5C
420 #define AC97_LINEOUT_MUX_SEL 0x0001
421 #define AC97_MONO_MUX_SEL 0x0002
422 #define AC97_CLOCK_DELAY_SEL 0x1F
423 #define AC97_DAC_CDS_SHIFT 6
424 #define AC97_ADC_CDS_SHIFT 11
425
426 #define AC97_MULTI_CHANNEL_SEL 0x74
427
428 /*#define AC97_VENDOR_ID1 0x7C
429 #define AC97_VENDOR_ID2 0x7E*/
430
431 /*
432 * ASSP control regs
433 */
434 #define DSP_PORT_TIMER_COUNT 0x06
435
436 #define DSP_PORT_MEMORY_INDEX 0x80
437
438 #define DSP_PORT_MEMORY_TYPE 0x82
439 #define MEMTYPE_INTERNAL_CODE 0x0002
440 #define MEMTYPE_INTERNAL_DATA 0x0003
441 #define MEMTYPE_MASK 0x0003
442
443 #define DSP_PORT_MEMORY_DATA 0x84
444
445 #define DSP_PORT_CONTROL_REG_A 0xA2
446 #define DSP_PORT_CONTROL_REG_B 0xA4
447 #define DSP_PORT_CONTROL_REG_C 0xA6
448
449 #define REV_A_CODE_MEMORY_BEGIN 0x0000
450 #define REV_A_CODE_MEMORY_END 0x0FFF
451 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
452 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
453
454 #define REV_B_CODE_MEMORY_BEGIN 0x0000
455 #define REV_B_CODE_MEMORY_END 0x0BFF
456 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
457 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
458
459 #define REV_A_DATA_MEMORY_BEGIN 0x1000
460 #define REV_A_DATA_MEMORY_END 0x2FFF
461 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
462 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
463
464 #define REV_B_DATA_MEMORY_BEGIN 0x1000
465 #define REV_B_DATA_MEMORY_END 0x2BFF
466 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
467 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
468
469
470 #define NUM_UNITS_KERNEL_CODE 16
471 #define NUM_UNITS_KERNEL_DATA 2
472
473 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
474 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
475
476 /*
477 * Kernel data layout
478 */
479
480 #define DP_SHIFT_COUNT 7
481
482 #define KDATA_BASE_ADDR 0x1000
483 #define KDATA_BASE_ADDR2 0x1080
484
485 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
486 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
487 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
488 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
489 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
490 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
491 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
492 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
493 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
494
495 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
496 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
497
498 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
499 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
500 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
501 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
502 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
503 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
504 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
505 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
506 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
507 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
508
509 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
510 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
511
512 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
513 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
514
515 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
516 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
517
518 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
519 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
520 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
521
522 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
523 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
524 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
525 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
526 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
527
528 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
529 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
530 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
531
532 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
533 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
534 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
535
536 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
537 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
538 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
539 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
540 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
541 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
542 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
543 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
544 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
545 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
546
547 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
548 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
549 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
550
551 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
552 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
553
554 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
555 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
556 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
557
558 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
559 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
560 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
561 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
562 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
563 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
564
565 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
566 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
567 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
568 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
569 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
570 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
571
572 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
573 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
574 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
575 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
576 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
577 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
578
579 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
580 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
581 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
582 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
583
584 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
585 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
586
587 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
588 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
589
590 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
591 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
592 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
593 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
594 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
595
596 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
597 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
598
599 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
600 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
601 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
602
603 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
604 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
605
606 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
607
608 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
609 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
610 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
611 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
612 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
613 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
614 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
615 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
616 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
617 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
618 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
619 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
620
621 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
622 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
623 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
624 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
625
626 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
627 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
628
629 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
630 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
631 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
632 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
633
634 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
635 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
636 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
637 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
638 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
639
640 /*
641 * second 'segment' (?) reserved for mixer
642 * buffers..
643 */
644
645 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
646 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
647 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
648 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
649 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
650 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
651 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
652 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
653 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
654 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
655 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
656 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
657 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
658 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
659 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
660 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
661
662 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
663 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
664 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
665 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
666 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
667 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
668 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
669 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
670 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
671 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
672 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
673
674 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
675 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
676 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
677 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
678 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
679 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
680
681 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
682 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
683 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
684 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
685
686 /*
687 * client data area offsets
688 */
689 #define CDATA_INSTANCE_READY 0x00
690
691 #define CDATA_HOST_SRC_ADDRL 0x01
692 #define CDATA_HOST_SRC_ADDRH 0x02
693 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
694 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
695 #define CDATA_HOST_SRC_CURRENTL 0x05
696 #define CDATA_HOST_SRC_CURRENTH 0x06
697
698 #define CDATA_IN_BUF_CONNECT 0x07
699 #define CDATA_OUT_BUF_CONNECT 0x08
700
701 #define CDATA_IN_BUF_BEGIN 0x09
702 #define CDATA_IN_BUF_END_PLUS_1 0x0A
703 #define CDATA_IN_BUF_HEAD 0x0B
704 #define CDATA_IN_BUF_TAIL 0x0C
705 #define CDATA_OUT_BUF_BEGIN 0x0D
706 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
707 #define CDATA_OUT_BUF_HEAD 0x0F
708 #define CDATA_OUT_BUF_TAIL 0x10
709
710 #define CDATA_DMA_CONTROL 0x11
711 #define CDATA_RESERVED 0x12
712
713 #define CDATA_FREQUENCY 0x13
714 #define CDATA_LEFT_VOLUME 0x14
715 #define CDATA_RIGHT_VOLUME 0x15
716 #define CDATA_LEFT_SUR_VOL 0x16
717 #define CDATA_RIGHT_SUR_VOL 0x17
718
719 #define CDATA_HEADER_LEN 0x18
720
721 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
722 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
723 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
724 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
725 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
726 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
727 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
728 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
729
730 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
731 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
732 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733 #define MINISRC_BIQUAD_STAGE 2
734 #define MINISRC_COEF_LOC 0x175
735
736 #define DMACONTROL_BLOCK_MASK 0x000F
737 #define DMAC_BLOCK0_SELECTOR 0x0000
738 #define DMAC_BLOCK1_SELECTOR 0x0001
739 #define DMAC_BLOCK2_SELECTOR 0x0002
740 #define DMAC_BLOCK3_SELECTOR 0x0003
741 #define DMAC_BLOCK4_SELECTOR 0x0004
742 #define DMAC_BLOCK5_SELECTOR 0x0005
743 #define DMAC_BLOCK6_SELECTOR 0x0006
744 #define DMAC_BLOCK7_SELECTOR 0x0007
745 #define DMAC_BLOCK8_SELECTOR 0x0008
746 #define DMAC_BLOCK9_SELECTOR 0x0009
747 #define DMAC_BLOCKA_SELECTOR 0x000A
748 #define DMAC_BLOCKB_SELECTOR 0x000B
749 #define DMAC_BLOCKC_SELECTOR 0x000C
750 #define DMAC_BLOCKD_SELECTOR 0x000D
751 #define DMAC_BLOCKE_SELECTOR 0x000E
752 #define DMAC_BLOCKF_SELECTOR 0x000F
753 #define DMACONTROL_PAGE_MASK 0x00F0
754 #define DMAC_PAGE0_SELECTOR 0x0030
755 #define DMAC_PAGE1_SELECTOR 0x0020
756 #define DMAC_PAGE2_SELECTOR 0x0010
757 #define DMAC_PAGE3_SELECTOR 0x0000
758 #define DMACONTROL_AUTOREPEAT 0x1000
759 #define DMACONTROL_STOPPED 0x2000
760 #define DMACONTROL_DIRECTION 0x0100
761
762 /*
763 * an arbitrary volume we set the internal
764 * volume settings to so that the ac97 volume
765 * range is a little less insane. 0x7fff is
766 * max.
767 */
768 #define ARB_VOLUME ( 0x6800 )
769
770 /*
771 */
772
773 struct m3_list {
774 int curlen;
775 int mem_addr;
776 int max;
777 };
778
779 struct m3_dma {
780
781 int number;
782 struct snd_pcm_substream *substream;
783
784 struct assp_instance {
785 unsigned short code, data;
786 } inst;
787
788 int running;
789 int opened;
790
791 unsigned long buffer_addr;
792 int dma_size;
793 int period_size;
794 unsigned int hwptr;
795 int count;
796
797 int index[3];
798 struct m3_list *index_list[3];
799
800 int in_lists;
801
802 struct list_head list;
803
804 };
805
806 struct snd_m3 {
807
808 struct snd_card *card;
809
810 unsigned long iobase;
811
812 int irq;
813 unsigned int allegro_flag : 1;
814
815 struct snd_ac97 *ac97;
816
817 struct snd_pcm *pcm;
818
819 struct pci_dev *pci;
820
821 int dacs_active;
822 int timer_users;
823
824 struct m3_list msrc_list;
825 struct m3_list mixer_list;
826 struct m3_list adc1_list;
827 struct m3_list dma_list;
828
829 /* for storing reset state..*/
830 u8 reset_state;
831
832 int external_amp;
833 int amp_gpio; /* gpio pin # for external amp, -1 = default */
834 unsigned int hv_config; /* hardware-volume config bits */
835 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
836 (e.g. for IrDA on Dell Inspirons) */
837 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
838
839 /* midi */
840 struct snd_rawmidi *rmidi;
841
842 /* pcm streams */
843 int num_substreams;
844 struct m3_dma *substreams;
845
846 spinlock_t reg_lock;
847 spinlock_t ac97_lock;
848
849 struct snd_kcontrol *master_switch;
850 struct snd_kcontrol *master_volume;
851 struct tasklet_struct hwvol_tq;
852 unsigned int in_suspend;
853
854 #ifdef CONFIG_PM
855 u16 *suspend_mem;
856 #endif
857
858 const struct firmware *assp_kernel_image;
859 const struct firmware *assp_minisrc_image;
860 };
861
862 /*
863 * pci ids
864 */
865 static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
866 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
867 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
868 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
869 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
870 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
871 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
872 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
873 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
874 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
875 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
876 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
877 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
878 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
879 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
880 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
881 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
882 {0,},
883 };
884
885 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
886
887 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
888 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
889 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
890 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
891 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
892 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
893 { } /* END */
894 };
895
896 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
897 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
898 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
899 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
900 { } /* END */
901 };
902
903 /* hardware volume quirks */
904 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
905 /* Allegro chips */
906 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
932 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
954 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
955 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
956 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
957 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
958 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
959 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
960 /* Maestro3 chips */
961 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
977 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
978 { } /* END */
979 };
980
981 /* HP Omnibook quirks */
982 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
983 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
984 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
985 { } /* END */
986 };
987
988 /*
989 * lowlevel functions
990 */
991
992 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
993 {
994 outw(value, chip->iobase + reg);
995 }
996
997 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
998 {
999 return inw(chip->iobase + reg);
1000 }
1001
1002 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1003 {
1004 outb(value, chip->iobase + reg);
1005 }
1006
1007 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1008 {
1009 return inb(chip->iobase + reg);
1010 }
1011
1012 /*
1013 * access 16bit words to the code or data regions of the dsp's memory.
1014 * index addresses 16bit words.
1015 */
1016 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1017 {
1018 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1019 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1020 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1021 }
1022
1023 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1024 {
1025 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1026 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1027 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1028 }
1029
1030 static void snd_m3_assp_halt(struct snd_m3 *chip)
1031 {
1032 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1033 msleep(10);
1034 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1035 }
1036
1037 static void snd_m3_assp_continue(struct snd_m3 *chip)
1038 {
1039 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1040 }
1041
1042
1043 /*
1044 * This makes me sad. the maestro3 has lists
1045 * internally that must be packed.. 0 terminates,
1046 * apparently, or maybe all unused entries have
1047 * to be 0, the lists have static lengths set
1048 * by the binary code images.
1049 */
1050
1051 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1052 {
1053 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1054 list->mem_addr + list->curlen,
1055 val);
1056 return list->curlen++;
1057 }
1058
1059 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1060 {
1061 u16 val;
1062 int lastindex = list->curlen - 1;
1063
1064 if (index != lastindex) {
1065 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1066 list->mem_addr + lastindex);
1067 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068 list->mem_addr + index,
1069 val);
1070 }
1071
1072 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073 list->mem_addr + lastindex,
1074 0);
1075
1076 list->curlen--;
1077 }
1078
1079 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1080 {
1081 chip->timer_users++;
1082 if (chip->timer_users != 1)
1083 return;
1084
1085 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1086 KDATA_TIMER_COUNT_RELOAD,
1087 240);
1088
1089 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1090 KDATA_TIMER_COUNT_CURRENT,
1091 240);
1092
1093 snd_m3_outw(chip,
1094 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1095 HOST_INT_CTRL);
1096 }
1097
1098 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1099 {
1100 chip->timer_users--;
1101 if (chip->timer_users > 0)
1102 return;
1103
1104 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1105 KDATA_TIMER_COUNT_RELOAD,
1106 0);
1107
1108 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1109 KDATA_TIMER_COUNT_CURRENT,
1110 0);
1111
1112 snd_m3_outw(chip,
1113 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1114 HOST_INT_CTRL);
1115 }
1116
1117 /*
1118 * start/stop
1119 */
1120
1121 /* spinlock held! */
1122 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1123 struct snd_pcm_substream *subs)
1124 {
1125 if (! s || ! subs)
1126 return -EINVAL;
1127
1128 snd_m3_inc_timer_users(chip);
1129 switch (subs->stream) {
1130 case SNDRV_PCM_STREAM_PLAYBACK:
1131 chip->dacs_active++;
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 s->inst.data + CDATA_INSTANCE_READY, 1);
1134 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135 KDATA_MIXER_TASK_NUMBER,
1136 chip->dacs_active);
1137 break;
1138 case SNDRV_PCM_STREAM_CAPTURE:
1139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140 KDATA_ADC1_REQUEST, 1);
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 s->inst.data + CDATA_INSTANCE_READY, 1);
1143 break;
1144 }
1145 return 0;
1146 }
1147
1148 /* spinlock held! */
1149 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1150 struct snd_pcm_substream *subs)
1151 {
1152 if (! s || ! subs)
1153 return -EINVAL;
1154
1155 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1156 s->inst.data + CDATA_INSTANCE_READY, 0);
1157 snd_m3_dec_timer_users(chip);
1158 switch (subs->stream) {
1159 case SNDRV_PCM_STREAM_PLAYBACK:
1160 chip->dacs_active--;
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 KDATA_MIXER_TASK_NUMBER,
1163 chip->dacs_active);
1164 break;
1165 case SNDRV_PCM_STREAM_CAPTURE:
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 KDATA_ADC1_REQUEST, 0);
1168 break;
1169 }
1170 return 0;
1171 }
1172
1173 static int
1174 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1175 {
1176 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1177 struct m3_dma *s = subs->runtime->private_data;
1178 int err = -EINVAL;
1179
1180 if (snd_BUG_ON(!s))
1181 return -ENXIO;
1182
1183 spin_lock(&chip->reg_lock);
1184 switch (cmd) {
1185 case SNDRV_PCM_TRIGGER_START:
1186 case SNDRV_PCM_TRIGGER_RESUME:
1187 if (s->running)
1188 err = -EBUSY;
1189 else {
1190 s->running = 1;
1191 err = snd_m3_pcm_start(chip, s, subs);
1192 }
1193 break;
1194 case SNDRV_PCM_TRIGGER_STOP:
1195 case SNDRV_PCM_TRIGGER_SUSPEND:
1196 if (! s->running)
1197 err = 0; /* should return error? */
1198 else {
1199 s->running = 0;
1200 err = snd_m3_pcm_stop(chip, s, subs);
1201 }
1202 break;
1203 }
1204 spin_unlock(&chip->reg_lock);
1205 return err;
1206 }
1207
1208 /*
1209 * setup
1210 */
1211 static void
1212 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1213 {
1214 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1215 struct snd_pcm_runtime *runtime = subs->runtime;
1216
1217 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1218 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1219 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1220 } else {
1221 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1222 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1223 }
1224 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1225 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1226
1227 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1228 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1229 s->hwptr = 0;
1230 s->count = 0;
1231
1232 #define LO(x) ((x) & 0xffff)
1233 #define HI(x) LO((x) >> 16)
1234
1235 /* host dma buffer pointers */
1236 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1237 s->inst.data + CDATA_HOST_SRC_ADDRL,
1238 LO(s->buffer_addr));
1239
1240 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1241 s->inst.data + CDATA_HOST_SRC_ADDRH,
1242 HI(s->buffer_addr));
1243
1244 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1246 LO(s->buffer_addr + s->dma_size));
1247
1248 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1249 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1250 HI(s->buffer_addr + s->dma_size));
1251
1252 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1254 LO(s->buffer_addr));
1255
1256 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1257 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1258 HI(s->buffer_addr));
1259 #undef LO
1260 #undef HI
1261
1262 /* dsp buffers */
1263
1264 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265 s->inst.data + CDATA_IN_BUF_BEGIN,
1266 dsp_in_buffer);
1267
1268 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1270 dsp_in_buffer + (dsp_in_size / 2));
1271
1272 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273 s->inst.data + CDATA_IN_BUF_HEAD,
1274 dsp_in_buffer);
1275
1276 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1277 s->inst.data + CDATA_IN_BUF_TAIL,
1278 dsp_in_buffer);
1279
1280 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1281 s->inst.data + CDATA_OUT_BUF_BEGIN,
1282 dsp_out_buffer);
1283
1284 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1285 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1286 dsp_out_buffer + (dsp_out_size / 2));
1287
1288 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1289 s->inst.data + CDATA_OUT_BUF_HEAD,
1290 dsp_out_buffer);
1291
1292 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1293 s->inst.data + CDATA_OUT_BUF_TAIL,
1294 dsp_out_buffer);
1295 }
1296
1297 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1298 struct snd_pcm_runtime *runtime)
1299 {
1300 u32 freq;
1301
1302 /*
1303 * put us in the lists if we're not already there
1304 */
1305 if (! s->in_lists) {
1306 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1307 s->inst.data >> DP_SHIFT_COUNT);
1308 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1309 s->inst.data >> DP_SHIFT_COUNT);
1310 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1311 s->inst.data >> DP_SHIFT_COUNT);
1312 s->in_lists = 1;
1313 }
1314
1315 /* write to 'mono' word */
1316 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1317 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1318 runtime->channels == 2 ? 0 : 1);
1319 /* write to '8bit' word */
1320 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1321 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1322 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1323
1324 /* set up dac/adc rate */
1325 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1326 if (freq)
1327 freq--;
1328
1329 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1330 s->inst.data + CDATA_FREQUENCY,
1331 freq);
1332 }
1333
1334
1335 static const struct play_vals {
1336 u16 addr, val;
1337 } pv[] = {
1338 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1339 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1340 {SRC3_DIRECTION_OFFSET, 0} ,
1341 /* +1, +2 are stereo/16 bit */
1342 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1343 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1344 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1345 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1346 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1347 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1348 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1349 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1350 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1351 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1352 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1353 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1354 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1355 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1356 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1357 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1358 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1359 };
1360
1361
1362 /* the mode passed should be already shifted and masked */
1363 static void
1364 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1365 struct snd_pcm_substream *subs)
1366 {
1367 unsigned int i;
1368
1369 /*
1370 * some per client initializers
1371 */
1372
1373 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1375 s->inst.data + 40 + 8);
1376
1377 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1378 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1379 s->inst.code + MINISRC_COEF_LOC);
1380
1381 /* enable or disable low pass filter? */
1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1384 subs->runtime->rate > 45000 ? 0xff : 0);
1385
1386 /* tell it which way dma is going? */
1387 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1388 s->inst.data + CDATA_DMA_CONTROL,
1389 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1390
1391 /*
1392 * set an armload of static initializers
1393 */
1394 for (i = 0; i < ARRAY_SIZE(pv); i++)
1395 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1396 s->inst.data + pv[i].addr, pv[i].val);
1397 }
1398
1399 /*
1400 * Native record driver
1401 */
1402 static const struct rec_vals {
1403 u16 addr, val;
1404 } rv[] = {
1405 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1406 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1407 {SRC3_DIRECTION_OFFSET, 1} ,
1408 /* +1, +2 are stereo/16 bit */
1409 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1410 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1411 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1412 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1413 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1414 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1415 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1416 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1417 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1418 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1419 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1420 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1421 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1422 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1423 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1424 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1425 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1426 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1427 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1428 };
1429
1430 static void
1431 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1432 {
1433 unsigned int i;
1434
1435 /*
1436 * some per client initializers
1437 */
1438
1439 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1440 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1441 s->inst.data + 40 + 8);
1442
1443 /* tell it which way dma is going? */
1444 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1445 s->inst.data + CDATA_DMA_CONTROL,
1446 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1447 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1448
1449 /*
1450 * set an armload of static initializers
1451 */
1452 for (i = 0; i < ARRAY_SIZE(rv); i++)
1453 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1454 s->inst.data + rv[i].addr, rv[i].val);
1455 }
1456
1457 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1458 struct snd_pcm_hw_params *hw_params)
1459 {
1460 struct m3_dma *s = substream->runtime->private_data;
1461 int err;
1462
1463 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1464 return err;
1465 /* set buffer address */
1466 s->buffer_addr = substream->runtime->dma_addr;
1467 if (s->buffer_addr & 0x3) {
1468 snd_printk(KERN_ERR "oh my, not aligned\n");
1469 s->buffer_addr = s->buffer_addr & ~0x3;
1470 }
1471 return 0;
1472 }
1473
1474 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1475 {
1476 struct m3_dma *s;
1477
1478 if (substream->runtime->private_data == NULL)
1479 return 0;
1480 s = substream->runtime->private_data;
1481 snd_pcm_lib_free_pages(substream);
1482 s->buffer_addr = 0;
1483 return 0;
1484 }
1485
1486 static int
1487 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1488 {
1489 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1490 struct snd_pcm_runtime *runtime = subs->runtime;
1491 struct m3_dma *s = runtime->private_data;
1492
1493 if (snd_BUG_ON(!s))
1494 return -ENXIO;
1495
1496 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1497 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1498 return -EINVAL;
1499 if (runtime->rate > 48000 ||
1500 runtime->rate < 8000)
1501 return -EINVAL;
1502
1503 spin_lock_irq(&chip->reg_lock);
1504
1505 snd_m3_pcm_setup1(chip, s, subs);
1506
1507 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1508 snd_m3_playback_setup(chip, s, subs);
1509 else
1510 snd_m3_capture_setup(chip, s, subs);
1511
1512 snd_m3_pcm_setup2(chip, s, runtime);
1513
1514 spin_unlock_irq(&chip->reg_lock);
1515
1516 return 0;
1517 }
1518
1519 /*
1520 * get current pointer
1521 */
1522 static unsigned int
1523 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1524 {
1525 u16 hi = 0, lo = 0;
1526 int retry = 10;
1527 u32 addr;
1528
1529 /*
1530 * try and get a valid answer
1531 */
1532 while (retry--) {
1533 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1534 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1535
1536 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1537 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1538
1539 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1540 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1541 break;
1542 }
1543 addr = lo | ((u32)hi<<16);
1544 return (unsigned int)(addr - s->buffer_addr);
1545 }
1546
1547 static snd_pcm_uframes_t
1548 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1549 {
1550 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1551 unsigned int ptr;
1552 struct m3_dma *s = subs->runtime->private_data;
1553
1554 if (snd_BUG_ON(!s))
1555 return 0;
1556
1557 spin_lock(&chip->reg_lock);
1558 ptr = snd_m3_get_pointer(chip, s, subs);
1559 spin_unlock(&chip->reg_lock);
1560 return bytes_to_frames(subs->runtime, ptr);
1561 }
1562
1563
1564 /* update pointer */
1565 /* spinlock held! */
1566 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1567 {
1568 struct snd_pcm_substream *subs = s->substream;
1569 unsigned int hwptr;
1570 int diff;
1571
1572 if (! s->running)
1573 return;
1574
1575 hwptr = snd_m3_get_pointer(chip, s, subs);
1576
1577 /* try to avoid expensive modulo divisions */
1578 if (hwptr >= s->dma_size)
1579 hwptr %= s->dma_size;
1580
1581 diff = s->dma_size + hwptr - s->hwptr;
1582 if (diff >= s->dma_size)
1583 diff %= s->dma_size;
1584
1585 s->hwptr = hwptr;
1586 s->count += diff;
1587
1588 if (s->count >= (signed)s->period_size) {
1589
1590 if (s->count < 2 * (signed)s->period_size)
1591 s->count -= (signed)s->period_size;
1592 else
1593 s->count %= s->period_size;
1594
1595 spin_unlock(&chip->reg_lock);
1596 snd_pcm_period_elapsed(subs);
1597 spin_lock(&chip->reg_lock);
1598 }
1599 }
1600
1601 static void snd_m3_update_hw_volume(unsigned long private_data)
1602 {
1603 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1604 int x, val;
1605 unsigned long flags;
1606
1607 /* Figure out which volume control button was pushed,
1608 based on differences from the default register
1609 values. */
1610 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1611
1612 /* Reset the volume control registers. */
1613 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1614 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1615 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1616 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1617
1618 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1619 mistaking them for a mute button press. */
1620 if (chip->in_suspend)
1621 return;
1622
1623 if (!chip->master_switch || !chip->master_volume)
1624 return;
1625
1626 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1627 spin_lock_irqsave(&chip->ac97_lock, flags);
1628
1629 val = chip->ac97->regs[AC97_MASTER_VOL];
1630 switch (x) {
1631 case 0x88:
1632 /* mute */
1633 val ^= 0x8000;
1634 chip->ac97->regs[AC97_MASTER_VOL] = val;
1635 outw(val, chip->iobase + CODEC_DATA);
1636 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1637 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1638 &chip->master_switch->id);
1639 break;
1640 case 0xaa:
1641 /* volume up */
1642 if ((val & 0x7f) > 0)
1643 val--;
1644 if ((val & 0x7f00) > 0)
1645 val -= 0x0100;
1646 chip->ac97->regs[AC97_MASTER_VOL] = val;
1647 outw(val, chip->iobase + CODEC_DATA);
1648 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1649 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1650 &chip->master_volume->id);
1651 break;
1652 case 0x66:
1653 /* volume down */
1654 if ((val & 0x7f) < 0x1f)
1655 val++;
1656 if ((val & 0x7f00) < 0x1f00)
1657 val += 0x0100;
1658 chip->ac97->regs[AC97_MASTER_VOL] = val;
1659 outw(val, chip->iobase + CODEC_DATA);
1660 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1661 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1662 &chip->master_volume->id);
1663 break;
1664 }
1665 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1666 }
1667
1668 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1669 {
1670 struct snd_m3 *chip = dev_id;
1671 u8 status;
1672 int i;
1673
1674 status = inb(chip->iobase + HOST_INT_STATUS);
1675
1676 if (status == 0xff)
1677 return IRQ_NONE;
1678
1679 if (status & HV_INT_PENDING)
1680 tasklet_schedule(&chip->hwvol_tq);
1681
1682 /*
1683 * ack an assp int if its running
1684 * and has an int pending
1685 */
1686 if (status & ASSP_INT_PENDING) {
1687 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1688 if (!(ctl & STOP_ASSP_CLOCK)) {
1689 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1690 if (ctl & DSP2HOST_REQ_TIMER) {
1691 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1692 /* update adc/dac info if it was a timer int */
1693 spin_lock(&chip->reg_lock);
1694 for (i = 0; i < chip->num_substreams; i++) {
1695 struct m3_dma *s = &chip->substreams[i];
1696 if (s->running)
1697 snd_m3_update_ptr(chip, s);
1698 }
1699 spin_unlock(&chip->reg_lock);
1700 }
1701 }
1702 }
1703
1704 #if 0 /* TODO: not supported yet */
1705 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1706 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1707 #endif
1708
1709 /* ack ints */
1710 outb(status, chip->iobase + HOST_INT_STATUS);
1711
1712 return IRQ_HANDLED;
1713 }
1714
1715
1716 /*
1717 */
1718
1719 static struct snd_pcm_hardware snd_m3_playback =
1720 {
1721 .info = (SNDRV_PCM_INFO_MMAP |
1722 SNDRV_PCM_INFO_INTERLEAVED |
1723 SNDRV_PCM_INFO_MMAP_VALID |
1724 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1725 /*SNDRV_PCM_INFO_PAUSE |*/
1726 SNDRV_PCM_INFO_RESUME),
1727 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1728 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1729 .rate_min = 8000,
1730 .rate_max = 48000,
1731 .channels_min = 1,
1732 .channels_max = 2,
1733 .buffer_bytes_max = (512*1024),
1734 .period_bytes_min = 64,
1735 .period_bytes_max = (512*1024),
1736 .periods_min = 1,
1737 .periods_max = 1024,
1738 };
1739
1740 static struct snd_pcm_hardware snd_m3_capture =
1741 {
1742 .info = (SNDRV_PCM_INFO_MMAP |
1743 SNDRV_PCM_INFO_INTERLEAVED |
1744 SNDRV_PCM_INFO_MMAP_VALID |
1745 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1746 /*SNDRV_PCM_INFO_PAUSE |*/
1747 SNDRV_PCM_INFO_RESUME),
1748 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1749 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1750 .rate_min = 8000,
1751 .rate_max = 48000,
1752 .channels_min = 1,
1753 .channels_max = 2,
1754 .buffer_bytes_max = (512*1024),
1755 .period_bytes_min = 64,
1756 .period_bytes_max = (512*1024),
1757 .periods_min = 1,
1758 .periods_max = 1024,
1759 };
1760
1761
1762 /*
1763 */
1764
1765 static int
1766 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1767 {
1768 int i;
1769 struct m3_dma *s;
1770
1771 spin_lock_irq(&chip->reg_lock);
1772 for (i = 0; i < chip->num_substreams; i++) {
1773 s = &chip->substreams[i];
1774 if (! s->opened)
1775 goto __found;
1776 }
1777 spin_unlock_irq(&chip->reg_lock);
1778 return -ENOMEM;
1779 __found:
1780 s->opened = 1;
1781 s->running = 0;
1782 spin_unlock_irq(&chip->reg_lock);
1783
1784 subs->runtime->private_data = s;
1785 s->substream = subs;
1786
1787 /* set list owners */
1788 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1789 s->index_list[0] = &chip->mixer_list;
1790 } else
1791 s->index_list[0] = &chip->adc1_list;
1792 s->index_list[1] = &chip->msrc_list;
1793 s->index_list[2] = &chip->dma_list;
1794
1795 return 0;
1796 }
1797
1798 static void
1799 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1800 {
1801 struct m3_dma *s = subs->runtime->private_data;
1802
1803 if (s == NULL)
1804 return; /* not opened properly */
1805
1806 spin_lock_irq(&chip->reg_lock);
1807 if (s->substream && s->running)
1808 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1809 if (s->in_lists) {
1810 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1811 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1812 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1813 s->in_lists = 0;
1814 }
1815 s->running = 0;
1816 s->opened = 0;
1817 spin_unlock_irq(&chip->reg_lock);
1818 }
1819
1820 static int
1821 snd_m3_playback_open(struct snd_pcm_substream *subs)
1822 {
1823 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1824 struct snd_pcm_runtime *runtime = subs->runtime;
1825 int err;
1826
1827 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1828 return err;
1829
1830 runtime->hw = snd_m3_playback;
1831
1832 return 0;
1833 }
1834
1835 static int
1836 snd_m3_playback_close(struct snd_pcm_substream *subs)
1837 {
1838 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1839
1840 snd_m3_substream_close(chip, subs);
1841 return 0;
1842 }
1843
1844 static int
1845 snd_m3_capture_open(struct snd_pcm_substream *subs)
1846 {
1847 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1848 struct snd_pcm_runtime *runtime = subs->runtime;
1849 int err;
1850
1851 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1852 return err;
1853
1854 runtime->hw = snd_m3_capture;
1855
1856 return 0;
1857 }
1858
1859 static int
1860 snd_m3_capture_close(struct snd_pcm_substream *subs)
1861 {
1862 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1863
1864 snd_m3_substream_close(chip, subs);
1865 return 0;
1866 }
1867
1868 /*
1869 * create pcm instance
1870 */
1871
1872 static struct snd_pcm_ops snd_m3_playback_ops = {
1873 .open = snd_m3_playback_open,
1874 .close = snd_m3_playback_close,
1875 .ioctl = snd_pcm_lib_ioctl,
1876 .hw_params = snd_m3_pcm_hw_params,
1877 .hw_free = snd_m3_pcm_hw_free,
1878 .prepare = snd_m3_pcm_prepare,
1879 .trigger = snd_m3_pcm_trigger,
1880 .pointer = snd_m3_pcm_pointer,
1881 };
1882
1883 static struct snd_pcm_ops snd_m3_capture_ops = {
1884 .open = snd_m3_capture_open,
1885 .close = snd_m3_capture_close,
1886 .ioctl = snd_pcm_lib_ioctl,
1887 .hw_params = snd_m3_pcm_hw_params,
1888 .hw_free = snd_m3_pcm_hw_free,
1889 .prepare = snd_m3_pcm_prepare,
1890 .trigger = snd_m3_pcm_trigger,
1891 .pointer = snd_m3_pcm_pointer,
1892 };
1893
1894 static int __devinit
1895 snd_m3_pcm(struct snd_m3 * chip, int device)
1896 {
1897 struct snd_pcm *pcm;
1898 int err;
1899
1900 err = snd_pcm_new(chip->card, chip->card->driver, device,
1901 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1902 if (err < 0)
1903 return err;
1904
1905 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1906 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1907
1908 pcm->private_data = chip;
1909 pcm->info_flags = 0;
1910 strcpy(pcm->name, chip->card->driver);
1911 chip->pcm = pcm;
1912
1913 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1914 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1915
1916 return 0;
1917 }
1918
1919
1920 /*
1921 * ac97 interface
1922 */
1923
1924 /*
1925 * Wait for the ac97 serial bus to be free.
1926 * return nonzero if the bus is still busy.
1927 */
1928 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1929 {
1930 int i = 10000;
1931
1932 do {
1933 if (! (snd_m3_inb(chip, 0x30) & 1))
1934 return 0;
1935 cpu_relax();
1936 } while (i-- > 0);
1937
1938 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1939 return 1;
1940 }
1941
1942 static unsigned short
1943 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1944 {
1945 struct snd_m3 *chip = ac97->private_data;
1946 unsigned long flags;
1947 unsigned short data = 0xffff;
1948
1949 if (snd_m3_ac97_wait(chip))
1950 goto fail;
1951 spin_lock_irqsave(&chip->ac97_lock, flags);
1952 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1953 if (snd_m3_ac97_wait(chip))
1954 goto fail_unlock;
1955 data = snd_m3_inw(chip, CODEC_DATA);
1956 fail_unlock:
1957 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1958 fail:
1959 return data;
1960 }
1961
1962 static void
1963 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1964 {
1965 struct snd_m3 *chip = ac97->private_data;
1966 unsigned long flags;
1967
1968 if (snd_m3_ac97_wait(chip))
1969 return;
1970 spin_lock_irqsave(&chip->ac97_lock, flags);
1971 snd_m3_outw(chip, val, CODEC_DATA);
1972 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1973 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1974 }
1975
1976
1977 static void snd_m3_remote_codec_config(int io, int isremote)
1978 {
1979 isremote = isremote ? 1 : 0;
1980
1981 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1982 io + RING_BUS_CTRL_B);
1983 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1984 io + SDO_OUT_DEST_CTRL);
1985 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1986 io + SDO_IN_DEST_CTRL);
1987 }
1988
1989 /*
1990 * hack, returns non zero on err
1991 */
1992 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1993 {
1994 u16 ret;
1995
1996 if (snd_m3_ac97_wait(chip))
1997 return 1;
1998
1999 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2000
2001 if (snd_m3_ac97_wait(chip))
2002 return 1;
2003
2004 ret = snd_m3_inw(chip, 0x32);
2005
2006 return (ret == 0) || (ret == 0xffff);
2007 }
2008
2009 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2010 {
2011 u16 dir;
2012 int delay1 = 0, delay2 = 0, i;
2013 int io = chip->iobase;
2014
2015 if (chip->allegro_flag) {
2016 /*
2017 * the onboard codec on the allegro seems
2018 * to want to wait a very long time before
2019 * coming back to life
2020 */
2021 delay1 = 50;
2022 delay2 = 800;
2023 } else {
2024 /* maestro3 */
2025 delay1 = 20;
2026 delay2 = 500;
2027 }
2028
2029 for (i = 0; i < 5; i++) {
2030 dir = inw(io + GPIO_DIRECTION);
2031 if (!chip->irda_workaround)
2032 dir |= 0x10; /* assuming pci bus master? */
2033
2034 snd_m3_remote_codec_config(io, 0);
2035
2036 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2037 udelay(20);
2038
2039 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2040 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2041 outw(0, io + GPIO_DATA);
2042 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2043
2044 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2045
2046 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2047 udelay(5);
2048 /* ok, bring back the ac-link */
2049 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2050 outw(~0, io + GPIO_MASK);
2051
2052 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2053
2054 if (! snd_m3_try_read_vendor(chip))
2055 break;
2056
2057 delay1 += 10;
2058 delay2 += 100;
2059
2060 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2061 delay1, delay2);
2062 }
2063
2064 #if 0
2065 /* more gung-ho reset that doesn't
2066 * seem to work anywhere :)
2067 */
2068 tmp = inw(io + RING_BUS_CTRL_A);
2069 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2070 msleep(20);
2071 outw(tmp, io + RING_BUS_CTRL_A);
2072 msleep(50);
2073 #endif
2074 }
2075
2076 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2077 {
2078 struct snd_ac97_bus *pbus;
2079 struct snd_ac97_template ac97;
2080 struct snd_ctl_elem_id elem_id;
2081 int err;
2082 static struct snd_ac97_bus_ops ops = {
2083 .write = snd_m3_ac97_write,
2084 .read = snd_m3_ac97_read,
2085 };
2086
2087 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2088 return err;
2089
2090 memset(&ac97, 0, sizeof(ac97));
2091 ac97.private_data = chip;
2092 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2093 return err;
2094
2095 /* seems ac97 PCM needs initialization.. hack hack.. */
2096 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2097 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2098 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2099
2100 memset(&elem_id, 0, sizeof(elem_id));
2101 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2102 strcpy(elem_id.name, "Master Playback Switch");
2103 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2104 memset(&elem_id, 0, sizeof(elem_id));
2105 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2106 strcpy(elem_id.name, "Master Playback Volume");
2107 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2108
2109 return 0;
2110 }
2111
2112
2113 /*
2114 * initialize ASSP
2115 */
2116
2117 #define MINISRC_LPF_LEN 10
2118 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2119 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2120 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2121 };
2122
2123 static void snd_m3_assp_init(struct snd_m3 *chip)
2124 {
2125 unsigned int i;
2126 const u16 *data;
2127
2128 /* zero kernel data */
2129 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2130 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2131 KDATA_BASE_ADDR + i, 0);
2132
2133 /* zero mixer data? */
2134 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2135 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2136 KDATA_BASE_ADDR2 + i, 0);
2137
2138 /* init dma pointer */
2139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2140 KDATA_CURRENT_DMA,
2141 KDATA_DMA_XFER0);
2142
2143 /* write kernel into code memory.. */
2144 data = (const u16 *)chip->assp_kernel_image->data;
2145 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2146 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2147 REV_B_CODE_MEMORY_BEGIN + i,
2148 le16_to_cpu(data[i]));
2149 }
2150
2151 /*
2152 * We only have this one client and we know that 0x400
2153 * is free in our kernel's mem map, so lets just
2154 * drop it there. It seems that the minisrc doesn't
2155 * need vectors, so we won't bother with them..
2156 */
2157 data = (const u16 *)chip->assp_minisrc_image->data;
2158 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2159 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2160 0x400 + i, le16_to_cpu(data[i]));
2161 }
2162
2163 /*
2164 * write the coefficients for the low pass filter?
2165 */
2166 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2167 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2168 0x400 + MINISRC_COEF_LOC + i,
2169 minisrc_lpf[i]);
2170 }
2171
2172 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2173 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2174 0x8000);
2175
2176 /*
2177 * the minisrc is the only thing on
2178 * our task list..
2179 */
2180 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2181 KDATA_TASK0,
2182 0x400);
2183
2184 /*
2185 * init the mixer number..
2186 */
2187
2188 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2189 KDATA_MIXER_TASK_NUMBER,0);
2190
2191 /*
2192 * EXTREME KERNEL MASTER VOLUME
2193 */
2194 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2195 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2196 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2197 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2198
2199 chip->mixer_list.curlen = 0;
2200 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2201 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2202 chip->adc1_list.curlen = 0;
2203 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2204 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2205 chip->dma_list.curlen = 0;
2206 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2207 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2208 chip->msrc_list.curlen = 0;
2209 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2210 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2211 }
2212
2213
2214 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2215 {
2216 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2217 MINISRC_IN_BUFFER_SIZE / 2 +
2218 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2219 int address, i;
2220
2221 /*
2222 * the revb memory map has 0x1100 through 0x1c00
2223 * free.
2224 */
2225
2226 /*
2227 * align instance address to 256 bytes so that its
2228 * shifted list address is aligned.
2229 * list address = (mem address >> 1) >> 7;
2230 */
2231 data_bytes = ALIGN(data_bytes, 256);
2232 address = 0x1100 + ((data_bytes/2) * index);
2233
2234 if ((address + (data_bytes/2)) >= 0x1c00) {
2235 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2236 data_bytes, index, address);
2237 return -ENOMEM;
2238 }
2239
2240 s->number = index;
2241 s->inst.code = 0x400;
2242 s->inst.data = address;
2243
2244 for (i = data_bytes / 2; i > 0; address++, i--) {
2245 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2246 address, 0);
2247 }
2248
2249 return 0;
2250 }
2251
2252
2253 /*
2254 * this works for the reference board, have to find
2255 * out about others
2256 *
2257 * this needs more magic for 4 speaker, but..
2258 */
2259 static void
2260 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2261 {
2262 int io = chip->iobase;
2263 u16 gpo, polarity;
2264
2265 if (! chip->external_amp)
2266 return;
2267
2268 polarity = enable ? 0 : 1;
2269 polarity = polarity << chip->amp_gpio;
2270 gpo = 1 << chip->amp_gpio;
2271
2272 outw(~gpo, io + GPIO_MASK);
2273
2274 outw(inw(io + GPIO_DIRECTION) | gpo,
2275 io + GPIO_DIRECTION);
2276
2277 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2278 io + GPIO_DATA);
2279
2280 outw(0xffff, io + GPIO_MASK);
2281 }
2282
2283 static void
2284 snd_m3_hv_init(struct snd_m3 *chip)
2285 {
2286 unsigned long io = chip->iobase;
2287 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2288
2289 if (!chip->is_omnibook)
2290 return;
2291
2292 /*
2293 * Volume buttons on some HP OmniBook laptops
2294 * require some GPIO magic to work correctly.
2295 */
2296 outw(0xffff, io + GPIO_MASK);
2297 outw(0x0000, io + GPIO_DATA);
2298
2299 outw(~val, io + GPIO_MASK);
2300 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2301 outw(val, io + GPIO_MASK);
2302
2303 outw(0xffff, io + GPIO_MASK);
2304 }
2305
2306 static int
2307 snd_m3_chip_init(struct snd_m3 *chip)
2308 {
2309 struct pci_dev *pcidev = chip->pci;
2310 unsigned long io = chip->iobase;
2311 u32 n;
2312 u16 w;
2313 u8 t; /* makes as much sense as 'n', no? */
2314
2315 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2316 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2317 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2318 DISABLE_LEGACY);
2319 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2320
2321 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2322 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2323 n |= chip->hv_config;
2324 /* For some reason we must always use reduced debounce. */
2325 n |= REDUCED_DEBOUNCE;
2326 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2327 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2328
2329 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2330 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2331 n &= ~INT_CLK_SELECT;
2332 if (!chip->allegro_flag) {
2333 n &= ~INT_CLK_MULT_ENABLE;
2334 n |= INT_CLK_SRC_NOT_PCI;
2335 }
2336 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2337 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2338
2339 if (chip->allegro_flag) {
2340 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2341 n |= IN_CLK_12MHZ_SELECT;
2342 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2343 }
2344
2345 t = inb(chip->iobase + ASSP_CONTROL_A);
2346 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2347 t |= ASSP_CLK_49MHZ_SELECT;
2348 t |= ASSP_0_WS_ENABLE;
2349 outb(t, chip->iobase + ASSP_CONTROL_A);
2350
2351 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2352 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2353
2354 outb(0x00, io + HARDWARE_VOL_CTRL);
2355 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2356 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2357 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2358 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2359
2360 return 0;
2361 }
2362
2363 static void
2364 snd_m3_enable_ints(struct snd_m3 *chip)
2365 {
2366 unsigned long io = chip->iobase;
2367 unsigned short val;
2368
2369 /* TODO: MPU401 not supported yet */
2370 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2371 if (chip->hv_config & HV_CTRL_ENABLE)
2372 val |= HV_INT_ENABLE;
2373 outw(val, io + HOST_INT_CTRL);
2374 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2375 io + ASSP_CONTROL_C);
2376 }
2377
2378
2379 /*
2380 */
2381
2382 static int snd_m3_free(struct snd_m3 *chip)
2383 {
2384 struct m3_dma *s;
2385 int i;
2386
2387 if (chip->substreams) {
2388 spin_lock_irq(&chip->reg_lock);
2389 for (i = 0; i < chip->num_substreams; i++) {
2390 s = &chip->substreams[i];
2391 /* check surviving pcms; this should not happen though.. */
2392 if (s->substream && s->running)
2393 snd_m3_pcm_stop(chip, s, s->substream);
2394 }
2395 spin_unlock_irq(&chip->reg_lock);
2396 kfree(chip->substreams);
2397 }
2398 if (chip->iobase) {
2399 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2400 }
2401
2402 #ifdef CONFIG_PM
2403 vfree(chip->suspend_mem);
2404 #endif
2405
2406 if (chip->irq >= 0)
2407 free_irq(chip->irq, chip);
2408
2409 if (chip->iobase)
2410 pci_release_regions(chip->pci);
2411
2412 release_firmware(chip->assp_kernel_image);
2413 release_firmware(chip->assp_minisrc_image);
2414
2415 pci_disable_device(chip->pci);
2416 kfree(chip);
2417 return 0;
2418 }
2419
2420
2421 /*
2422 * APM support
2423 */
2424 #ifdef CONFIG_PM
2425 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2426 {
2427 struct snd_card *card = pci_get_drvdata(pci);
2428 struct snd_m3 *chip = card->private_data;
2429 int i, dsp_index;
2430
2431 if (chip->suspend_mem == NULL)
2432 return 0;
2433
2434 chip->in_suspend = 1;
2435 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2436 snd_pcm_suspend_all(chip->pcm);
2437 snd_ac97_suspend(chip->ac97);
2438
2439 msleep(10); /* give the assp a chance to idle.. */
2440
2441 snd_m3_assp_halt(chip);
2442
2443 /* save dsp image */
2444 dsp_index = 0;
2445 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2446 chip->suspend_mem[dsp_index++] =
2447 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2448 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2449 chip->suspend_mem[dsp_index++] =
2450 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2451
2452 pci_disable_device(pci);
2453 pci_save_state(pci);
2454 pci_set_power_state(pci, pci_choose_state(pci, state));
2455 return 0;
2456 }
2457
2458 static int m3_resume(struct pci_dev *pci)
2459 {
2460 struct snd_card *card = pci_get_drvdata(pci);
2461 struct snd_m3 *chip = card->private_data;
2462 int i, dsp_index;
2463
2464 if (chip->suspend_mem == NULL)
2465 return 0;
2466
2467 pci_set_power_state(pci, PCI_D0);
2468 pci_restore_state(pci);
2469 if (pci_enable_device(pci) < 0) {
2470 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2471 "disabling device\n");
2472 snd_card_disconnect(card);
2473 return -EIO;
2474 }
2475 pci_set_master(pci);
2476
2477 /* first lets just bring everything back. .*/
2478 snd_m3_outw(chip, 0, 0x54);
2479 snd_m3_outw(chip, 0, 0x56);
2480
2481 snd_m3_chip_init(chip);
2482 snd_m3_assp_halt(chip);
2483 snd_m3_ac97_reset(chip);
2484
2485 /* restore dsp image */
2486 dsp_index = 0;
2487 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2488 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2489 chip->suspend_mem[dsp_index++]);
2490 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2491 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2492 chip->suspend_mem[dsp_index++]);
2493
2494 /* tell the dma engine to restart itself */
2495 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2496 KDATA_DMA_ACTIVE, 0);
2497
2498 /* restore ac97 registers */
2499 snd_ac97_resume(chip->ac97);
2500
2501 snd_m3_assp_continue(chip);
2502 snd_m3_enable_ints(chip);
2503 snd_m3_amp_enable(chip, 1);
2504
2505 snd_m3_hv_init(chip);
2506
2507 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2508 chip->in_suspend = 0;
2509 return 0;
2510 }
2511 #endif /* CONFIG_PM */
2512
2513
2514 /*
2515 */
2516
2517 static int snd_m3_dev_free(struct snd_device *device)
2518 {
2519 struct snd_m3 *chip = device->device_data;
2520 return snd_m3_free(chip);
2521 }
2522
2523 static int __devinit
2524 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2525 int enable_amp,
2526 int amp_gpio,
2527 struct snd_m3 **chip_ret)
2528 {
2529 struct snd_m3 *chip;
2530 int i, err;
2531 const struct snd_pci_quirk *quirk;
2532 static struct snd_device_ops ops = {
2533 .dev_free = snd_m3_dev_free,
2534 };
2535
2536 *chip_ret = NULL;
2537
2538 if (pci_enable_device(pci))
2539 return -EIO;
2540
2541 /* check, if we can restrict PCI DMA transfers to 28 bits */
2542 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2543 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
2544 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2545 pci_disable_device(pci);
2546 return -ENXIO;
2547 }
2548
2549 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2550 if (chip == NULL) {
2551 pci_disable_device(pci);
2552 return -ENOMEM;
2553 }
2554
2555 spin_lock_init(&chip->reg_lock);
2556 spin_lock_init(&chip->ac97_lock);
2557
2558 switch (pci->device) {
2559 case PCI_DEVICE_ID_ESS_ALLEGRO:
2560 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2561 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2562 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2563 chip->allegro_flag = 1;
2564 break;
2565 }
2566
2567 chip->card = card;
2568 chip->pci = pci;
2569 chip->irq = -1;
2570
2571 chip->external_amp = enable_amp;
2572 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2573 chip->amp_gpio = amp_gpio;
2574 else {
2575 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2576 if (quirk) {
2577 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2578 "for '%s'\n", quirk->name);
2579 chip->amp_gpio = quirk->value;
2580 } else if (chip->allegro_flag)
2581 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2582 else /* presumably this is for all 'maestro3's.. */
2583 chip->amp_gpio = GPO_EXT_AMP_M3;
2584 }
2585
2586 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2587 if (quirk) {
2588 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2589 "for '%s'\n", quirk->name);
2590 chip->irda_workaround = 1;
2591 }
2592 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2593 if (quirk)
2594 chip->hv_config = quirk->value;
2595 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2596 chip->is_omnibook = 1;
2597
2598 chip->num_substreams = NR_DSPS;
2599 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2600 GFP_KERNEL);
2601 if (chip->substreams == NULL) {
2602 kfree(chip);
2603 pci_disable_device(pci);
2604 return -ENOMEM;
2605 }
2606
2607 err = request_firmware(&chip->assp_kernel_image,
2608 "ess/maestro3_assp_kernel.fw", &pci->dev);
2609 if (err < 0) {
2610 snd_m3_free(chip);
2611 return err;
2612 }
2613
2614 err = request_firmware(&chip->assp_minisrc_image,
2615 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2616 if (err < 0) {
2617 snd_m3_free(chip);
2618 return err;
2619 }
2620
2621 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2622 snd_m3_free(chip);
2623 return err;
2624 }
2625 chip->iobase = pci_resource_start(pci, 0);
2626
2627 /* just to be sure */
2628 pci_set_master(pci);
2629
2630 snd_m3_chip_init(chip);
2631 snd_m3_assp_halt(chip);
2632
2633 snd_m3_ac97_reset(chip);
2634
2635 snd_m3_amp_enable(chip, 1);
2636
2637 snd_m3_hv_init(chip);
2638
2639 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2640
2641 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2642 card->driver, chip)) {
2643 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2644 snd_m3_free(chip);
2645 return -ENOMEM;
2646 }
2647 chip->irq = pci->irq;
2648
2649 #ifdef CONFIG_PM
2650 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2651 if (chip->suspend_mem == NULL)
2652 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2653 #endif
2654
2655 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2656 snd_m3_free(chip);
2657 return err;
2658 }
2659
2660 if ((err = snd_m3_mixer(chip)) < 0)
2661 return err;
2662
2663 for (i = 0; i < chip->num_substreams; i++) {
2664 struct m3_dma *s = &chip->substreams[i];
2665 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2666 return err;
2667 }
2668
2669 if ((err = snd_m3_pcm(chip, 0)) < 0)
2670 return err;
2671
2672 snd_m3_enable_ints(chip);
2673 snd_m3_assp_continue(chip);
2674
2675 snd_card_set_dev(card, &pci->dev);
2676
2677 *chip_ret = chip;
2678
2679 return 0;
2680 }
2681
2682 /*
2683 */
2684 static int __devinit
2685 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2686 {
2687 static int dev;
2688 struct snd_card *card;
2689 struct snd_m3 *chip;
2690 int err;
2691
2692 /* don't pick up modems */
2693 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2694 return -ENODEV;
2695
2696 if (dev >= SNDRV_CARDS)
2697 return -ENODEV;
2698 if (!enable[dev]) {
2699 dev++;
2700 return -ENOENT;
2701 }
2702
2703 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2704 if (err < 0)
2705 return err;
2706
2707 switch (pci->device) {
2708 case PCI_DEVICE_ID_ESS_ALLEGRO:
2709 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2710 strcpy(card->driver, "Allegro");
2711 break;
2712 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2713 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2714 strcpy(card->driver, "Canyon3D-2");
2715 break;
2716 default:
2717 strcpy(card->driver, "Maestro3");
2718 break;
2719 }
2720
2721 if ((err = snd_m3_create(card, pci,
2722 external_amp[dev],
2723 amp_gpio[dev],
2724 &chip)) < 0) {
2725 snd_card_free(card);
2726 return err;
2727 }
2728 card->private_data = chip;
2729
2730 sprintf(card->shortname, "ESS %s PCI", card->driver);
2731 sprintf(card->longname, "%s at 0x%lx, irq %d",
2732 card->shortname, chip->iobase, chip->irq);
2733
2734 if ((err = snd_card_register(card)) < 0) {
2735 snd_card_free(card);
2736 return err;
2737 }
2738
2739 #if 0 /* TODO: not supported yet */
2740 /* TODO enable MIDI IRQ and I/O */
2741 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2742 chip->iobase + MPU401_DATA_PORT,
2743 MPU401_INFO_INTEGRATED,
2744 chip->irq, 0, &chip->rmidi);
2745 if (err < 0)
2746 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2747 #endif
2748
2749 pci_set_drvdata(pci, card);
2750 dev++;
2751 return 0;
2752 }
2753
2754 static void __devexit snd_m3_remove(struct pci_dev *pci)
2755 {
2756 snd_card_free(pci_get_drvdata(pci));
2757 pci_set_drvdata(pci, NULL);
2758 }
2759
2760 static struct pci_driver driver = {
2761 .name = "Maestro3",
2762 .id_table = snd_m3_ids,
2763 .probe = snd_m3_probe,
2764 .remove = __devexit_p(snd_m3_remove),
2765 #ifdef CONFIG_PM
2766 .suspend = m3_suspend,
2767 .resume = m3_resume,
2768 #endif
2769 };
2770
2771 static int __init alsa_card_m3_init(void)
2772 {
2773 return pci_register_driver(&driver);
2774 }
2775
2776 static void __exit alsa_card_m3_exit(void)
2777 {
2778 pci_unregister_driver(&driver);
2779 }
2780
2781 module_init(alsa_card_m3_init)
2782 module_exit(alsa_card_m3_exit)
Linux ARM platform port for MOXA ART SoC