?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[NET_SCHED]: sch_htb: use hrtimer based watchdog
[linux-2.6.22.y-op.git] / drivers / video / s3fb.c
blob3091b20124b45eb94d609da9a9702a92e9e1c9c1
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
28 #include <video/vga.h>
29
30 #ifdef CONFIG_MTRR
31 #include <asm/mtrr.h>
32 #endif
33
34 struct s3fb_info {
35 int chip, rev, mclk_freq;
36 int mtrr_reg;
37 struct vgastate state;
38 struct mutex open_lock;
39 unsigned int ref_count;
40 u32 pseudo_palette[16];
41 };
42
43
44 /* ------------------------------------------------------------------------- */
45
46 static const struct svga_fb_format s3fb_formats[] = {
47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
55 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
59 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
63 SVGA_FORMAT_END
64 };
65
66
67 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
68 60000, 240000, 14318};
69
70 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
71
72 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
74 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
76 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
77
78 #define CHIP_UNKNOWN 0x00
79 #define CHIP_732_TRIO32 0x01
80 #define CHIP_764_TRIO64 0x02
81 #define CHIP_765_TRIO64VP 0x03
82 #define CHIP_767_TRIO64UVP 0x04
83 #define CHIP_775_TRIO64V2_DX 0x05
84 #define CHIP_785_TRIO64V2_GX 0x06
85 #define CHIP_551_PLATO_PX 0x07
86 #define CHIP_M65_AURORA64VP 0x08
87 #define CHIP_325_VIRGE 0x09
88 #define CHIP_988_VIRGE_VX 0x0A
89 #define CHIP_375_VIRGE_DX 0x0B
90 #define CHIP_385_VIRGE_GX 0x0C
91 #define CHIP_356_VIRGE_GX2 0x0D
92 #define CHIP_357_VIRGE_GX2P 0x0E
93 #define CHIP_359_VIRGE_GX2P 0x0F
94
95 #define CHIP_XXX_TRIO 0x80
96 #define CHIP_XXX_TRIO64V2_DXGX 0x81
97 #define CHIP_XXX_VIRGE_DXGX 0x82
98
99 #define CHIP_UNDECIDED_FLAG 0x80
100 #define CHIP_MASK 0xFF
101
102 /* CRT timing register sets */
103
104 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
105 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
106 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
107 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
108 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
109 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
110
111 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
112 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
113 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
114 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
115 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
116 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
117
118 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
119 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
120 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
121
122 static const struct svga_timing_regs s3_timing_regs = {
123 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
124 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
125 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
126 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
127 };
128
129
130 /* ------------------------------------------------------------------------- */
131
132 /* Module parameters */
133
134
135 static char *mode = "640x480-8@60";
136
137 #ifdef CONFIG_MTRR
138 static int mtrr = 1;
139 #endif
140
141 static int fasttext = 1;
142
143
144 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
145 MODULE_LICENSE("GPL");
146 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
147
148 module_param(mode, charp, 0444);
149 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
150
151 #ifdef CONFIG_MTRR
152 module_param(mtrr, int, 0444);
153 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
154 #endif
155
156 module_param(fasttext, int, 0644);
157 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
158
159
160 /* ------------------------------------------------------------------------- */
161
162 /* Set font in S3 fast text mode */
163
164 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
165 {
166 const u8 *font = map->data;
167 u8* fb = (u8 *) info->screen_base;
168 int i, c;
169
170 if ((map->width != 8) || (map->height != 16) ||
171 (map->depth != 1) || (map->length != 256)) {
172 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
173 info->node, map->width, map->height, map->depth, map->length);
174 return;
175 }
176
177 fb += 2;
178 for (i = 0; i < map->height; i++) {
179 for (c = 0; c < map->length; c++) {
180 fb[c * 4] = font[c * map->height + i];
181 }
182 fb += 1024;
183 }
184 }
185
186
187
188 static struct fb_tile_ops s3fb_tile_ops = {
189 .fb_settile = svga_settile,
190 .fb_tilecopy = svga_tilecopy,
191 .fb_tilefill = svga_tilefill,
192 .fb_tileblit = svga_tileblit,
193 .fb_tilecursor = svga_tilecursor,
194 };
195
196 static struct fb_tile_ops s3fb_fast_tile_ops = {
197 .fb_settile = s3fb_settile_fast,
198 .fb_tilecopy = svga_tilecopy,
199 .fb_tilefill = svga_tilefill,
200 .fb_tileblit = svga_tileblit,
201 .fb_tilecursor = svga_tilecursor,
202 };
203
204
205 /* ------------------------------------------------------------------------- */
206
207 /* image data is MSB-first, fb structure is MSB-first too */
208 static inline u32 expand_color(u32 c)
209 {
210 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
211 }
212
213 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
214 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
215 {
216 u32 fg = expand_color(image->fg_color);
217 u32 bg = expand_color(image->bg_color);
218 const u8 *src1, *src;
219 u8 __iomem *dst1;
220 u32 __iomem *dst;
221 u32 val;
222 int x, y;
223
224 src1 = image->data;
225 dst1 = info->screen_base + (image->dy * info->fix.line_length)
226 + ((image->dx / 8) * 4);
227
228 for (y = 0; y < image->height; y++) {
229 src = src1;
230 dst = (u32 __iomem *) dst1;
231 for (x = 0; x < image->width; x += 8) {
232 val = *(src++) * 0x01010101;
233 val = (val & fg) | (~val & bg);
234 fb_writel(val, dst++);
235 }
236 src1 += image->width / 8;
237 dst1 += info->fix.line_length;
238 }
239
240 }
241
242 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
243 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
244 {
245 u32 fg = expand_color(rect->color);
246 u8 __iomem *dst1;
247 u32 __iomem *dst;
248 int x, y;
249
250 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
251 + ((rect->dx / 8) * 4);
252
253 for (y = 0; y < rect->height; y++) {
254 dst = (u32 __iomem *) dst1;
255 for (x = 0; x < rect->width; x += 8) {
256 fb_writel(fg, dst++);
257 }
258 dst1 += info->fix.line_length;
259 }
260 }
261
262
263 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
264 static inline u32 expand_pixel(u32 c)
265 {
266 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
267 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
268 }
269
270 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
271 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
272 {
273 u32 fg = image->fg_color * 0x11111111;
274 u32 bg = image->bg_color * 0x11111111;
275 const u8 *src1, *src;
276 u8 __iomem *dst1;
277 u32 __iomem *dst;
278 u32 val;
279 int x, y;
280
281 src1 = image->data;
282 dst1 = info->screen_base + (image->dy * info->fix.line_length)
283 + ((image->dx / 8) * 4);
284
285 for (y = 0; y < image->height; y++) {
286 src = src1;
287 dst = (u32 __iomem *) dst1;
288 for (x = 0; x < image->width; x += 8) {
289 val = expand_pixel(*(src++));
290 val = (val & fg) | (~val & bg);
291 fb_writel(val, dst++);
292 }
293 src1 += image->width / 8;
294 dst1 += info->fix.line_length;
295 }
296 }
297
298 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
299 {
300 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
301 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
302 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
303 s3fb_iplan_imageblit(info, image);
304 else
305 s3fb_cfb4_imageblit(info, image);
306 } else
307 cfb_imageblit(info, image);
308 }
309
310 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
311 {
312 if ((info->var.bits_per_pixel == 4)
313 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
314 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
315 s3fb_iplan_fillrect(info, rect);
316 else
317 cfb_fillrect(info, rect);
318 }
319
320
321
322 /* ------------------------------------------------------------------------- */
323
324
325 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
326 {
327 u16 m, n, r;
328 u8 regval;
329
330 svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
331
332 /* Set VGA misc register */
333 regval = vga_r(NULL, VGA_MIS_R);
334 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
335
336 /* Set S3 clock registers */
337 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
338 vga_wseq(NULL, 0x13, m - 2);
339
340 udelay(1000);
341
342 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
343 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
344 vga_wseq(NULL, 0x15, regval & ~(1<<5));
345 vga_wseq(NULL, 0x15, regval | (1<<5));
346 vga_wseq(NULL, 0x15, regval & ~(1<<5));
347 }
348
349
350 /* Open framebuffer */
351
352 static int s3fb_open(struct fb_info *info, int user)
353 {
354 struct s3fb_info *par = info->par;
355
356 mutex_lock(&(par->open_lock));
357 if (par->ref_count == 0) {
358 memset(&(par->state), 0, sizeof(struct vgastate));
359 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
360 par->state.num_crtc = 0x70;
361 par->state.num_seq = 0x20;
362 save_vga(&(par->state));
363 }
364
365 par->ref_count++;
366 mutex_unlock(&(par->open_lock));
367
368 return 0;
369 }
370
371 /* Close framebuffer */
372
373 static int s3fb_release(struct fb_info *info, int user)
374 {
375 struct s3fb_info *par = info->par;
376
377 mutex_lock(&(par->open_lock));
378 if (par->ref_count == 0) {
379 mutex_unlock(&(par->open_lock));
380 return -EINVAL;
381 }
382
383 if (par->ref_count == 1)
384 restore_vga(&(par->state));
385
386 par->ref_count--;
387 mutex_unlock(&(par->open_lock));
388
389 return 0;
390 }
391
392 /* Validate passed in var */
393
394 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
395 {
396 struct s3fb_info *par = info->par;
397 int rv, mem, step;
398
399 /* Find appropriate format */
400 rv = svga_match_format (s3fb_formats, var, NULL);
401 if ((rv < 0) || ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)))
402 { /* 24bpp on VIRGE VX, 32bpp on others */
403 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
404 return rv;
405 }
406
407 /* Do not allow to have real resoulution larger than virtual */
408 if (var->xres > var->xres_virtual)
409 var->xres_virtual = var->xres;
410
411 if (var->yres > var->yres_virtual)
412 var->yres_virtual = var->yres;
413
414 /* Round up xres_virtual to have proper alignment of lines */
415 step = s3fb_formats[rv].xresstep - 1;
416 var->xres_virtual = (var->xres_virtual+step) & ~step;
417
418 /* Check whether have enough memory */
419 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
420 if (mem > info->screen_size)
421 {
422 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
423 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
424 return -EINVAL;
425 }
426
427 rv = svga_check_timings (&s3_timing_regs, var, info->node);
428 if (rv < 0)
429 {
430 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
431 return rv;
432 }
433
434 return 0;
435 }
436
437 /* Set video mode from par */
438
439 static int s3fb_set_par(struct fb_info *info)
440 {
441 struct s3fb_info *par = info->par;
442 u32 value, mode, hmul, offset_value, screen_size, multiplex;
443 u32 bpp = info->var.bits_per_pixel;
444
445 if (bpp != 0) {
446 info->fix.ypanstep = 1;
447 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
448
449 info->flags &= ~FBINFO_MISC_TILEBLITTING;
450 info->tileops = NULL;
451
452 offset_value = (info->var.xres_virtual * bpp) / 64;
453 screen_size = info->var.yres_virtual * info->fix.line_length;
454 } else {
455 info->fix.ypanstep = 16;
456 info->fix.line_length = 0;
457
458 info->flags |= FBINFO_MISC_TILEBLITTING;
459 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
460
461 offset_value = info->var.xres_virtual / 16;
462 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
463 }
464
465 info->var.xoffset = 0;
466 info->var.yoffset = 0;
467 info->var.activate = FB_ACTIVATE_NOW;
468
469 /* Unlock registers */
470 vga_wcrt(NULL, 0x38, 0x48);
471 vga_wcrt(NULL, 0x39, 0xA5);
472 vga_wseq(NULL, 0x08, 0x06);
473 svga_wcrt_mask(0x11, 0x00, 0x80);
474
475 /* Blank screen and turn off sync */
476 svga_wseq_mask(0x01, 0x20, 0x20);
477 svga_wcrt_mask(0x17, 0x00, 0x80);
478
479 /* Set default values */
480 svga_set_default_gfx_regs();
481 svga_set_default_atc_regs();
482 svga_set_default_seq_regs();
483 svga_set_default_crt_regs();
484 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
485 svga_wcrt_multi(s3_start_address_regs, 0);
486
487 /* S3 specific initialization */
488 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
489 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
490
491 /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
492 /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
493 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
494 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
495
496 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
497
498 /* svga_wcrt_mask(0x58, 0x03, 0x03); */
499
500 /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
501 /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
502
503
504 /* Set the offset register */
505 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
506 svga_wcrt_multi(s3_offset_regs, offset_value);
507
508 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
509 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
510 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
511 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
512
513 vga_wcrt(NULL, 0x3A, 0x35);
514 svga_wattr(0x33, 0x00);
515
516 if (info->var.vmode & FB_VMODE_DOUBLE)
517 svga_wcrt_mask(0x09, 0x80, 0x80);
518 else
519 svga_wcrt_mask(0x09, 0x00, 0x80);
520
521 if (info->var.vmode & FB_VMODE_INTERLACED)
522 svga_wcrt_mask(0x42, 0x20, 0x20);
523 else
524 svga_wcrt_mask(0x42, 0x00, 0x20);
525
526 /* Disable hardware graphics cursor */
527 svga_wcrt_mask(0x45, 0x00, 0x01);
528 /* Disable Streams engine */
529 svga_wcrt_mask(0x67, 0x00, 0x0C);
530
531 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
532
533 /* S3 virge DX hack */
534 if (par->chip == CHIP_375_VIRGE_DX) {
535 vga_wcrt(NULL, 0x86, 0x80);
536 vga_wcrt(NULL, 0x90, 0x00);
537 }
538
539 /* S3 virge VX hack */
540 if (par->chip == CHIP_988_VIRGE_VX) {
541 vga_wcrt(NULL, 0x50, 0x00);
542 vga_wcrt(NULL, 0x67, 0x50);
543
544 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
545 vga_wcrt(NULL, 0x66, 0x90);
546 }
547
548 svga_wcrt_mask(0x31, 0x00, 0x40);
549 multiplex = 0;
550 hmul = 1;
551
552 /* Set mode-specific register values */
553 switch (mode) {
554 case 0:
555 pr_debug("fb%d: text mode\n", info->node);
556 svga_set_textmode_vga_regs();
557
558 /* Set additional registers like in 8-bit mode */
559 svga_wcrt_mask(0x50, 0x00, 0x30);
560 svga_wcrt_mask(0x67, 0x00, 0xF0);
561
562 /* Disable enhanced mode */
563 svga_wcrt_mask(0x3A, 0x00, 0x30);
564
565 if (fasttext) {
566 pr_debug("fb%d: high speed text mode set\n", info->node);
567 svga_wcrt_mask(0x31, 0x40, 0x40);
568 }
569 break;
570 case 1:
571 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
572 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
573
574 /* Set additional registers like in 8-bit mode */
575 svga_wcrt_mask(0x50, 0x00, 0x30);
576 svga_wcrt_mask(0x67, 0x00, 0xF0);
577
578 /* disable enhanced mode */
579 svga_wcrt_mask(0x3A, 0x00, 0x30);
580 break;
581 case 2:
582 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
583
584 /* Set additional registers like in 8-bit mode */
585 svga_wcrt_mask(0x50, 0x00, 0x30);
586 svga_wcrt_mask(0x67, 0x00, 0xF0);
587
588 /* disable enhanced mode */
589 svga_wcrt_mask(0x3A, 0x00, 0x30);
590 break;
591 case 3:
592 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
593 if (info->var.pixclock > 20000) {
594 svga_wcrt_mask(0x50, 0x00, 0x30);
595 svga_wcrt_mask(0x67, 0x00, 0xF0);
596 } else {
597 svga_wcrt_mask(0x50, 0x00, 0x30);
598 svga_wcrt_mask(0x67, 0x10, 0xF0);
599 multiplex = 1;
600 }
601 break;
602 case 4:
603 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
604 if (par->chip == CHIP_988_VIRGE_VX) {
605 if (info->var.pixclock > 20000)
606 svga_wcrt_mask(0x67, 0x20, 0xF0);
607 else
608 svga_wcrt_mask(0x67, 0x30, 0xF0);
609 } else {
610 svga_wcrt_mask(0x50, 0x10, 0x30);
611 svga_wcrt_mask(0x67, 0x30, 0xF0);
612 hmul = 2;
613 }
614 break;
615 case 5:
616 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
617 if (par->chip == CHIP_988_VIRGE_VX) {
618 if (info->var.pixclock > 20000)
619 svga_wcrt_mask(0x67, 0x40, 0xF0);
620 else
621 svga_wcrt_mask(0x67, 0x50, 0xF0);
622 } else {
623 svga_wcrt_mask(0x50, 0x10, 0x30);
624 svga_wcrt_mask(0x67, 0x50, 0xF0);
625 hmul = 2;
626 }
627 break;
628 case 6:
629 /* VIRGE VX case */
630 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
631 svga_wcrt_mask(0x67, 0xD0, 0xF0);
632 break;
633 case 7:
634 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
635 svga_wcrt_mask(0x50, 0x30, 0x30);
636 svga_wcrt_mask(0x67, 0xD0, 0xF0);
637 break;
638 default:
639 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
640 return -EINVAL;
641 }
642
643 if (par->chip != CHIP_988_VIRGE_VX) {
644 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
645 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
646 }
647
648 s3_set_pixclock(info, info->var.pixclock);
649 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
650 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
651 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
652 hmul, info->node);
653
654 /* Set interlaced mode start/end register */
655 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
656 value = ((value * hmul) / 8) - 5;
657 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
658
659 memset((u8*)info->screen_base, 0x00, screen_size);
660 /* Device and screen back on */
661 svga_wcrt_mask(0x17, 0x80, 0x80);
662 svga_wseq_mask(0x01, 0x00, 0x20);
663
664 return 0;
665 }
666
667 /* Set a colour register */
668
669 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
670 u_int transp, struct fb_info *fb)
671 {
672 switch (fb->var.bits_per_pixel) {
673 case 0:
674 case 4:
675 if (regno >= 16)
676 return -EINVAL;
677
678 if ((fb->var.bits_per_pixel == 4) &&
679 (fb->var.nonstd == 0)) {
680 outb(0xF0, VGA_PEL_MSK);
681 outb(regno*16, VGA_PEL_IW);
682 } else {
683 outb(0x0F, VGA_PEL_MSK);
684 outb(regno, VGA_PEL_IW);
685 }
686 outb(red >> 10, VGA_PEL_D);
687 outb(green >> 10, VGA_PEL_D);
688 outb(blue >> 10, VGA_PEL_D);
689 break;
690 case 8:
691 if (regno >= 256)
692 return -EINVAL;
693
694 outb(0xFF, VGA_PEL_MSK);
695 outb(regno, VGA_PEL_IW);
696 outb(red >> 10, VGA_PEL_D);
697 outb(green >> 10, VGA_PEL_D);
698 outb(blue >> 10, VGA_PEL_D);
699 break;
700 case 16:
701 if (regno >= 16)
702 return -EINVAL;
703
704 if (fb->var.green.length == 5)
705 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
706 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
707 else if (fb->var.green.length == 6)
708 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
709 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
710 else return -EINVAL;
711 break;
712 case 24:
713 case 32:
714 if (regno >= 16)
715 return -EINVAL;
716
717 ((u32*)fb->pseudo_palette)[regno] = ((transp & 0xFF00) << 16) | ((red & 0xFF00) << 8) |
718 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 return 0;
725 }
726
727
728 /* Set the display blanking state */
729
730 static int s3fb_blank(int blank_mode, struct fb_info *info)
731 {
732 switch (blank_mode) {
733 case FB_BLANK_UNBLANK:
734 pr_debug("fb%d: unblank\n", info->node);
735 svga_wcrt_mask(0x56, 0x00, 0x06);
736 svga_wseq_mask(0x01, 0x00, 0x20);
737 break;
738 case FB_BLANK_NORMAL:
739 pr_debug("fb%d: blank\n", info->node);
740 svga_wcrt_mask(0x56, 0x00, 0x06);
741 svga_wseq_mask(0x01, 0x20, 0x20);
742 break;
743 case FB_BLANK_HSYNC_SUSPEND:
744 pr_debug("fb%d: hsync\n", info->node);
745 svga_wcrt_mask(0x56, 0x02, 0x06);
746 svga_wseq_mask(0x01, 0x20, 0x20);
747 break;
748 case FB_BLANK_VSYNC_SUSPEND:
749 pr_debug("fb%d: vsync\n", info->node);
750 svga_wcrt_mask(0x56, 0x04, 0x06);
751 svga_wseq_mask(0x01, 0x20, 0x20);
752 break;
753 case FB_BLANK_POWERDOWN:
754 pr_debug("fb%d: sync down\n", info->node);
755 svga_wcrt_mask(0x56, 0x06, 0x06);
756 svga_wseq_mask(0x01, 0x20, 0x20);
757 break;
758 }
759
760 return 0;
761 }
762
763
764 /* Pan the display */
765
766 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
767
768 unsigned int offset;
769
770 /* Validate the offsets */
771 if ((var->xoffset + var->xres) > var->xres_virtual)
772 return -EINVAL;
773 if ((var->yoffset + var->yres) > var->yres_virtual)
774 return -EINVAL;
775
776 /* Calculate the offset */
777 if (var->bits_per_pixel == 0) {
778 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
779 offset = offset >> 2;
780 } else {
781 offset = (var->yoffset * info->fix.line_length) +
782 (var->xoffset * var->bits_per_pixel / 8);
783 offset = offset >> 2;
784 }
785
786 /* Set the offset */
787 svga_wcrt_multi(s3_start_address_regs, offset);
788
789 return 0;
790 }
791
792 /* ------------------------------------------------------------------------- */
793
794 /* Frame buffer operations */
795
796 static struct fb_ops s3fb_ops = {
797 .owner = THIS_MODULE,
798 .fb_open = s3fb_open,
799 .fb_release = s3fb_release,
800 .fb_check_var = s3fb_check_var,
801 .fb_set_par = s3fb_set_par,
802 .fb_setcolreg = s3fb_setcolreg,
803 .fb_blank = s3fb_blank,
804 .fb_pan_display = s3fb_pan_display,
805 .fb_fillrect = s3fb_fillrect,
806 .fb_copyarea = cfb_copyarea,
807 .fb_imageblit = s3fb_imageblit,
808 };
809
810 /* ------------------------------------------------------------------------- */
811
812 static int __devinit s3_identification(int chip)
813 {
814 if (chip == CHIP_XXX_TRIO) {
815 u8 cr30 = vga_rcrt(NULL, 0x30);
816 u8 cr2e = vga_rcrt(NULL, 0x2e);
817 u8 cr2f = vga_rcrt(NULL, 0x2f);
818
819 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
820 if (cr2e == 0x10)
821 return CHIP_732_TRIO32;
822 if (cr2e == 0x11) {
823 if (! (cr2f & 0x40))
824 return CHIP_764_TRIO64;
825 else
826 return CHIP_765_TRIO64VP;
827 }
828 }
829 }
830
831 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
832 u8 cr6f = vga_rcrt(NULL, 0x6f);
833
834 if (! (cr6f & 0x01))
835 return CHIP_775_TRIO64V2_DX;
836 else
837 return CHIP_785_TRIO64V2_GX;
838 }
839
840 if (chip == CHIP_XXX_VIRGE_DXGX) {
841 u8 cr6f = vga_rcrt(NULL, 0x6f);
842
843 if (! (cr6f & 0x01))
844 return CHIP_375_VIRGE_DX;
845 else
846 return CHIP_385_VIRGE_GX;
847 }
848
849 return CHIP_UNKNOWN;
850 }
851
852
853 /* PCI probe */
854
855 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
856 {
857 struct fb_info *info;
858 struct s3fb_info *par;
859 int rc;
860 u8 regval, cr38, cr39;
861
862 /* Ignore secondary VGA device because there is no VGA arbitration */
863 if (! svga_primary_device(dev)) {
864 dev_info(&(dev->dev), "ignoring secondary device\n");
865 return -ENODEV;
866 }
867
868 /* Allocate and fill driver data structure */
869 info = framebuffer_alloc(sizeof(struct s3fb_info), NULL);
870 if (!info) {
871 dev_err(&(dev->dev), "cannot allocate memory\n");
872 return -ENOMEM;
873 }
874
875 par = info->par;
876 mutex_init(&par->open_lock);
877
878 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
879 info->fbops = &s3fb_ops;
880
881 /* Prepare PCI device */
882 rc = pci_enable_device(dev);
883 if (rc < 0) {
884 dev_err(&(dev->dev), "cannot enable PCI device\n");
885 goto err_enable_device;
886 }
887
888 rc = pci_request_regions(dev, "s3fb");
889 if (rc < 0) {
890 dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
891 goto err_request_regions;
892 }
893
894
895 info->fix.smem_start = pci_resource_start(dev, 0);
896 info->fix.smem_len = pci_resource_len(dev, 0);
897
898 /* Map physical IO memory address into kernel space */
899 info->screen_base = pci_iomap(dev, 0, 0);
900 if (! info->screen_base) {
901 rc = -ENOMEM;
902 dev_err(&(dev->dev), "iomap for framebuffer failed\n");
903 goto err_iomap;
904 }
905
906 /* Unlock regs */
907 cr38 = vga_rcrt(NULL, 0x38);
908 cr39 = vga_rcrt(NULL, 0x39);
909 vga_wseq(NULL, 0x08, 0x06);
910 vga_wcrt(NULL, 0x38, 0x48);
911 vga_wcrt(NULL, 0x39, 0xA5);
912
913 /* Find how many physical memory there is on card */
914 /* 0x36 register is accessible even if other registers are locked */
915 regval = vga_rcrt(NULL, 0x36);
916 info->screen_size = s3_memsizes[regval >> 5] << 10;
917 info->fix.smem_len = info->screen_size;
918
919 par->chip = id->driver_data & CHIP_MASK;
920 par->rev = vga_rcrt(NULL, 0x2f);
921 if (par->chip & CHIP_UNDECIDED_FLAG)
922 par->chip = s3_identification(par->chip);
923
924 /* Find MCLK frequency */
925 regval = vga_rseq(NULL, 0x10);
926 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
927 par->mclk_freq = par->mclk_freq >> (regval >> 5);
928
929 /* Restore locks */
930 vga_wcrt(NULL, 0x38, cr38);
931 vga_wcrt(NULL, 0x39, cr39);
932
933 strcpy(info->fix.id, s3_names [par->chip]);
934 info->fix.mmio_start = 0;
935 info->fix.mmio_len = 0;
936 info->fix.type = FB_TYPE_PACKED_PIXELS;
937 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
938 info->fix.ypanstep = 0;
939 info->fix.accel = FB_ACCEL_NONE;
940 info->pseudo_palette = (void*) (par->pseudo_palette);
941
942 /* Prepare startup mode */
943 rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
944 if (! ((rc == 1) || (rc == 2))) {
945 rc = -EINVAL;
946 dev_err(&(dev->dev), "mode %s not found\n", mode);
947 goto err_find_mode;
948 }
949
950 rc = fb_alloc_cmap(&info->cmap, 256, 0);
951 if (rc < 0) {
952 dev_err(&(dev->dev), "cannot allocate colormap\n");
953 goto err_alloc_cmap;
954 }
955
956 rc = register_framebuffer(info);
957 if (rc < 0) {
958 dev_err(&(dev->dev), "cannot register framebuffer\n");
959 goto err_reg_fb;
960 }
961
962 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
963 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
964
965 if (par->chip == CHIP_UNKNOWN)
966 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
967 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
968 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
969
970 /* Record a reference to the driver data */
971 pci_set_drvdata(dev, info);
972
973 #ifdef CONFIG_MTRR
974 if (mtrr) {
975 par->mtrr_reg = -1;
976 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
977 }
978 #endif
979
980 return 0;
981
982 /* Error handling */
983 err_reg_fb:
984 fb_dealloc_cmap(&info->cmap);
985 err_alloc_cmap:
986 err_find_mode:
987 pci_iounmap(dev, info->screen_base);
988 err_iomap:
989 pci_release_regions(dev);
990 err_request_regions:
991 /* pci_disable_device(dev); */
992 err_enable_device:
993 framebuffer_release(info);
994 return rc;
995 }
996
997
998 /* PCI remove */
999
1000 static void __devexit s3_pci_remove(struct pci_dev *dev)
1001 {
1002 struct fb_info *info = pci_get_drvdata(dev);
1003
1004 if (info) {
1005
1006 #ifdef CONFIG_MTRR
1007 struct s3fb_info *par = info->par;
1008
1009 if (par->mtrr_reg >= 0) {
1010 mtrr_del(par->mtrr_reg, 0, 0);
1011 par->mtrr_reg = -1;
1012 }
1013 #endif
1014
1015 unregister_framebuffer(info);
1016 fb_dealloc_cmap(&info->cmap);
1017
1018 pci_iounmap(dev, info->screen_base);
1019 pci_release_regions(dev);
1020 /* pci_disable_device(dev); */
1021
1022 pci_set_drvdata(dev, NULL);
1023 framebuffer_release(info);
1024 }
1025 }
1026
1027 /* PCI suspend */
1028
1029 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1030 {
1031 struct fb_info *info = pci_get_drvdata(dev);
1032 struct s3fb_info *par = info->par;
1033
1034 dev_info(&(dev->dev), "suspend\n");
1035
1036 acquire_console_sem();
1037 mutex_lock(&(par->open_lock));
1038
1039 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1040 mutex_unlock(&(par->open_lock));
1041 release_console_sem();
1042 return 0;
1043 }
1044
1045 fb_set_suspend(info, 1);
1046
1047 pci_save_state(dev);
1048 pci_disable_device(dev);
1049 pci_set_power_state(dev, pci_choose_state(dev, state));
1050
1051 mutex_unlock(&(par->open_lock));
1052 release_console_sem();
1053
1054 return 0;
1055 }
1056
1057
1058 /* PCI resume */
1059
1060 static int s3_pci_resume(struct pci_dev* dev)
1061 {
1062 struct fb_info *info = pci_get_drvdata(dev);
1063 struct s3fb_info *par = info->par;
1064
1065 dev_info(&(dev->dev), "resume\n");
1066
1067 acquire_console_sem();
1068 mutex_lock(&(par->open_lock));
1069
1070 if (par->ref_count == 0) {
1071 mutex_unlock(&(par->open_lock));
1072 release_console_sem();
1073 return 0;
1074 }
1075
1076 pci_set_power_state(dev, PCI_D0);
1077 pci_restore_state(dev);
1078 pci_enable_device(dev);
1079 pci_set_master(dev);
1080
1081 s3fb_set_par(info);
1082 fb_set_suspend(info, 0);
1083
1084 mutex_unlock(&(par->open_lock));
1085 release_console_sem();
1086
1087 return 0;
1088 }
1089
1090
1091 /* List of boards that we are trying to support */
1092
1093 static struct pci_device_id s3_devices[] __devinitdata = {
1094 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1095 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1096 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1097 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1098 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1099 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1100
1101 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1102 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1103 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1104 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1105 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1106 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1107
1108 {0, 0, 0, 0, 0, 0, 0}
1109 };
1110
1111
1112 MODULE_DEVICE_TABLE(pci, s3_devices);
1113
1114 static struct pci_driver s3fb_pci_driver = {
1115 .name = "s3fb",
1116 .id_table = s3_devices,
1117 .probe = s3_pci_probe,
1118 .remove = __devexit_p(s3_pci_remove),
1119 .suspend = s3_pci_suspend,
1120 .resume = s3_pci_resume,
1121 };
1122
1123 /* Parse user speficied options */
1124
1125 #ifndef MODULE
1126 static int __init s3fb_setup(char *options)
1127 {
1128 char *opt;
1129
1130 if (!options || !*options)
1131 return 0;
1132
1133 while ((opt = strsep(&options, ",")) != NULL) {
1134
1135 if (!*opt)
1136 continue;
1137 #ifdef CONFIG_MTRR
1138 else if (!strncmp(opt, "mtrr:", 5))
1139 mtrr = simple_strtoul(opt + 5, NULL, 0);
1140 #endif
1141 else if (!strncmp(opt, "fasttext:", 9))
1142 fasttext = simple_strtoul(opt + 9, NULL, 0);
1143 else
1144 mode = opt;
1145 }
1146
1147 return 0;
1148 }
1149 #endif
1150
1151 /* Cleanup */
1152
1153 static void __exit s3fb_cleanup(void)
1154 {
1155 pr_debug("s3fb: cleaning up\n");
1156 pci_unregister_driver(&s3fb_pci_driver);
1157 }
1158
1159 /* Driver Initialisation */
1160
1161 static int __init s3fb_init(void)
1162 {
1163
1164 #ifndef MODULE
1165 char *option = NULL;
1166
1167 if (fb_get_options("s3fb", &option))
1168 return -ENODEV;
1169 s3fb_setup(option);
1170 #endif
1171
1172 pr_debug("s3fb: initializing\n");
1173 return pci_register_driver(&s3fb_pci_driver);
1174 }
1175
1176 /* ------------------------------------------------------------------------- */
1177
1178 /* Modularization */
1179
1180 module_init(s3fb_init);
1181 module_exit(s3fb_cleanup);
linux v2.6.22.y-op