arch/arm/mach-sa1100/irq.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/irq.c
   3  *
   4  * Copyright (C) 1999-2001 Nicolas Pitre
   5  *
   6  * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/ioport.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/sysdev.h>
  19
  20 #include <asm/hardware.h>
  21 #include <asm/mach/irq.h>
  22
  23 #include "generic.h"
  24
  25
  26 /*
  27  * SA1100 GPIO edge detection for IRQs:
  28  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
  29  * Use this instead of directly setting GRER/GFER.
  30  */
  31 static int GPIO_IRQ_rising_edge;
  32 static int GPIO_IRQ_falling_edge;
  33 static int GPIO_IRQ_mask = (1 << 11) - 1;
  34
  35 /*
  36  * To get the GPIO number from an IRQ number
  37  */
  38 #define GPIO_11_27_IRQ(i)       ((i) - 21)
  39 #define GPIO11_27_MASK(irq)     (1 << GPIO_11_27_IRQ(irq))
  40
  41 static int sa1100_gpio_type(unsigned int irq, unsigned int type)
  42 {
  43         unsigned int mask;
  44
  45         if (irq <= 10)
  46                 mask = 1 << irq;
  47         else
  48                 mask = GPIO11_27_MASK(irq);
  49
  50         if (type == IRQT_PROBE) {
  51                 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
  52                         return 0;
  53                 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
  54         }
  55
  56         if (type & __IRQT_RISEDGE) {
  57                 GPIO_IRQ_rising_edge |= mask;
  58         } else
  59                 GPIO_IRQ_rising_edge &= ~mask;
  60         if (type & __IRQT_FALEDGE) {
  61                 GPIO_IRQ_falling_edge |= mask;
  62         } else
  63                 GPIO_IRQ_falling_edge &= ~mask;
  64
  65         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
  66         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
  67
  68         return 0;
  69 }
  70
  71 /*
  72  * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
  73  */
  74 static void sa1100_low_gpio_ack(unsigned int irq)
  75 {
  76         GEDR = (1 << irq);
  77 }
  78
  79 static void sa1100_low_gpio_mask(unsigned int irq)
  80 {
  81         ICMR &= ~(1 << irq);
  82 }
  83
  84 static void sa1100_low_gpio_unmask(unsigned int irq)
  85 {
  86         ICMR |= 1 << irq;
  87 }
  88
  89 static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
  90 {
  91         if (on)
  92                 PWER |= 1 << irq;
  93         else
  94                 PWER &= ~(1 << irq);
  95         return 0;
  96 }
  97
  98 static struct irq_chip sa1100_low_gpio_chip = {
  99         .name           = "GPIO-l",
 100         .ack            = sa1100_low_gpio_ack,
 101         .mask           = sa1100_low_gpio_mask,
 102         .unmask         = sa1100_low_gpio_unmask,
 103         .set_type       = sa1100_gpio_type,
 104         .set_wake       = sa1100_low_gpio_wake,
 105 };
 106
 107 /*
 108  * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 109  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 110  * and call the handler.
 111  */
 112 static void
 113 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
 114 {
 115         unsigned int mask;
 116
 117         mask = GEDR & 0xfffff800;
 118         do {
 119                 /*
 120                  * clear down all currently active IRQ sources.
 121                  * We will be processing them all.
 122                  */
 123                 GEDR = mask;
 124
 125                 irq = IRQ_GPIO11;
 126                 desc = irq_desc + irq;
 127                 mask >>= 11;
 128                 do {
 129                         if (mask & 1)
 130                                 desc_handle_irq(irq, desc);
 131                         mask >>= 1;
 132                         irq++;
 133                         desc++;
 134                 } while (mask);
 135
 136                 mask = GEDR & 0xfffff800;
 137         } while (mask);
 138 }
 139
 140 /*
 141  * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 142  * In addition, the IRQs are all collected up into one bit in the
 143  * interrupt controller registers.
 144  */
 145 static void sa1100_high_gpio_ack(unsigned int irq)
 146 {
 147         unsigned int mask = GPIO11_27_MASK(irq);
 148
 149         GEDR = mask;
 150 }
 151
 152 static void sa1100_high_gpio_mask(unsigned int irq)
 153 {
 154         unsigned int mask = GPIO11_27_MASK(irq);
 155
 156         GPIO_IRQ_mask &= ~mask;
 157
 158         GRER &= ~mask;
 159         GFER &= ~mask;
 160 }
 161
 162 static void sa1100_high_gpio_unmask(unsigned int irq)
 163 {
 164         unsigned int mask = GPIO11_27_MASK(irq);
 165
 166         GPIO_IRQ_mask |= mask;
 167
 168         GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 169         GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 170 }
 171
 172 static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
 173 {
 174         if (on)
 175                 PWER |= GPIO11_27_MASK(irq);
 176         else
 177                 PWER &= ~GPIO11_27_MASK(irq);
 178         return 0;
 179 }
 180
 181 static struct irq_chip sa1100_high_gpio_chip = {
 182         .name           = "GPIO-h",
 183         .ack            = sa1100_high_gpio_ack,
 184         .mask           = sa1100_high_gpio_mask,
 185         .unmask         = sa1100_high_gpio_unmask,
 186         .set_type       = sa1100_gpio_type,
 187         .set_wake       = sa1100_high_gpio_wake,
 188 };
 189
 190 /*
 191  * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 192  * this is for internal IRQs i.e. from 11 to 31.
 193  */
 194 static void sa1100_mask_irq(unsigned int irq)
 195 {
 196         ICMR &= ~(1 << irq);
 197 }
 198
 199 static void sa1100_unmask_irq(unsigned int irq)
 200 {
 201         ICMR |= (1 << irq);
 202 }
 203
 204 /*
 205  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 206  */
 207 static int sa1100_set_wake(unsigned int irq, unsigned int on)
 208 {
 209         if (irq == IRQ_RTCAlrm) {
 210                 if (on)
 211                         PWER |= PWER_RTC;
 212                 else
 213                         PWER &= ~PWER_RTC;
 214                 return 0;
 215         }
 216         return -EINVAL;
 217 }
 218
 219 static struct irq_chip sa1100_normal_chip = {
 220         .name           = "SC",
 221         .ack            = sa1100_mask_irq,
 222         .mask           = sa1100_mask_irq,
 223         .unmask         = sa1100_unmask_irq,
 224         .set_wake       = sa1100_set_wake,
 225 };
 226
 227 static struct resource irq_resource = {
 228         .name   = "irqs",
 229         .start  = 0x90050000,
 230         .end    = 0x9005ffff,
 231 };
 232
 233 static struct sa1100irq_state {
 234         unsigned int    saved;
 235         unsigned int    icmr;
 236         unsigned int    iclr;
 237         unsigned int    iccr;
 238 } sa1100irq_state;
 239
 240 static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
 241 {
 242         struct sa1100irq_state *st = &sa1100irq_state;
 243
 244         st->saved = 1;
 245         st->icmr = ICMR;
 246         st->iclr = ICLR;
 247         st->iccr = ICCR;
 248
 249         /*
 250          * Disable all GPIO-based interrupts.
 251          */
 252         ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
 253                   IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
 254                   IC_GPIO1|IC_GPIO0);
 255
 256         /*
 257          * Set the appropriate edges for wakeup.
 258          */
 259         GRER = PWER & GPIO_IRQ_rising_edge;
 260         GFER = PWER & GPIO_IRQ_falling_edge;
 261
 262         /*
 263          * Clear any pending GPIO interrupts.
 264          */
 265         GEDR = GEDR;
 266
 267         return 0;
 268 }
 269
 270 static int sa1100irq_resume(struct sys_device *dev)
 271 {
 272         struct sa1100irq_state *st = &sa1100irq_state;
 273
 274         if (st->saved) {
 275                 ICCR = st->iccr;
 276                 ICLR = st->iclr;
 277
 278                 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
 279                 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
 280
 281                 ICMR = st->icmr;
 282         }
 283         return 0;
 284 }
 285
 286 static struct sysdev_class sa1100irq_sysclass = {
 287         set_kset_name("sa11x0-irq"),
 288         .suspend        = sa1100irq_suspend,
 289         .resume         = sa1100irq_resume,
 290 };
 291
 292 static struct sys_device sa1100irq_device = {
 293         .id             = 0,
 294         .cls            = &sa1100irq_sysclass,
 295 };
 296
 297 static int __init sa1100irq_init_devicefs(void)
 298 {
 299         sysdev_class_register(&sa1100irq_sysclass);
 300         return sysdev_register(&sa1100irq_device);
 301 }
 302
 303 device_initcall(sa1100irq_init_devicefs);
 304
 305 void __init sa1100_init_irq(void)
 306 {
 307         unsigned int irq;
 308
 309         request_resource(&iomem_resource, &irq_resource);
 310
 311         /* disable all IRQs */
 312         ICMR = 0;
 313
 314         /* all IRQs are IRQ, not FIQ */
 315         ICLR = 0;
 316
 317         /* clear all GPIO edge detects */
 318         GFER = 0;
 319         GRER = 0;
 320         GEDR = -1;
 321
 322         /*
 323          * Whatever the doc says, this has to be set for the wait-on-irq
 324          * instruction to work... on a SA1100 rev 9 at least.
 325          */
 326         ICCR = 1;
 327
 328         for (irq = 0; irq <= 10; irq++) {
 329                 set_irq_chip(irq, &sa1100_low_gpio_chip);
 330                 set_irq_handler(irq, handle_edge_irq);
 331                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 332         }
 333
 334         for (irq = 12; irq <= 31; irq++) {
 335                 set_irq_chip(irq, &sa1100_normal_chip);
 336                 set_irq_handler(irq, handle_level_irq);
 337                 set_irq_flags(irq, IRQF_VALID);
 338         }
 339
 340         for (irq = 32; irq <= 48; irq++) {
 341                 set_irq_chip(irq, &sa1100_high_gpio_chip);
 342                 set_irq_handler(irq, handle_edge_irq);
 343                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 344         }
 345
 346         /*
 347          * Install handler for GPIO 11-27 edge detect interrupts
 348          */
 349         set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
 350         set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 351 }