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[PATCH] genirq: x86_64 irq: Kill gsi_irq_sharing
[linux-2.6.22.y-op.git] / arch / x86_64 / kernel / io_apic.c
blobe076a8fa3ac330ce493869e2f8f683663d02dc11
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #ifdef CONFIG_ACPI
34 #include <acpi/acpi_bus.h>
35 #endif
36
37 #include <asm/io.h>
38 #include <asm/smp.h>
39 #include <asm/desc.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
42 #include <asm/acpi.h>
43 #include <asm/dma.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46
47 static int assign_irq_vector(int irq, cpumask_t mask);
48
49 #define __apicdebuginit __init
50
51 int sis_apic_bug; /* not actually supported, dummy for compile */
52
53 static int no_timer_check;
54
55 static int disable_timer_pin_1 __initdata;
56
57 int timer_over_8254 __initdata = 0;
58
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61
62 static DEFINE_SPINLOCK(ioapic_lock);
63 static DEFINE_SPINLOCK(vector_lock);
64
65 /*
66 * # of IRQ routing registers
67 */
68 int nr_ioapic_registers[MAX_IO_APICS];
69
70 /*
71 * Rough estimation of how many shared IRQs there are, can
72 * be changed anytime.
73 */
74 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
75 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
76
77 /*
78 * This is performance-critical, we want to do it O(1)
79 *
80 * the indexing order of this array favors 1:1 mappings
81 * between pins and IRQs.
82 */
83
84 static struct irq_pin_list {
85 short apic, pin, next;
86 } irq_2_pin[PIN_MAP_SIZE];
87
88 #define __DO_ACTION(R, ACTION, FINAL) \
89 \
90 { \
91 int pin; \
92 struct irq_pin_list *entry = irq_2_pin + irq; \
93 \
94 BUG_ON(irq >= NR_IRQS); \
95 for (;;) { \
96 unsigned int reg; \
97 pin = entry->pin; \
98 if (pin == -1) \
99 break; \
100 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
101 reg ACTION; \
102 io_apic_modify(entry->apic, reg); \
103 if (!entry->next) \
104 break; \
105 entry = irq_2_pin + entry->next; \
106 } \
107 FINAL; \
108 }
109
110 union entry_union {
111 struct { u32 w1, w2; };
112 struct IO_APIC_route_entry entry;
113 };
114
115 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
116 {
117 union entry_union eu;
118 unsigned long flags;
119 spin_lock_irqsave(&ioapic_lock, flags);
120 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
121 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
122 spin_unlock_irqrestore(&ioapic_lock, flags);
123 return eu.entry;
124 }
125
126 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
127 {
128 unsigned long flags;
129 union entry_union eu;
130 eu.entry = e;
131 spin_lock_irqsave(&ioapic_lock, flags);
132 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
133 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
134 spin_unlock_irqrestore(&ioapic_lock, flags);
135 }
136
137 #ifdef CONFIG_SMP
138 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
139 {
140 int apic, pin;
141 struct irq_pin_list *entry = irq_2_pin + irq;
142
143 BUG_ON(irq >= NR_IRQS);
144 for (;;) {
145 unsigned int reg;
146 apic = entry->apic;
147 pin = entry->pin;
148 if (pin == -1)
149 break;
150 io_apic_write(apic, 0x11 + pin*2, dest);
151 reg = io_apic_read(apic, 0x10 + pin*2);
152 reg &= ~0x000000ff;
153 reg |= vector;
154 io_apic_modify(apic, reg);
155 if (!entry->next)
156 break;
157 entry = irq_2_pin + entry->next;
158 }
159 }
160
161 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
162 {
163 unsigned long flags;
164 unsigned int dest;
165 cpumask_t tmp;
166 int vector;
167
168 cpus_and(tmp, mask, cpu_online_map);
169 if (cpus_empty(tmp))
170 tmp = TARGET_CPUS;
171
172 cpus_and(mask, tmp, CPU_MASK_ALL);
173
174 vector = assign_irq_vector(irq, mask);
175 if (vector < 0)
176 return;
177
178 cpus_clear(tmp);
179 cpu_set(vector >> 8, tmp);
180 dest = cpu_mask_to_apicid(tmp);
181
182 /*
183 * Only the high 8 bits are valid.
184 */
185 dest = SET_APIC_LOGICAL_ID(dest);
186
187 spin_lock_irqsave(&ioapic_lock, flags);
188 __target_IO_APIC_irq(irq, dest, vector & 0xff);
189 set_native_irq_info(irq, mask);
190 spin_unlock_irqrestore(&ioapic_lock, flags);
191 }
192 #endif
193
194 /*
195 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
196 * shared ISA-space IRQs, so we have to support them. We are super
197 * fast in the common case, and fast for shared ISA-space IRQs.
198 */
199 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
200 {
201 static int first_free_entry = NR_IRQS;
202 struct irq_pin_list *entry = irq_2_pin + irq;
203
204 BUG_ON(irq >= NR_IRQS);
205 while (entry->next)
206 entry = irq_2_pin + entry->next;
207
208 if (entry->pin != -1) {
209 entry->next = first_free_entry;
210 entry = irq_2_pin + entry->next;
211 if (++first_free_entry >= PIN_MAP_SIZE)
212 panic("io_apic.c: ran out of irq_2_pin entries!");
213 }
214 entry->apic = apic;
215 entry->pin = pin;
216 }
217
218
219 #define DO_ACTION(name,R,ACTION, FINAL) \
220 \
221 static void name##_IO_APIC_irq (unsigned int irq) \
222 __DO_ACTION(R, ACTION, FINAL)
223
224 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
225 /* mask = 1 */
226 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
227 /* mask = 0 */
228
229 static void mask_IO_APIC_irq (unsigned int irq)
230 {
231 unsigned long flags;
232
233 spin_lock_irqsave(&ioapic_lock, flags);
234 __mask_IO_APIC_irq(irq);
235 spin_unlock_irqrestore(&ioapic_lock, flags);
236 }
237
238 static void unmask_IO_APIC_irq (unsigned int irq)
239 {
240 unsigned long flags;
241
242 spin_lock_irqsave(&ioapic_lock, flags);
243 __unmask_IO_APIC_irq(irq);
244 spin_unlock_irqrestore(&ioapic_lock, flags);
245 }
246
247 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
248 {
249 struct IO_APIC_route_entry entry;
250
251 /* Check delivery_mode to be sure we're not clearing an SMI pin */
252 entry = ioapic_read_entry(apic, pin);
253 if (entry.delivery_mode == dest_SMI)
254 return;
255 /*
256 * Disable it in the IO-APIC irq-routing table:
257 */
258 memset(&entry, 0, sizeof(entry));
259 entry.mask = 1;
260 ioapic_write_entry(apic, pin, entry);
261 }
262
263 static void clear_IO_APIC (void)
264 {
265 int apic, pin;
266
267 for (apic = 0; apic < nr_ioapics; apic++)
268 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
269 clear_IO_APIC_pin(apic, pin);
270 }
271
272 int skip_ioapic_setup;
273 int ioapic_force;
274
275 /* dummy parsing: see setup.c */
276
277 static int __init disable_ioapic_setup(char *str)
278 {
279 skip_ioapic_setup = 1;
280 return 0;
281 }
282 early_param("noapic", disable_ioapic_setup);
283
284 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
285 static int __init disable_timer_pin_setup(char *arg)
286 {
287 disable_timer_pin_1 = 1;
288 return 1;
289 }
290 __setup("disable_timer_pin_1", disable_timer_pin_setup);
291
292 static int __init setup_disable_8254_timer(char *s)
293 {
294 timer_over_8254 = -1;
295 return 1;
296 }
297 static int __init setup_enable_8254_timer(char *s)
298 {
299 timer_over_8254 = 2;
300 return 1;
301 }
302
303 __setup("disable_8254_timer", setup_disable_8254_timer);
304 __setup("enable_8254_timer", setup_enable_8254_timer);
305
306
307 /*
308 * Find the IRQ entry number of a certain pin.
309 */
310 static int find_irq_entry(int apic, int pin, int type)
311 {
312 int i;
313
314 for (i = 0; i < mp_irq_entries; i++)
315 if (mp_irqs[i].mpc_irqtype == type &&
316 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
317 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
318 mp_irqs[i].mpc_dstirq == pin)
319 return i;
320
321 return -1;
322 }
323
324 /*
325 * Find the pin to which IRQ[irq] (ISA) is connected
326 */
327 static int __init find_isa_irq_pin(int irq, int type)
328 {
329 int i;
330
331 for (i = 0; i < mp_irq_entries; i++) {
332 int lbus = mp_irqs[i].mpc_srcbus;
333
334 if (test_bit(lbus, mp_bus_not_pci) &&
335 (mp_irqs[i].mpc_irqtype == type) &&
336 (mp_irqs[i].mpc_srcbusirq == irq))
337
338 return mp_irqs[i].mpc_dstirq;
339 }
340 return -1;
341 }
342
343 static int __init find_isa_irq_apic(int irq, int type)
344 {
345 int i;
346
347 for (i = 0; i < mp_irq_entries; i++) {
348 int lbus = mp_irqs[i].mpc_srcbus;
349
350 if (test_bit(lbus, mp_bus_not_pci) &&
351 (mp_irqs[i].mpc_irqtype == type) &&
352 (mp_irqs[i].mpc_srcbusirq == irq))
353 break;
354 }
355 if (i < mp_irq_entries) {
356 int apic;
357 for(apic = 0; apic < nr_ioapics; apic++) {
358 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
359 return apic;
360 }
361 }
362
363 return -1;
364 }
365
366 /*
367 * Find a specific PCI IRQ entry.
368 * Not an __init, possibly needed by modules
369 */
370 static int pin_2_irq(int idx, int apic, int pin);
371
372 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
373 {
374 int apic, i, best_guess = -1;
375
376 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
377 bus, slot, pin);
378 if (mp_bus_id_to_pci_bus[bus] == -1) {
379 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
380 return -1;
381 }
382 for (i = 0; i < mp_irq_entries; i++) {
383 int lbus = mp_irqs[i].mpc_srcbus;
384
385 for (apic = 0; apic < nr_ioapics; apic++)
386 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
387 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
388 break;
389
390 if (!test_bit(lbus, mp_bus_not_pci) &&
391 !mp_irqs[i].mpc_irqtype &&
392 (bus == lbus) &&
393 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
394 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
395
396 if (!(apic || IO_APIC_IRQ(irq)))
397 continue;
398
399 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
400 return irq;
401 /*
402 * Use the first all-but-pin matching entry as a
403 * best-guess fuzzy result for broken mptables.
404 */
405 if (best_guess < 0)
406 best_guess = irq;
407 }
408 }
409 BUG_ON(best_guess >= NR_IRQS);
410 return best_guess;
411 }
412
413 /* ISA interrupts are always polarity zero edge triggered,
414 * when listed as conforming in the MP table. */
415
416 #define default_ISA_trigger(idx) (0)
417 #define default_ISA_polarity(idx) (0)
418
419 /* PCI interrupts are always polarity one level triggered,
420 * when listed as conforming in the MP table. */
421
422 #define default_PCI_trigger(idx) (1)
423 #define default_PCI_polarity(idx) (1)
424
425 static int __init MPBIOS_polarity(int idx)
426 {
427 int bus = mp_irqs[idx].mpc_srcbus;
428 int polarity;
429
430 /*
431 * Determine IRQ line polarity (high active or low active):
432 */
433 switch (mp_irqs[idx].mpc_irqflag & 3)
434 {
435 case 0: /* conforms, ie. bus-type dependent polarity */
436 if (test_bit(bus, mp_bus_not_pci))
437 polarity = default_ISA_polarity(idx);
438 else
439 polarity = default_PCI_polarity(idx);
440 break;
441 case 1: /* high active */
442 {
443 polarity = 0;
444 break;
445 }
446 case 2: /* reserved */
447 {
448 printk(KERN_WARNING "broken BIOS!!\n");
449 polarity = 1;
450 break;
451 }
452 case 3: /* low active */
453 {
454 polarity = 1;
455 break;
456 }
457 default: /* invalid */
458 {
459 printk(KERN_WARNING "broken BIOS!!\n");
460 polarity = 1;
461 break;
462 }
463 }
464 return polarity;
465 }
466
467 static int MPBIOS_trigger(int idx)
468 {
469 int bus = mp_irqs[idx].mpc_srcbus;
470 int trigger;
471
472 /*
473 * Determine IRQ trigger mode (edge or level sensitive):
474 */
475 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
476 {
477 case 0: /* conforms, ie. bus-type dependent */
478 if (test_bit(bus, mp_bus_not_pci))
479 trigger = default_ISA_trigger(idx);
480 else
481 trigger = default_PCI_trigger(idx);
482 break;
483 case 1: /* edge */
484 {
485 trigger = 0;
486 break;
487 }
488 case 2: /* reserved */
489 {
490 printk(KERN_WARNING "broken BIOS!!\n");
491 trigger = 1;
492 break;
493 }
494 case 3: /* level */
495 {
496 trigger = 1;
497 break;
498 }
499 default: /* invalid */
500 {
501 printk(KERN_WARNING "broken BIOS!!\n");
502 trigger = 0;
503 break;
504 }
505 }
506 return trigger;
507 }
508
509 static inline int irq_polarity(int idx)
510 {
511 return MPBIOS_polarity(idx);
512 }
513
514 static inline int irq_trigger(int idx)
515 {
516 return MPBIOS_trigger(idx);
517 }
518
519 static int pin_2_irq(int idx, int apic, int pin)
520 {
521 int irq, i;
522 int bus = mp_irqs[idx].mpc_srcbus;
523
524 /*
525 * Debugging check, we are in big trouble if this message pops up!
526 */
527 if (mp_irqs[idx].mpc_dstirq != pin)
528 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
529
530 if (test_bit(bus, mp_bus_not_pci)) {
531 irq = mp_irqs[idx].mpc_srcbusirq;
532 } else {
533 /*
534 * PCI IRQs are mapped in order
535 */
536 i = irq = 0;
537 while (i < apic)
538 irq += nr_ioapic_registers[i++];
539 irq += pin;
540 }
541 BUG_ON(irq >= NR_IRQS);
542 return irq;
543 }
544
545 static inline int IO_APIC_irq_trigger(int irq)
546 {
547 int apic, idx, pin;
548
549 for (apic = 0; apic < nr_ioapics; apic++) {
550 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
551 idx = find_irq_entry(apic,pin,mp_INT);
552 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
553 return irq_trigger(idx);
554 }
555 }
556 /*
557 * nonexistent IRQs are edge default
558 */
559 return 0;
560 }
561
562 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
563 unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 };
564
565 static int __assign_irq_vector(int irq, cpumask_t mask)
566 {
567 /*
568 * NOTE! The local APIC isn't very good at handling
569 * multiple interrupts at the same interrupt level.
570 * As the interrupt level is determined by taking the
571 * vector number and shifting that right by 4, we
572 * want to spread these out a bit so that they don't
573 * all fall in the same interrupt level.
574 *
575 * Also, we've got to be careful not to trash gate
576 * 0x80, because int 0x80 is hm, kind of importantish. ;)
577 */
578 static struct {
579 int vector;
580 int offset;
581 } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
582 int old_vector = -1;
583 int cpu;
584
585 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
586
587 if (IO_APIC_VECTOR(irq) > 0)
588 old_vector = IO_APIC_VECTOR(irq);
589 if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) {
590 return old_vector;
591 }
592
593 for_each_cpu_mask(cpu, mask) {
594 int vector, offset;
595 vector = pos[cpu].vector;
596 offset = pos[cpu].offset;
597 next:
598 vector += 8;
599 if (vector >= FIRST_SYSTEM_VECTOR) {
600 /* If we run out of vectors on large boxen, must share them. */
601 offset = (offset + 1) % 8;
602 vector = FIRST_DEVICE_VECTOR + offset;
603 }
604 if (unlikely(pos[cpu].vector == vector))
605 continue;
606 if (vector == IA32_SYSCALL_VECTOR)
607 goto next;
608 if (per_cpu(vector_irq, cpu)[vector] != -1)
609 goto next;
610 /* Found one! */
611 pos[cpu].vector = vector;
612 pos[cpu].offset = offset;
613 if (old_vector >= 0) {
614 int old_cpu = old_vector >> 8;
615 old_vector &= 0xff;
616 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
617 }
618 per_cpu(vector_irq, cpu)[vector] = irq;
619 vector |= cpu << 8;
620 IO_APIC_VECTOR(irq) = vector;
621 return vector;
622 }
623 return -ENOSPC;
624 }
625
626 static int assign_irq_vector(int irq, cpumask_t mask)
627 {
628 int vector;
629 unsigned long flags;
630
631 spin_lock_irqsave(&vector_lock, flags);
632 vector = __assign_irq_vector(irq, mask);
633 spin_unlock_irqrestore(&vector_lock, flags);
634 return vector;
635 }
636
637 extern void (*interrupt[NR_IRQS])(void);
638
639 static struct irq_chip ioapic_chip;
640
641 #define IOAPIC_AUTO -1
642 #define IOAPIC_EDGE 0
643 #define IOAPIC_LEVEL 1
644
645 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
646 {
647 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
648 trigger == IOAPIC_LEVEL)
649 set_irq_chip_and_handler(irq, &ioapic_chip,
650 handle_fasteoi_irq);
651 else
652 set_irq_chip_and_handler(irq, &ioapic_chip,
653 handle_edge_irq);
654 }
655
656 static void __init setup_IO_APIC_irqs(void)
657 {
658 struct IO_APIC_route_entry entry;
659 int apic, pin, idx, irq, first_notcon = 1, vector;
660 unsigned long flags;
661
662 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
663
664 for (apic = 0; apic < nr_ioapics; apic++) {
665 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
666
667 /*
668 * add it to the IO-APIC irq-routing table:
669 */
670 memset(&entry,0,sizeof(entry));
671
672 entry.delivery_mode = INT_DELIVERY_MODE;
673 entry.dest_mode = INT_DEST_MODE;
674 entry.mask = 0; /* enable IRQ */
675 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
676
677 idx = find_irq_entry(apic,pin,mp_INT);
678 if (idx == -1) {
679 if (first_notcon) {
680 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
681 first_notcon = 0;
682 } else
683 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
684 continue;
685 }
686
687 entry.trigger = irq_trigger(idx);
688 entry.polarity = irq_polarity(idx);
689
690 if (irq_trigger(idx)) {
691 entry.trigger = 1;
692 entry.mask = 1;
693 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
694 }
695
696 irq = pin_2_irq(idx, apic, pin);
697 add_pin_to_irq(irq, apic, pin);
698
699 if (!apic && !IO_APIC_IRQ(irq))
700 continue;
701
702 if (IO_APIC_IRQ(irq)) {
703 cpumask_t mask;
704 vector = assign_irq_vector(irq, TARGET_CPUS);
705 if (vector < 0)
706 continue;
707
708 cpus_clear(mask);
709 cpu_set(vector >> 8, mask);
710 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
711 entry.vector = vector & 0xff;
712
713 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
714 if (!apic && (irq < 16))
715 disable_8259A_irq(irq);
716 }
717 ioapic_write_entry(apic, pin, entry);
718
719 spin_lock_irqsave(&ioapic_lock, flags);
720 set_native_irq_info(irq, TARGET_CPUS);
721 spin_unlock_irqrestore(&ioapic_lock, flags);
722 }
723 }
724
725 if (!first_notcon)
726 apic_printk(APIC_VERBOSE," not connected.\n");
727 }
728
729 /*
730 * Set up the 8259A-master output pin as broadcast to all
731 * CPUs.
732 */
733 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
734 {
735 struct IO_APIC_route_entry entry;
736 unsigned long flags;
737
738 memset(&entry,0,sizeof(entry));
739
740 disable_8259A_irq(0);
741
742 /* mask LVT0 */
743 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
744
745 /*
746 * We use logical delivery to get the timer IRQ
747 * to the first CPU.
748 */
749 entry.dest_mode = INT_DEST_MODE;
750 entry.mask = 0; /* unmask IRQ now */
751 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
752 entry.delivery_mode = INT_DELIVERY_MODE;
753 entry.polarity = 0;
754 entry.trigger = 0;
755 entry.vector = vector;
756
757 /*
758 * The timer IRQ doesn't have to know that behind the
759 * scene we have a 8259A-master in AEOI mode ...
760 */
761 set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
762
763 /*
764 * Add it to the IO-APIC irq-routing table:
765 */
766 spin_lock_irqsave(&ioapic_lock, flags);
767 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
768 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
769 spin_unlock_irqrestore(&ioapic_lock, flags);
770
771 enable_8259A_irq(0);
772 }
773
774 void __init UNEXPECTED_IO_APIC(void)
775 {
776 }
777
778 void __apicdebuginit print_IO_APIC(void)
779 {
780 int apic, i;
781 union IO_APIC_reg_00 reg_00;
782 union IO_APIC_reg_01 reg_01;
783 union IO_APIC_reg_02 reg_02;
784 unsigned long flags;
785
786 if (apic_verbosity == APIC_QUIET)
787 return;
788
789 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
790 for (i = 0; i < nr_ioapics; i++)
791 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
792 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
793
794 /*
795 * We are a bit conservative about what we expect. We have to
796 * know about every hardware change ASAP.
797 */
798 printk(KERN_INFO "testing the IO APIC.......................\n");
799
800 for (apic = 0; apic < nr_ioapics; apic++) {
801
802 spin_lock_irqsave(&ioapic_lock, flags);
803 reg_00.raw = io_apic_read(apic, 0);
804 reg_01.raw = io_apic_read(apic, 1);
805 if (reg_01.bits.version >= 0x10)
806 reg_02.raw = io_apic_read(apic, 2);
807 spin_unlock_irqrestore(&ioapic_lock, flags);
808
809 printk("\n");
810 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
811 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
812 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
813 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
814 UNEXPECTED_IO_APIC();
815
816 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
817 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
818 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
819 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
820 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
821 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
822 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
823 (reg_01.bits.entries != 0x2E) &&
824 (reg_01.bits.entries != 0x3F) &&
825 (reg_01.bits.entries != 0x03)
826 )
827 UNEXPECTED_IO_APIC();
828
829 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
830 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
831 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
832 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
833 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
834 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
835 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
836 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
837 )
838 UNEXPECTED_IO_APIC();
839 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
840 UNEXPECTED_IO_APIC();
841
842 if (reg_01.bits.version >= 0x10) {
843 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
844 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
845 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
846 UNEXPECTED_IO_APIC();
847 }
848
849 printk(KERN_DEBUG ".... IRQ redirection table:\n");
850
851 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
852 " Stat Dest Deli Vect: \n");
853
854 for (i = 0; i <= reg_01.bits.entries; i++) {
855 struct IO_APIC_route_entry entry;
856
857 entry = ioapic_read_entry(apic, i);
858
859 printk(KERN_DEBUG " %02x %03X %02X ",
860 i,
861 entry.dest.logical.logical_dest,
862 entry.dest.physical.physical_dest
863 );
864
865 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
866 entry.mask,
867 entry.trigger,
868 entry.irr,
869 entry.polarity,
870 entry.delivery_status,
871 entry.dest_mode,
872 entry.delivery_mode,
873 entry.vector
874 );
875 }
876 }
877 printk(KERN_DEBUG "IRQ to pin mappings:\n");
878 for (i = 0; i < NR_IRQS; i++) {
879 struct irq_pin_list *entry = irq_2_pin + i;
880 if (entry->pin < 0)
881 continue;
882 printk(KERN_DEBUG "IRQ%d ", i);
883 for (;;) {
884 printk("-> %d:%d", entry->apic, entry->pin);
885 if (!entry->next)
886 break;
887 entry = irq_2_pin + entry->next;
888 }
889 printk("\n");
890 }
891
892 printk(KERN_INFO ".................................... done.\n");
893
894 return;
895 }
896
897 #if 0
898
899 static __apicdebuginit void print_APIC_bitfield (int base)
900 {
901 unsigned int v;
902 int i, j;
903
904 if (apic_verbosity == APIC_QUIET)
905 return;
906
907 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
908 for (i = 0; i < 8; i++) {
909 v = apic_read(base + i*0x10);
910 for (j = 0; j < 32; j++) {
911 if (v & (1<<j))
912 printk("1");
913 else
914 printk("0");
915 }
916 printk("\n");
917 }
918 }
919
920 void __apicdebuginit print_local_APIC(void * dummy)
921 {
922 unsigned int v, ver, maxlvt;
923
924 if (apic_verbosity == APIC_QUIET)
925 return;
926
927 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
928 smp_processor_id(), hard_smp_processor_id());
929 v = apic_read(APIC_ID);
930 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
931 v = apic_read(APIC_LVR);
932 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
933 ver = GET_APIC_VERSION(v);
934 maxlvt = get_maxlvt();
935
936 v = apic_read(APIC_TASKPRI);
937 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
938
939 v = apic_read(APIC_ARBPRI);
940 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
941 v & APIC_ARBPRI_MASK);
942 v = apic_read(APIC_PROCPRI);
943 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
944
945 v = apic_read(APIC_EOI);
946 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
947 v = apic_read(APIC_RRR);
948 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
949 v = apic_read(APIC_LDR);
950 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
951 v = apic_read(APIC_DFR);
952 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
953 v = apic_read(APIC_SPIV);
954 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
955
956 printk(KERN_DEBUG "... APIC ISR field:\n");
957 print_APIC_bitfield(APIC_ISR);
958 printk(KERN_DEBUG "... APIC TMR field:\n");
959 print_APIC_bitfield(APIC_TMR);
960 printk(KERN_DEBUG "... APIC IRR field:\n");
961 print_APIC_bitfield(APIC_IRR);
962
963 v = apic_read(APIC_ESR);
964 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
965
966 v = apic_read(APIC_ICR);
967 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
968 v = apic_read(APIC_ICR2);
969 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
970
971 v = apic_read(APIC_LVTT);
972 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
973
974 if (maxlvt > 3) { /* PC is LVT#4. */
975 v = apic_read(APIC_LVTPC);
976 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
977 }
978 v = apic_read(APIC_LVT0);
979 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
980 v = apic_read(APIC_LVT1);
981 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
982
983 if (maxlvt > 2) { /* ERR is LVT#3. */
984 v = apic_read(APIC_LVTERR);
985 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
986 }
987
988 v = apic_read(APIC_TMICT);
989 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
990 v = apic_read(APIC_TMCCT);
991 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
992 v = apic_read(APIC_TDCR);
993 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
994 printk("\n");
995 }
996
997 void print_all_local_APICs (void)
998 {
999 on_each_cpu(print_local_APIC, NULL, 1, 1);
1000 }
1001
1002 void __apicdebuginit print_PIC(void)
1003 {
1004 unsigned int v;
1005 unsigned long flags;
1006
1007 if (apic_verbosity == APIC_QUIET)
1008 return;
1009
1010 printk(KERN_DEBUG "\nprinting PIC contents\n");
1011
1012 spin_lock_irqsave(&i8259A_lock, flags);
1013
1014 v = inb(0xa1) << 8 | inb(0x21);
1015 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1016
1017 v = inb(0xa0) << 8 | inb(0x20);
1018 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1019
1020 outb(0x0b,0xa0);
1021 outb(0x0b,0x20);
1022 v = inb(0xa0) << 8 | inb(0x20);
1023 outb(0x0a,0xa0);
1024 outb(0x0a,0x20);
1025
1026 spin_unlock_irqrestore(&i8259A_lock, flags);
1027
1028 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1029
1030 v = inb(0x4d1) << 8 | inb(0x4d0);
1031 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1032 }
1033
1034 #endif /* 0 */
1035
1036 static void __init enable_IO_APIC(void)
1037 {
1038 union IO_APIC_reg_01 reg_01;
1039 int i8259_apic, i8259_pin;
1040 int i, apic;
1041 unsigned long flags;
1042
1043 for (i = 0; i < PIN_MAP_SIZE; i++) {
1044 irq_2_pin[i].pin = -1;
1045 irq_2_pin[i].next = 0;
1046 }
1047
1048 /*
1049 * The number of IO-APIC IRQ registers (== #pins):
1050 */
1051 for (apic = 0; apic < nr_ioapics; apic++) {
1052 spin_lock_irqsave(&ioapic_lock, flags);
1053 reg_01.raw = io_apic_read(apic, 1);
1054 spin_unlock_irqrestore(&ioapic_lock, flags);
1055 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1056 }
1057 for(apic = 0; apic < nr_ioapics; apic++) {
1058 int pin;
1059 /* See if any of the pins is in ExtINT mode */
1060 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1061 struct IO_APIC_route_entry entry;
1062 entry = ioapic_read_entry(apic, pin);
1063
1064 /* If the interrupt line is enabled and in ExtInt mode
1065 * I have found the pin where the i8259 is connected.
1066 */
1067 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1068 ioapic_i8259.apic = apic;
1069 ioapic_i8259.pin = pin;
1070 goto found_i8259;
1071 }
1072 }
1073 }
1074 found_i8259:
1075 /* Look to see what if the MP table has reported the ExtINT */
1076 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1077 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1078 /* Trust the MP table if nothing is setup in the hardware */
1079 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1080 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1081 ioapic_i8259.pin = i8259_pin;
1082 ioapic_i8259.apic = i8259_apic;
1083 }
1084 /* Complain if the MP table and the hardware disagree */
1085 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1086 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1087 {
1088 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1089 }
1090
1091 /*
1092 * Do not trust the IO-APIC being empty at bootup
1093 */
1094 clear_IO_APIC();
1095 }
1096
1097 /*
1098 * Not an __init, needed by the reboot code
1099 */
1100 void disable_IO_APIC(void)
1101 {
1102 /*
1103 * Clear the IO-APIC before rebooting:
1104 */
1105 clear_IO_APIC();
1106
1107 /*
1108 * If the i8259 is routed through an IOAPIC
1109 * Put that IOAPIC in virtual wire mode
1110 * so legacy interrupts can be delivered.
1111 */
1112 if (ioapic_i8259.pin != -1) {
1113 struct IO_APIC_route_entry entry;
1114
1115 memset(&entry, 0, sizeof(entry));
1116 entry.mask = 0; /* Enabled */
1117 entry.trigger = 0; /* Edge */
1118 entry.irr = 0;
1119 entry.polarity = 0; /* High */
1120 entry.delivery_status = 0;
1121 entry.dest_mode = 0; /* Physical */
1122 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1123 entry.vector = 0;
1124 entry.dest.physical.physical_dest =
1125 GET_APIC_ID(apic_read(APIC_ID));
1126
1127 /*
1128 * Add it to the IO-APIC irq-routing table:
1129 */
1130 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1131 }
1132
1133 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1134 }
1135
1136 /*
1137 * There is a nasty bug in some older SMP boards, their mptable lies
1138 * about the timer IRQ. We do the following to work around the situation:
1139 *
1140 * - timer IRQ defaults to IO-APIC IRQ
1141 * - if this function detects that timer IRQs are defunct, then we fall
1142 * back to ISA timer IRQs
1143 */
1144 static int __init timer_irq_works(void)
1145 {
1146 unsigned long t1 = jiffies;
1147
1148 local_irq_enable();
1149 /* Let ten ticks pass... */
1150 mdelay((10 * 1000) / HZ);
1151
1152 /*
1153 * Expect a few ticks at least, to be sure some possible
1154 * glue logic does not lock up after one or two first
1155 * ticks in a non-ExtINT mode. Also the local APIC
1156 * might have cached one ExtINT interrupt. Finally, at
1157 * least one tick may be lost due to delays.
1158 */
1159
1160 /* jiffies wrap? */
1161 if (jiffies - t1 > 4)
1162 return 1;
1163 return 0;
1164 }
1165
1166 /*
1167 * In the SMP+IOAPIC case it might happen that there are an unspecified
1168 * number of pending IRQ events unhandled. These cases are very rare,
1169 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1170 * better to do it this way as thus we do not have to be aware of
1171 * 'pending' interrupts in the IRQ path, except at this point.
1172 */
1173 /*
1174 * Edge triggered needs to resend any interrupt
1175 * that was delayed but this is now handled in the device
1176 * independent code.
1177 */
1178
1179 /*
1180 * Starting up a edge-triggered IO-APIC interrupt is
1181 * nasty - we need to make sure that we get the edge.
1182 * If it is already asserted for some reason, we need
1183 * return 1 to indicate that is was pending.
1184 *
1185 * This is not complete - we should be able to fake
1186 * an edge even if it isn't on the 8259A...
1187 */
1188
1189 static unsigned int startup_ioapic_irq(unsigned int irq)
1190 {
1191 int was_pending = 0;
1192 unsigned long flags;
1193
1194 spin_lock_irqsave(&ioapic_lock, flags);
1195 if (irq < 16) {
1196 disable_8259A_irq(irq);
1197 if (i8259A_irq_pending(irq))
1198 was_pending = 1;
1199 }
1200 __unmask_IO_APIC_irq(irq);
1201 spin_unlock_irqrestore(&ioapic_lock, flags);
1202
1203 return was_pending;
1204 }
1205
1206 static int ioapic_retrigger_irq(unsigned int irq)
1207 {
1208 cpumask_t mask;
1209 unsigned vector;
1210
1211 vector = irq_vector[irq];
1212 cpus_clear(mask);
1213 cpu_set(vector >> 8, mask);
1214
1215 send_IPI_mask(mask, vector & 0xff);
1216
1217 return 1;
1218 }
1219
1220 /*
1221 * Level and edge triggered IO-APIC interrupts need different handling,
1222 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1223 * handled with the level-triggered descriptor, but that one has slightly
1224 * more overhead. Level-triggered interrupts cannot be handled with the
1225 * edge-triggered handler, without risking IRQ storms and other ugly
1226 * races.
1227 */
1228
1229 static void ack_apic_edge(unsigned int irq)
1230 {
1231 move_native_irq(irq);
1232 ack_APIC_irq();
1233 }
1234
1235 static void ack_apic_level(unsigned int irq)
1236 {
1237 int do_unmask_irq = 0;
1238
1239 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1240 /* If we are moving the irq we need to mask it */
1241 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1242 do_unmask_irq = 1;
1243 mask_IO_APIC_irq(irq);
1244 }
1245 #endif
1246
1247 /*
1248 * We must acknowledge the irq before we move it or the acknowledge will
1249 * not propogate properly.
1250 */
1251 ack_APIC_irq();
1252
1253 /* Now we can move and renable the irq */
1254 move_masked_irq(irq);
1255 if (unlikely(do_unmask_irq))
1256 unmask_IO_APIC_irq(irq);
1257 }
1258
1259 static struct irq_chip ioapic_chip __read_mostly = {
1260 .name = "IO-APIC",
1261 .startup = startup_ioapic_irq,
1262 .mask = mask_IO_APIC_irq,
1263 .unmask = unmask_IO_APIC_irq,
1264 .ack = ack_apic_edge,
1265 .eoi = ack_apic_level,
1266 #ifdef CONFIG_SMP
1267 .set_affinity = set_ioapic_affinity_irq,
1268 #endif
1269 .retrigger = ioapic_retrigger_irq,
1270 };
1271
1272 static inline void init_IO_APIC_traps(void)
1273 {
1274 int irq;
1275
1276 /*
1277 * NOTE! The local APIC isn't very good at handling
1278 * multiple interrupts at the same interrupt level.
1279 * As the interrupt level is determined by taking the
1280 * vector number and shifting that right by 4, we
1281 * want to spread these out a bit so that they don't
1282 * all fall in the same interrupt level.
1283 *
1284 * Also, we've got to be careful not to trash gate
1285 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1286 */
1287 for (irq = 0; irq < NR_IRQS ; irq++) {
1288 int tmp = irq;
1289 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1290 /*
1291 * Hmm.. We don't have an entry for this,
1292 * so default to an old-fashioned 8259
1293 * interrupt if we can..
1294 */
1295 if (irq < 16)
1296 make_8259A_irq(irq);
1297 else
1298 /* Strange. Oh, well.. */
1299 irq_desc[irq].chip = &no_irq_chip;
1300 }
1301 }
1302 }
1303
1304 static void enable_lapic_irq (unsigned int irq)
1305 {
1306 unsigned long v;
1307
1308 v = apic_read(APIC_LVT0);
1309 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1310 }
1311
1312 static void disable_lapic_irq (unsigned int irq)
1313 {
1314 unsigned long v;
1315
1316 v = apic_read(APIC_LVT0);
1317 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1318 }
1319
1320 static void ack_lapic_irq (unsigned int irq)
1321 {
1322 ack_APIC_irq();
1323 }
1324
1325 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1326
1327 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1328 .typename = "local-APIC-edge",
1329 .startup = NULL, /* startup_irq() not used for IRQ0 */
1330 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1331 .enable = enable_lapic_irq,
1332 .disable = disable_lapic_irq,
1333 .ack = ack_lapic_irq,
1334 .end = end_lapic_irq,
1335 };
1336
1337 static void setup_nmi (void)
1338 {
1339 /*
1340 * Dirty trick to enable the NMI watchdog ...
1341 * We put the 8259A master into AEOI mode and
1342 * unmask on all local APICs LVT0 as NMI.
1343 *
1344 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1345 * is from Maciej W. Rozycki - so we do not have to EOI from
1346 * the NMI handler or the timer interrupt.
1347 */
1348 printk(KERN_INFO "activating NMI Watchdog ...");
1349
1350 enable_NMI_through_LVT0(NULL);
1351
1352 printk(" done.\n");
1353 }
1354
1355 /*
1356 * This looks a bit hackish but it's about the only one way of sending
1357 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1358 * not support the ExtINT mode, unfortunately. We need to send these
1359 * cycles as some i82489DX-based boards have glue logic that keeps the
1360 * 8259A interrupt line asserted until INTA. --macro
1361 */
1362 static inline void unlock_ExtINT_logic(void)
1363 {
1364 int apic, pin, i;
1365 struct IO_APIC_route_entry entry0, entry1;
1366 unsigned char save_control, save_freq_select;
1367 unsigned long flags;
1368
1369 pin = find_isa_irq_pin(8, mp_INT);
1370 apic = find_isa_irq_apic(8, mp_INT);
1371 if (pin == -1)
1372 return;
1373
1374 spin_lock_irqsave(&ioapic_lock, flags);
1375 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1376 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1377 spin_unlock_irqrestore(&ioapic_lock, flags);
1378 clear_IO_APIC_pin(apic, pin);
1379
1380 memset(&entry1, 0, sizeof(entry1));
1381
1382 entry1.dest_mode = 0; /* physical delivery */
1383 entry1.mask = 0; /* unmask IRQ now */
1384 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1385 entry1.delivery_mode = dest_ExtINT;
1386 entry1.polarity = entry0.polarity;
1387 entry1.trigger = 0;
1388 entry1.vector = 0;
1389
1390 spin_lock_irqsave(&ioapic_lock, flags);
1391 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1392 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1393 spin_unlock_irqrestore(&ioapic_lock, flags);
1394
1395 save_control = CMOS_READ(RTC_CONTROL);
1396 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1397 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1398 RTC_FREQ_SELECT);
1399 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1400
1401 i = 100;
1402 while (i-- > 0) {
1403 mdelay(10);
1404 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1405 i -= 10;
1406 }
1407
1408 CMOS_WRITE(save_control, RTC_CONTROL);
1409 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1410 clear_IO_APIC_pin(apic, pin);
1411
1412 spin_lock_irqsave(&ioapic_lock, flags);
1413 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1414 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1415 spin_unlock_irqrestore(&ioapic_lock, flags);
1416 }
1417
1418 int timer_uses_ioapic_pin_0;
1419
1420 /*
1421 * This code may look a bit paranoid, but it's supposed to cooperate with
1422 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1423 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1424 * fanatically on his truly buggy board.
1425 *
1426 * FIXME: really need to revamp this for modern platforms only.
1427 */
1428 static inline void check_timer(void)
1429 {
1430 int apic1, pin1, apic2, pin2;
1431 int vector;
1432
1433 /*
1434 * get/set the timer IRQ vector:
1435 */
1436 disable_8259A_irq(0);
1437 vector = assign_irq_vector(0, TARGET_CPUS);
1438
1439 /*
1440 * Subtle, code in do_timer_interrupt() expects an AEOI
1441 * mode for the 8259A whenever interrupts are routed
1442 * through I/O APICs. Also IRQ0 has to be enabled in
1443 * the 8259A which implies the virtual wire has to be
1444 * disabled in the local APIC.
1445 */
1446 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1447 init_8259A(1);
1448 if (timer_over_8254 > 0)
1449 enable_8259A_irq(0);
1450
1451 pin1 = find_isa_irq_pin(0, mp_INT);
1452 apic1 = find_isa_irq_apic(0, mp_INT);
1453 pin2 = ioapic_i8259.pin;
1454 apic2 = ioapic_i8259.apic;
1455
1456 if (pin1 == 0)
1457 timer_uses_ioapic_pin_0 = 1;
1458
1459 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1460 vector, apic1, pin1, apic2, pin2);
1461
1462 if (pin1 != -1) {
1463 /*
1464 * Ok, does IRQ0 through the IOAPIC work?
1465 */
1466 unmask_IO_APIC_irq(0);
1467 if (!no_timer_check && timer_irq_works()) {
1468 nmi_watchdog_default();
1469 if (nmi_watchdog == NMI_IO_APIC) {
1470 disable_8259A_irq(0);
1471 setup_nmi();
1472 enable_8259A_irq(0);
1473 }
1474 if (disable_timer_pin_1 > 0)
1475 clear_IO_APIC_pin(0, pin1);
1476 return;
1477 }
1478 clear_IO_APIC_pin(apic1, pin1);
1479 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1480 "connected to IO-APIC\n");
1481 }
1482
1483 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1484 "through the 8259A ... ");
1485 if (pin2 != -1) {
1486 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1487 apic2, pin2);
1488 /*
1489 * legacy devices should be connected to IO APIC #0
1490 */
1491 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1492 if (timer_irq_works()) {
1493 apic_printk(APIC_VERBOSE," works.\n");
1494 nmi_watchdog_default();
1495 if (nmi_watchdog == NMI_IO_APIC) {
1496 setup_nmi();
1497 }
1498 return;
1499 }
1500 /*
1501 * Cleanup, just in case ...
1502 */
1503 clear_IO_APIC_pin(apic2, pin2);
1504 }
1505 apic_printk(APIC_VERBOSE," failed.\n");
1506
1507 if (nmi_watchdog == NMI_IO_APIC) {
1508 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1509 nmi_watchdog = 0;
1510 }
1511
1512 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1513
1514 disable_8259A_irq(0);
1515 irq_desc[0].chip = &lapic_irq_type;
1516 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1517 enable_8259A_irq(0);
1518
1519 if (timer_irq_works()) {
1520 apic_printk(APIC_VERBOSE," works.\n");
1521 return;
1522 }
1523 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1524 apic_printk(APIC_VERBOSE," failed.\n");
1525
1526 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1527
1528 init_8259A(0);
1529 make_8259A_irq(0);
1530 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1531
1532 unlock_ExtINT_logic();
1533
1534 if (timer_irq_works()) {
1535 apic_printk(APIC_VERBOSE," works.\n");
1536 return;
1537 }
1538 apic_printk(APIC_VERBOSE," failed :(.\n");
1539 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1540 }
1541
1542 static int __init notimercheck(char *s)
1543 {
1544 no_timer_check = 1;
1545 return 1;
1546 }
1547 __setup("no_timer_check", notimercheck);
1548
1549 /*
1550 *
1551 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1552 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1553 * Linux doesn't really care, as it's not actually used
1554 * for any interrupt handling anyway.
1555 */
1556 #define PIC_IRQS (1<<2)
1557
1558 void __init setup_IO_APIC(void)
1559 {
1560 enable_IO_APIC();
1561
1562 if (acpi_ioapic)
1563 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1564 else
1565 io_apic_irqs = ~PIC_IRQS;
1566
1567 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1568
1569 sync_Arb_IDs();
1570 setup_IO_APIC_irqs();
1571 init_IO_APIC_traps();
1572 check_timer();
1573 if (!acpi_ioapic)
1574 print_IO_APIC();
1575 }
1576
1577 struct sysfs_ioapic_data {
1578 struct sys_device dev;
1579 struct IO_APIC_route_entry entry[0];
1580 };
1581 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1582
1583 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1584 {
1585 struct IO_APIC_route_entry *entry;
1586 struct sysfs_ioapic_data *data;
1587 int i;
1588
1589 data = container_of(dev, struct sysfs_ioapic_data, dev);
1590 entry = data->entry;
1591 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1592 *entry = ioapic_read_entry(dev->id, i);
1593
1594 return 0;
1595 }
1596
1597 static int ioapic_resume(struct sys_device *dev)
1598 {
1599 struct IO_APIC_route_entry *entry;
1600 struct sysfs_ioapic_data *data;
1601 unsigned long flags;
1602 union IO_APIC_reg_00 reg_00;
1603 int i;
1604
1605 data = container_of(dev, struct sysfs_ioapic_data, dev);
1606 entry = data->entry;
1607
1608 spin_lock_irqsave(&ioapic_lock, flags);
1609 reg_00.raw = io_apic_read(dev->id, 0);
1610 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1611 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1612 io_apic_write(dev->id, 0, reg_00.raw);
1613 }
1614 spin_unlock_irqrestore(&ioapic_lock, flags);
1615 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1616 ioapic_write_entry(dev->id, i, entry[i]);
1617
1618 return 0;
1619 }
1620
1621 static struct sysdev_class ioapic_sysdev_class = {
1622 set_kset_name("ioapic"),
1623 .suspend = ioapic_suspend,
1624 .resume = ioapic_resume,
1625 };
1626
1627 static int __init ioapic_init_sysfs(void)
1628 {
1629 struct sys_device * dev;
1630 int i, size, error = 0;
1631
1632 error = sysdev_class_register(&ioapic_sysdev_class);
1633 if (error)
1634 return error;
1635
1636 for (i = 0; i < nr_ioapics; i++ ) {
1637 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1638 * sizeof(struct IO_APIC_route_entry);
1639 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1640 if (!mp_ioapic_data[i]) {
1641 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1642 continue;
1643 }
1644 memset(mp_ioapic_data[i], 0, size);
1645 dev = &mp_ioapic_data[i]->dev;
1646 dev->id = i;
1647 dev->cls = &ioapic_sysdev_class;
1648 error = sysdev_register(dev);
1649 if (error) {
1650 kfree(mp_ioapic_data[i]);
1651 mp_ioapic_data[i] = NULL;
1652 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1653 continue;
1654 }
1655 }
1656
1657 return 0;
1658 }
1659
1660 device_initcall(ioapic_init_sysfs);
1661
1662 /*
1663 * Dynamic irq allocate and deallocation
1664 */
1665 int create_irq(void)
1666 {
1667 /* Allocate an unused irq */
1668 int irq;
1669 int new;
1670 int vector = 0;
1671 unsigned long flags;
1672
1673 irq = -ENOSPC;
1674 spin_lock_irqsave(&vector_lock, flags);
1675 for (new = (NR_IRQS - 1); new >= 0; new--) {
1676 if (platform_legacy_irq(new))
1677 continue;
1678 if (irq_vector[new] != 0)
1679 continue;
1680 vector = __assign_irq_vector(new, TARGET_CPUS);
1681 if (likely(vector > 0))
1682 irq = new;
1683 break;
1684 }
1685 spin_unlock_irqrestore(&vector_lock, flags);
1686
1687 if (irq >= 0) {
1688 dynamic_irq_init(irq);
1689 }
1690 return irq;
1691 }
1692
1693 void destroy_irq(unsigned int irq)
1694 {
1695 unsigned long flags;
1696
1697 dynamic_irq_cleanup(irq);
1698
1699 spin_lock_irqsave(&vector_lock, flags);
1700 irq_vector[irq] = 0;
1701 spin_unlock_irqrestore(&vector_lock, flags);
1702 }
1703
1704 /*
1705 * MSI mesage composition
1706 */
1707 #ifdef CONFIG_PCI_MSI
1708 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1709 {
1710 /* For now always this code always uses physical delivery
1711 * mode.
1712 */
1713 int vector;
1714 unsigned dest;
1715
1716 vector = assign_irq_vector(irq, TARGET_CPUS);
1717 if (vector >= 0) {
1718 cpumask_t tmp;
1719
1720 cpus_clear(tmp);
1721 cpu_set(vector >> 8, tmp);
1722 dest = cpu_mask_to_apicid(tmp);
1723
1724 msg->address_hi = MSI_ADDR_BASE_HI;
1725 msg->address_lo =
1726 MSI_ADDR_BASE_LO |
1727 ((INT_DEST_MODE == 0) ?
1728 MSI_ADDR_DEST_MODE_PHYSICAL:
1729 MSI_ADDR_DEST_MODE_LOGICAL) |
1730 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1731 MSI_ADDR_REDIRECTION_CPU:
1732 MSI_ADDR_REDIRECTION_LOWPRI) |
1733 MSI_ADDR_DEST_ID(dest);
1734
1735 msg->data =
1736 MSI_DATA_TRIGGER_EDGE |
1737 MSI_DATA_LEVEL_ASSERT |
1738 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1739 MSI_DATA_DELIVERY_FIXED:
1740 MSI_DATA_DELIVERY_LOWPRI) |
1741 MSI_DATA_VECTOR(vector);
1742 }
1743 return vector;
1744 }
1745
1746 static void msi_msg_teardown(unsigned int irq)
1747 {
1748 return;
1749 }
1750
1751 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
1752 {
1753 int vector;
1754 unsigned dest;
1755
1756 vector = assign_irq_vector(irq, mask);
1757 if (vector > 0) {
1758 cpumask_t tmp;
1759
1760 cpus_clear(tmp);
1761 cpu_set(vector >> 8, tmp);
1762 dest = cpu_mask_to_apicid(tmp);
1763
1764 msg->data &= ~MSI_DATA_VECTOR_MASK;
1765 msg->data |= MSI_DATA_VECTOR(vector);
1766 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1767 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
1768 }
1769 }
1770
1771 struct msi_ops arch_msi_ops = {
1772 .needs_64bit_address = 0,
1773 .setup = msi_msg_setup,
1774 .teardown = msi_msg_teardown,
1775 .target = msi_msg_set_affinity,
1776 };
1777
1778 #endif
1779
1780 /* --------------------------------------------------------------------------
1781 ACPI-based IOAPIC Configuration
1782 -------------------------------------------------------------------------- */
1783
1784 #ifdef CONFIG_ACPI
1785
1786 #define IO_APIC_MAX_ID 0xFE
1787
1788 int __init io_apic_get_redir_entries (int ioapic)
1789 {
1790 union IO_APIC_reg_01 reg_01;
1791 unsigned long flags;
1792
1793 spin_lock_irqsave(&ioapic_lock, flags);
1794 reg_01.raw = io_apic_read(ioapic, 1);
1795 spin_unlock_irqrestore(&ioapic_lock, flags);
1796
1797 return reg_01.bits.entries;
1798 }
1799
1800
1801 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1802 {
1803 struct IO_APIC_route_entry entry;
1804 unsigned long flags;
1805 int vector;
1806 cpumask_t mask;
1807
1808 if (!IO_APIC_IRQ(irq)) {
1809 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1810 ioapic);
1811 return -EINVAL;
1812 }
1813
1814 /*
1815 * IRQs < 16 are already in the irq_2_pin[] map
1816 */
1817 if (irq >= 16)
1818 add_pin_to_irq(irq, ioapic, pin);
1819
1820
1821 vector = assign_irq_vector(irq, TARGET_CPUS);
1822 if (vector < 0)
1823 return vector;
1824
1825 cpus_clear(mask);
1826 cpu_set(vector >> 8, mask);
1827
1828 /*
1829 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1830 * Note that we mask (disable) IRQs now -- these get enabled when the
1831 * corresponding device driver registers for this IRQ.
1832 */
1833
1834 memset(&entry,0,sizeof(entry));
1835
1836 entry.delivery_mode = INT_DELIVERY_MODE;
1837 entry.dest_mode = INT_DEST_MODE;
1838 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
1839 entry.trigger = triggering;
1840 entry.polarity = polarity;
1841 entry.mask = 1; /* Disabled (masked) */
1842 entry.vector = vector & 0xff;
1843
1844 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1845 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1846 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1847 triggering, polarity);
1848
1849 ioapic_register_intr(irq, entry.vector, triggering);
1850
1851 if (!ioapic && (irq < 16))
1852 disable_8259A_irq(irq);
1853
1854 ioapic_write_entry(ioapic, pin, entry);
1855
1856 spin_lock_irqsave(&ioapic_lock, flags);
1857 set_native_irq_info(irq, TARGET_CPUS);
1858 spin_unlock_irqrestore(&ioapic_lock, flags);
1859
1860 return 0;
1861 }
1862
1863 #endif /* CONFIG_ACPI */
1864
1865
1866 /*
1867 * This function currently is only a helper for the i386 smp boot process where
1868 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1869 * so mask in all cases should simply be TARGET_CPUS
1870 */
1871 #ifdef CONFIG_SMP
1872 void __init setup_ioapic_dest(void)
1873 {
1874 int pin, ioapic, irq, irq_entry;
1875
1876 if (skip_ioapic_setup == 1)
1877 return;
1878
1879 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1880 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1881 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1882 if (irq_entry == -1)
1883 continue;
1884 irq = pin_2_irq(irq_entry, ioapic, pin);
1885 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1886 }
1887
1888 }
1889 }
1890 #endif
linux v2.6.22.y-op