drivers/ide/pci/cs5520.c

   1 /*
   2  *      IDE tuning and bus mastering support for the CS5510/CS5520
   3  *      chipsets
   4  *
   5  *      The CS5510/CS5520 are slightly unusual devices. Unlike the
   6  *      typical IDE controllers they do bus mastering with the drive in
   7  *      PIO mode and smarter silicon.
   8  *
   9  *      The practical upshot of this is that we must always tune the
  10  *      drive for the right PIO mode. We must also ignore all the blacklists
  11  *      and the drive bus mastering DMA information.
  12  *
  13  *      *** This driver is strictly experimental ***
  14  *
  15  *      (c) Copyright Red Hat Inc 2002
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2, or (at your option) any
  20  * later version.
  21  *
  22  * This program is distributed in the hope that it will be useful, but
  23  * WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  25  * General Public License for more details.
  26  *
  27  * For the avoidance of doubt the "preferred form" of this code is one which
  28  * is in an open non patent encumbered format. Where cryptographic key signing
  29  * forms part of the process of creating an executable the information
  30  * including keys needed to generate an equivalently functional executable
  31  * are deemed to be part of the source code.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/types.h>
  37 #include <linux/kernel.h>
  38 #include <linux/delay.h>
  39 #include <linux/timer.h>
  40 #include <linux/mm.h>
  41 #include <linux/ioport.h>
  42 #include <linux/blkdev.h>
  43 #include <linux/hdreg.h>
  44
  45 #include <linux/interrupt.h>
  46 #include <linux/init.h>
  47 #include <linux/pci.h>
  48 #include <linux/ide.h>
  49 #include <linux/dma-mapping.h>
  50
  51 #include <asm/io.h>
  52 #include <asm/irq.h>
  53
  54 struct pio_clocks
  55 {
  56         int address;
  57         int assert;
  58         int recovery;
  59 };
  60
  61 static struct pio_clocks cs5520_pio_clocks[]={
  62         {3, 6, 11},
  63         {2, 5, 6},
  64         {1, 4, 3},
  65         {1, 3, 2},
  66         {1, 2, 1}
  67 };
  68
  69 static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
  70 {
  71         ide_hwif_t *hwif = HWIF(drive);
  72         struct pci_dev *pdev = hwif->pci_dev;
  73         u8 speed = min((u8)XFER_PIO_4, xferspeed);
  74         int pio = speed;
  75         u8 reg;
  76         int controller = drive->dn > 1 ? 1 : 0;
  77         int error;
  78
  79         switch(speed)
  80         {
  81                 case XFER_PIO_4:
  82                 case XFER_PIO_3:
  83                 case XFER_PIO_2:
  84                 case XFER_PIO_1:
  85                 case XFER_PIO_0:
  86                         pio -= XFER_PIO_0;
  87                         break;
  88                 default:
  89                         pio = 0;
  90                         printk(KERN_ERR "cs55x0: bad ide timing.\n");
  91         }
  92
  93         printk("PIO clocking = %d\n", pio);
  94
  95         /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
  96
  97         /* 8bit CAT/CRT - 8bit command timing for channel */
  98         pci_write_config_byte(pdev, 0x62 + controller,
  99                 (cs5520_pio_clocks[pio].recovery << 4) |
 100                 (cs5520_pio_clocks[pio].assert));
 101
 102         /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
 103
 104         /* FIXME: should these use address ? */
 105         /* Data read timing */
 106         pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
 107                 (cs5520_pio_clocks[pio].recovery << 4) |
 108                 (cs5520_pio_clocks[pio].assert));
 109         /* Write command timing */
 110         pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
 111                 (cs5520_pio_clocks[pio].recovery << 4) |
 112                 (cs5520_pio_clocks[pio].assert));
 113
 114         /* Set the DMA enable/disable flag */
 115         reg = inb(hwif->dma_base + 0x02 + 8*controller);
 116         reg |= 1<<((drive->dn&1)+5);
 117         outb(reg, hwif->dma_base + 0x02 + 8*controller);
 118
 119         error = ide_config_drive_speed(drive, speed);
 120         /* ATAPI is harder so leave it for now */
 121         if(!error && drive->media == ide_disk)
 122                 error = hwif->ide_dma_on(drive);
 123
 124         return error;
 125 }
 126
 127 static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
 128 {
 129         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 130         cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
 131 }
 132
 133 static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
 134 {
 135         ide_hwif_t *hwif = HWIF(drive);
 136
 137         /* Tune the drive for PIO modes up to PIO 4 */
 138         cs5520_tune_drive(drive, 4);
 139         /* Then tell the core to use DMA operations */
 140         return hwif->ide_dma_on(drive);
 141 }
 142
 143 /*
 144  *      We provide a callback for our nonstandard DMA location
 145  */
 146
 147 static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
 148 {
 149         unsigned long bmide = pci_resource_start(dev, 2);       /* Not the usual 4 */
 150         if(hwif->mate && hwif->mate->dma_base)  /* Second channel at primary + 8 */
 151                 bmide += 8;
 152         ide_setup_dma(hwif, bmide, 8);
 153 }
 154
 155 /*
 156  *      We wrap the DMA activate to set the vdma flag. This is needed
 157  *      so that the IDE DMA layer issues PIO not DMA commands over the
 158  *      DMA channel
 159  */
 160
 161 static int cs5520_dma_on(ide_drive_t *drive)
 162 {
 163         drive->vdma = 1;
 164         return 0;
 165 }
 166
 167 static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
 168 {
 169         hwif->tuneproc = &cs5520_tune_drive;
 170         hwif->speedproc = &cs5520_tune_chipset;
 171         hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
 172         hwif->ide_dma_on = &cs5520_dma_on;
 173
 174         if(!noautodma)
 175                 hwif->autodma = 1;
 176
 177         if(!hwif->dma_base)
 178         {
 179                 hwif->drives[0].autotune = 1;
 180                 hwif->drives[1].autotune = 1;
 181                 return;
 182         }
 183
 184         hwif->atapi_dma = 0;
 185         hwif->ultra_mask = 0;
 186         hwif->swdma_mask = 0;
 187         hwif->mwdma_mask = 0;
 188
 189         hwif->drives[0].autodma = hwif->autodma;
 190         hwif->drives[1].autodma = hwif->autodma;
 191 }
 192
 193 #define DECLARE_CS_DEV(name_str)                                \
 194         {                                                       \
 195                 .name           = name_str,                     \
 196                 .init_setup_dma = cs5520_init_setup_dma,        \
 197                 .init_hwif      = init_hwif_cs5520,             \
 198                 .channels       = 2,                            \
 199                 .autodma        = AUTODMA,                      \
 200                 .bootable       = ON_BOARD,                     \
 201                 .flags          = IDEPCI_FLAG_ISA_PORTS,        \
 202         }
 203
 204 static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
 205         /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
 206         /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
 207 };
 208
 209 /*
 210  *      The 5510/5520 are a bit weird. They don't quite set up the way
 211  *      the PCI helper layer expects so we must do much of the set up
 212  *      work longhand.
 213  */
 214
 215 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 216 {
 217         ata_index_t index;
 218         ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
 219
 220         ide_setup_pci_noise(dev, d);
 221
 222         /* We must not grab the entire device, it has 'ISA' space in its
 223            BARS too and we will freak out other bits of the kernel */
 224         if (pci_enable_device_bars(dev, 1<<2)) {
 225                 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
 226                 return -ENODEV;
 227         }
 228         pci_set_master(dev);
 229         if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
 230                 printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
 231                 return -ENODEV;
 232         }
 233
 234         index.all = 0xf0f0;
 235
 236         /*
 237          *      Now the chipset is configured we can let the core
 238          *      do all the device setup for us
 239          */
 240
 241         ide_pci_setup_ports(dev, d, 14, &index);
 242
 243         if((index.b.low & 0xf0) != 0xf0)
 244                 probe_hwif_init(&ide_hwifs[index.b.low]);
 245         if((index.b.high & 0xf0) != 0xf0)
 246                 probe_hwif_init(&ide_hwifs[index.b.high]);
 247         return 0;
 248 }
 249
 250 static struct pci_device_id cs5520_pci_tbl[] = {
 251         { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 252         { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 253         { 0, },
 254 };
 255 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
 256
 257 static struct pci_driver driver = {
 258         .name           = "Cyrix_IDE",
 259         .id_table       = cs5520_pci_tbl,
 260         .probe          = cs5520_init_one,
 261 };
 262
 263 static int cs5520_ide_init(void)
 264 {
 265         return ide_pci_register_driver(&driver);
 266 }
 267
 268 module_init(cs5520_ide_init);
 269
 270 MODULE_AUTHOR("Alan Cox");
 271 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
 272 MODULE_LICENSE("GPL");