[XFS] endianess annotation for xfs_agfl_t. Trivial, xfs_agfl_t is always
[linux-2.6.22.y-op.git] / include / asm-arm / ptrace.h
blob5a8ef787dbf81c0c3ec5caf79471fe69a3033f07
1 /*
2 * linux/include/asm-arm/ptrace.h
4 * Copyright (C) 1996-2003 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #ifndef __ASM_ARM_PTRACE_H
11 #define __ASM_ARM_PTRACE_H
14 #define PTRACE_GETREGS 12
15 #define PTRACE_SETREGS 13
16 #define PTRACE_GETFPREGS 14
17 #define PTRACE_SETFPREGS 15
19 #define PTRACE_GETWMMXREGS 18
20 #define PTRACE_SETWMMXREGS 19
22 #define PTRACE_OLDSETOPTIONS 21
24 #define PTRACE_GET_THREAD_AREA 22
26 #define PTRACE_SET_SYSCALL 23
28 /* PTRACE_SYSCALL is 24 */
30 #define PTRACE_GETCRUNCHREGS 25
31 #define PTRACE_SETCRUNCHREGS 26
34 * PSR bits
36 #define USR26_MODE 0x00000000
37 #define FIQ26_MODE 0x00000001
38 #define IRQ26_MODE 0x00000002
39 #define SVC26_MODE 0x00000003
40 #define USR_MODE 0x00000010
41 #define FIQ_MODE 0x00000011
42 #define IRQ_MODE 0x00000012
43 #define SVC_MODE 0x00000013
44 #define ABT_MODE 0x00000017
45 #define UND_MODE 0x0000001b
46 #define SYSTEM_MODE 0x0000001f
47 #define MODE32_BIT 0x00000010
48 #define MODE_MASK 0x0000001f
49 #define PSR_T_BIT 0x00000020
50 #define PSR_F_BIT 0x00000040
51 #define PSR_I_BIT 0x00000080
52 #define PSR_J_BIT 0x01000000
53 #define PSR_Q_BIT 0x08000000
54 #define PSR_V_BIT 0x10000000
55 #define PSR_C_BIT 0x20000000
56 #define PSR_Z_BIT 0x40000000
57 #define PSR_N_BIT 0x80000000
58 #define PCMASK 0
61 * Groups of PSR bits
63 #define PSR_f 0xff000000 /* Flags */
64 #define PSR_s 0x00ff0000 /* Status */
65 #define PSR_x 0x0000ff00 /* Extension */
66 #define PSR_c 0x000000ff /* Control */
68 #ifndef __ASSEMBLY__
71 * This struct defines the way the registers are stored on the
72 * stack during a system call. Note that sizeof(struct pt_regs)
73 * has to be a multiple of 8.
75 struct pt_regs {
76 long uregs[18];
79 #define ARM_cpsr uregs[16]
80 #define ARM_pc uregs[15]
81 #define ARM_lr uregs[14]
82 #define ARM_sp uregs[13]
83 #define ARM_ip uregs[12]
84 #define ARM_fp uregs[11]
85 #define ARM_r10 uregs[10]
86 #define ARM_r9 uregs[9]
87 #define ARM_r8 uregs[8]
88 #define ARM_r7 uregs[7]
89 #define ARM_r6 uregs[6]
90 #define ARM_r5 uregs[5]
91 #define ARM_r4 uregs[4]
92 #define ARM_r3 uregs[3]
93 #define ARM_r2 uregs[2]
94 #define ARM_r1 uregs[1]
95 #define ARM_r0 uregs[0]
96 #define ARM_ORIG_r0 uregs[17]
98 #ifdef __KERNEL__
100 #define user_mode(regs) \
101 (((regs)->ARM_cpsr & 0xf) == 0)
103 #ifdef CONFIG_ARM_THUMB
104 #define thumb_mode(regs) \
105 (((regs)->ARM_cpsr & PSR_T_BIT))
106 #else
107 #define thumb_mode(regs) (0)
108 #endif
110 #define processor_mode(regs) \
111 ((regs)->ARM_cpsr & MODE_MASK)
113 #define interrupts_enabled(regs) \
114 (!((regs)->ARM_cpsr & PSR_I_BIT))
116 #define fast_interrupts_enabled(regs) \
117 (!((regs)->ARM_cpsr & PSR_F_BIT))
119 #define condition_codes(regs) \
120 ((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
122 /* Are the current registers suitable for user mode?
123 * (used to maintain security in signal handlers)
125 static inline int valid_user_regs(struct pt_regs *regs)
127 if (user_mode(regs) &&
128 (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
129 return 1;
132 * Force CPSR to something logical...
134 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
136 return 0;
139 #endif /* __KERNEL__ */
141 #define pc_pointer(v) \
142 ((v) & ~PCMASK)
144 #define instruction_pointer(regs) \
145 (pc_pointer((regs)->ARM_pc))
147 #ifdef CONFIG_SMP
148 extern unsigned long profile_pc(struct pt_regs *regs);
149 #else
150 #define profile_pc(regs) instruction_pointer(regs)
151 #endif
153 #ifdef __KERNEL__
154 #define predicate(x) ((x) & 0xf0000000)
155 #define PREDICATE_ALWAYS 0xe0000000
156 #endif
158 #endif /* __ASSEMBLY__ */
160 #endif