drivers/mtd/nand/au1550nd.c

   1 /*
   2  *  drivers/mtd/nand/au1550nd.c
   3  *
   4  *  Copyright (C) 2004 Embedded Edge, LLC
   5  *
   6  * $Id: au1550nd.c,v 1.13 2005/11/07 11:14:30 gleixner Exp $
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  */
  13
  14 #include <linux/slab.h>
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/version.h>
  21 #include <asm/io.h>
  22
  23 /* fixme: this is ugly */
  24 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
  25 #include <asm/mach-au1x00/au1xxx.h>
  26 #else
  27 #include <asm/au1000.h>
  28 #ifdef CONFIG_MIPS_PB1550
  29 #include <asm/pb1550.h>
  30 #endif
  31 #ifdef CONFIG_MIPS_DB1550
  32 #include <asm/db1x00.h>
  33 #endif
  34 #endif
  35
  36 /*
  37  * MTD structure for NAND controller
  38  */
  39 static struct mtd_info *au1550_mtd = NULL;
  40 static void __iomem *p_nand;
  41 static int nand_width = 1;      /* default x8 */
  42
  43 /*
  44  * Define partitions for flash device
  45  */
  46 static const struct mtd_partition partition_info[] = {
  47         {
  48          .name = "NAND FS 0",
  49          .offset = 0,
  50          .size = 8 * 1024 * 1024},
  51         {
  52          .name = "NAND FS 1",
  53          .offset = MTDPART_OFS_APPEND,
  54          .size = MTDPART_SIZ_FULL}
  55 };
  56
  57 /**
  58  * au_read_byte -  read one byte from the chip
  59  * @mtd:        MTD device structure
  60  *
  61  *  read function for 8bit buswith
  62  */
  63 static u_char au_read_byte(struct mtd_info *mtd)
  64 {
  65         struct nand_chip *this = mtd->priv;
  66         u_char ret = readb(this->IO_ADDR_R);
  67         au_sync();
  68         return ret;
  69 }
  70
  71 /**
  72  * au_write_byte -  write one byte to the chip
  73  * @mtd:        MTD device structure
  74  * @byte:       pointer to data byte to write
  75  *
  76  *  write function for 8it buswith
  77  */
  78 static void au_write_byte(struct mtd_info *mtd, u_char byte)
  79 {
  80         struct nand_chip *this = mtd->priv;
  81         writeb(byte, this->IO_ADDR_W);
  82         au_sync();
  83 }
  84
  85 /**
  86  * au_read_byte16 -  read one byte endianess aware from the chip
  87  * @mtd:        MTD device structure
  88  *
  89  *  read function for 16bit buswith with
  90  * endianess conversion
  91  */
  92 static u_char au_read_byte16(struct mtd_info *mtd)
  93 {
  94         struct nand_chip *this = mtd->priv;
  95         u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  96         au_sync();
  97         return ret;
  98 }
  99
 100 /**
 101  * au_write_byte16 -  write one byte endianess aware to the chip
 102  * @mtd:        MTD device structure
 103  * @byte:       pointer to data byte to write
 104  *
 105  *  write function for 16bit buswith with
 106  * endianess conversion
 107  */
 108 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
 109 {
 110         struct nand_chip *this = mtd->priv;
 111         writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
 112         au_sync();
 113 }
 114
 115 /**
 116  * au_read_word -  read one word from the chip
 117  * @mtd:        MTD device structure
 118  *
 119  *  read function for 16bit buswith without
 120  * endianess conversion
 121  */
 122 static u16 au_read_word(struct mtd_info *mtd)
 123 {
 124         struct nand_chip *this = mtd->priv;
 125         u16 ret = readw(this->IO_ADDR_R);
 126         au_sync();
 127         return ret;
 128 }
 129
 130 /**
 131  * au_write_word -  write one word to the chip
 132  * @mtd:        MTD device structure
 133  * @word:       data word to write
 134  *
 135  *  write function for 16bit buswith without
 136  * endianess conversion
 137  */
 138 static void au_write_word(struct mtd_info *mtd, u16 word)
 139 {
 140         struct nand_chip *this = mtd->priv;
 141         writew(word, this->IO_ADDR_W);
 142         au_sync();
 143 }
 144
 145 /**
 146  * au_write_buf -  write buffer to chip
 147  * @mtd:        MTD device structure
 148  * @buf:        data buffer
 149  * @len:        number of bytes to write
 150  *
 151  *  write function for 8bit buswith
 152  */
 153 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 154 {
 155         int i;
 156         struct nand_chip *this = mtd->priv;
 157
 158         for (i = 0; i < len; i++) {
 159                 writeb(buf[i], this->IO_ADDR_W);
 160                 au_sync();
 161         }
 162 }
 163
 164 /**
 165  * au_read_buf -  read chip data into buffer
 166  * @mtd:        MTD device structure
 167  * @buf:        buffer to store date
 168  * @len:        number of bytes to read
 169  *
 170  *  read function for 8bit buswith
 171  */
 172 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 173 {
 174         int i;
 175         struct nand_chip *this = mtd->priv;
 176
 177         for (i = 0; i < len; i++) {
 178                 buf[i] = readb(this->IO_ADDR_R);
 179                 au_sync();
 180         }
 181 }
 182
 183 /**
 184  * au_verify_buf -  Verify chip data against buffer
 185  * @mtd:        MTD device structure
 186  * @buf:        buffer containing the data to compare
 187  * @len:        number of bytes to compare
 188  *
 189  *  verify function for 8bit buswith
 190  */
 191 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 192 {
 193         int i;
 194         struct nand_chip *this = mtd->priv;
 195
 196         for (i = 0; i < len; i++) {
 197                 if (buf[i] != readb(this->IO_ADDR_R))
 198                         return -EFAULT;
 199                 au_sync();
 200         }
 201
 202         return 0;
 203 }
 204
 205 /**
 206  * au_write_buf16 -  write buffer to chip
 207  * @mtd:        MTD device structure
 208  * @buf:        data buffer
 209  * @len:        number of bytes to write
 210  *
 211  *  write function for 16bit buswith
 212  */
 213 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 214 {
 215         int i;
 216         struct nand_chip *this = mtd->priv;
 217         u16 *p = (u16 *) buf;
 218         len >>= 1;
 219
 220         for (i = 0; i < len; i++) {
 221                 writew(p[i], this->IO_ADDR_W);
 222                 au_sync();
 223         }
 224
 225 }
 226
 227 /**
 228  * au_read_buf16 -  read chip data into buffer
 229  * @mtd:        MTD device structure
 230  * @buf:        buffer to store date
 231  * @len:        number of bytes to read
 232  *
 233  *  read function for 16bit buswith
 234  */
 235 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 236 {
 237         int i;
 238         struct nand_chip *this = mtd->priv;
 239         u16 *p = (u16 *) buf;
 240         len >>= 1;
 241
 242         for (i = 0; i < len; i++) {
 243                 p[i] = readw(this->IO_ADDR_R);
 244                 au_sync();
 245         }
 246 }
 247
 248 /**
 249  * au_verify_buf16 -  Verify chip data against buffer
 250  * @mtd:        MTD device structure
 251  * @buf:        buffer containing the data to compare
 252  * @len:        number of bytes to compare
 253  *
 254  *  verify function for 16bit buswith
 255  */
 256 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 257 {
 258         int i;
 259         struct nand_chip *this = mtd->priv;
 260         u16 *p = (u16 *) buf;
 261         len >>= 1;
 262
 263         for (i = 0; i < len; i++) {
 264                 if (p[i] != readw(this->IO_ADDR_R))
 265                         return -EFAULT;
 266                 au_sync();
 267         }
 268         return 0;
 269 }
 270
 271
 272 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
 273 {
 274         register struct nand_chip *this = mtd->priv;
 275
 276         switch (cmd) {
 277
 278         case NAND_CTL_SETCLE:
 279                 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
 280                 break;
 281
 282         case NAND_CTL_CLRCLE:
 283                 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
 284                 break;
 285
 286         case NAND_CTL_SETALE:
 287                 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
 288                 break;
 289
 290         case NAND_CTL_CLRALE:
 291                 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
 292                 /* FIXME: Nobody knows why this is necessary,
 293                  * but it works only that way */
 294                 udelay(1);
 295                 break;
 296
 297         case NAND_CTL_SETNCE:
 298                 /* assert (force assert) chip enable */
 299                 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
 300                 break;
 301
 302         case NAND_CTL_CLRNCE:
 303                 /* deassert chip enable */
 304                 au_writel(0, MEM_STNDCTL);
 305                 break;
 306         }
 307
 308         this->IO_ADDR_R = this->IO_ADDR_W;
 309
 310         /* Drain the writebuffer */
 311         au_sync();
 312 }
 313
 314 int au1550_device_ready(struct mtd_info *mtd)
 315 {
 316         int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
 317         au_sync();
 318         return ret;
 319 }
 320
 321 /*
 322  * Main initialization routine
 323  */
 324 int __init au1xxx_nand_init(void)
 325 {
 326         struct nand_chip *this;
 327         u16 boot_swapboot = 0;  /* default value */
 328         int retval;
 329         u32 mem_staddr;
 330         u32 nand_phys;
 331
 332         /* Allocate memory for MTD device structure and private data */
 333         au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 334         if (!au1550_mtd) {
 335                 printk("Unable to allocate NAND MTD dev structure.\n");
 336                 return -ENOMEM;
 337         }
 338
 339         /* Get pointer to private data */
 340         this = (struct nand_chip *)(&au1550_mtd[1]);
 341
 342         /* Initialize structures */
 343         memset(au1550_mtd, 0, sizeof(struct mtd_info));
 344         memset(this, 0, sizeof(struct nand_chip));
 345
 346         /* Link the private data with the MTD structure */
 347         au1550_mtd->priv = this;
 348
 349         /* disable interrupts */
 350         au_writel(au_readl(MEM_STNDCTL) & ~(1 << 8), MEM_STNDCTL);
 351
 352         /* disable NAND boot */
 353         au_writel(au_readl(MEM_STNDCTL) & ~(1 << 0), MEM_STNDCTL);
 354
 355 #ifdef CONFIG_MIPS_PB1550
 356         /* set gpio206 high */
 357         au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
 358
 359         boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
 360         switch (boot_swapboot) {
 361         case 0:
 362         case 2:
 363         case 8:
 364         case 0xC:
 365         case 0xD:
 366                 /* x16 NAND Flash */
 367                 nand_width = 0;
 368                 break;
 369         case 1:
 370         case 9:
 371         case 3:
 372         case 0xE:
 373         case 0xF:
 374                 /* x8 NAND Flash */
 375                 nand_width = 1;
 376                 break;
 377         default:
 378                 printk("Pb1550 NAND: bad boot:swap\n");
 379                 retval = -EINVAL;
 380                 goto outmem;
 381         }
 382 #endif
 383
 384         /* Configure chip-select; normally done by boot code, e.g. YAMON */
 385 #ifdef NAND_STCFG
 386         if (NAND_CS == 0) {
 387                 au_writel(NAND_STCFG,  MEM_STCFG0);
 388                 au_writel(NAND_STTIME, MEM_STTIME0);
 389                 au_writel(NAND_STADDR, MEM_STADDR0);
 390         }
 391         if (NAND_CS == 1) {
 392                 au_writel(NAND_STCFG,  MEM_STCFG1);
 393                 au_writel(NAND_STTIME, MEM_STTIME1);
 394                 au_writel(NAND_STADDR, MEM_STADDR1);
 395         }
 396         if (NAND_CS == 2) {
 397                 au_writel(NAND_STCFG,  MEM_STCFG2);
 398                 au_writel(NAND_STTIME, MEM_STTIME2);
 399                 au_writel(NAND_STADDR, MEM_STADDR2);
 400         }
 401         if (NAND_CS == 3) {
 402                 au_writel(NAND_STCFG,  MEM_STCFG3);
 403                 au_writel(NAND_STTIME, MEM_STTIME3);
 404                 au_writel(NAND_STADDR, MEM_STADDR3);
 405         }
 406 #endif
 407
 408         /* Locate NAND chip-select in order to determine NAND phys address */
 409         mem_staddr = 0x00000000;
 410         if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
 411                 mem_staddr = au_readl(MEM_STADDR0);
 412         else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
 413                 mem_staddr = au_readl(MEM_STADDR1);
 414         else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
 415                 mem_staddr = au_readl(MEM_STADDR2);
 416         else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
 417                 mem_staddr = au_readl(MEM_STADDR3);
 418
 419         if (mem_staddr == 0x00000000) {
 420                 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
 421                 kfree(au1550_mtd);
 422                 return 1;
 423         }
 424         nand_phys = (mem_staddr << 4) & 0xFFFC0000;
 425
 426         p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
 427
 428         /* make controller and MTD agree */
 429         if (NAND_CS == 0)
 430                 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
 431         if (NAND_CS == 1)
 432                 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
 433         if (NAND_CS == 2)
 434                 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
 435         if (NAND_CS == 3)
 436                 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
 437
 438         /* Set address of hardware control function */
 439         this->hwcontrol = au1550_hwcontrol;
 440         this->dev_ready = au1550_device_ready;
 441         /* 30 us command delay time */
 442         this->chip_delay = 30;
 443         this->eccmode = NAND_ECC_SOFT;
 444
 445         this->options = NAND_NO_AUTOINCR;
 446
 447         if (!nand_width)
 448                 this->options |= NAND_BUSWIDTH_16;
 449
 450         this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
 451         this->write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
 452         this->write_word = au_write_word;
 453         this->read_word = au_read_word;
 454         this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
 455         this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
 456         this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
 457
 458         /* Scan to find existence of the device */
 459         if (nand_scan(au1550_mtd, 1)) {
 460                 retval = -ENXIO;
 461                 goto outio;
 462         }
 463
 464         /* Register the partitions */
 465         add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
 466
 467         return 0;
 468
 469  outio:
 470         iounmap((void *)p_nand);
 471
 472  outmem:
 473         kfree(au1550_mtd);
 474         return retval;
 475 }
 476
 477 module_init(au1xxx_nand_init);
 478
 479 /*
 480  * Clean up routine
 481  */
 482 #ifdef MODULE
 483 static void __exit au1550_cleanup(void)
 484 {
 485         struct nand_chip *this = (struct nand_chip *)&au1550_mtd[1];
 486
 487         /* Release resources, unregister device */
 488         nand_release(au1550_mtd);
 489
 490         /* Free the MTD device structure */
 491         kfree(au1550_mtd);
 492
 493         /* Unmap */
 494         iounmap((void *)p_nand);
 495 }
 496
 497 module_exit(au1550_cleanup);
 498 #endif
 499
 500 MODULE_LICENSE("GPL");
 501 MODULE_AUTHOR("Embedded Edge, LLC");
 502 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");