arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/spinlock.h>
  23
  24 #include <asm/machvec.h>
  25 #include <asm/page.h>
  26 #include <asm/system.h>
  27 #include <asm/io.h>
  28 #include <asm/sal.h>
  29 #include <asm/smp.h>
  30 #include <asm/irq.h>
  31 #include <asm/hw_irq.h>
  32
  33 /*
  34  * Low-level SAL-based PCI configuration access functions. Note that SAL
  35  * calls are already serialized (via sal_lock), so we don't need another
  36  * synchronization mechanism here.
  37  */
  38
  39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  40         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  41
  42 /* SAL 3.2 adds support for extended config space. */
  43
  44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  45         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  46
  47 static int
  48 pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  49               int reg, int len, u32 *value)
  50 {
  51         u64 addr, data = 0;
  52         int mode, result;
  53
  54         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  55                 return -EINVAL;
  56
  57         if ((seg | reg) <= 255) {
  58                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  59                 mode = 0;
  60         } else {
  61                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  62                 mode = 1;
  63         }
  64         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  65         if (result != 0)
  66                 return -EINVAL;
  67
  68         *value = (u32) data;
  69         return 0;
  70 }
  71
  72 static int
  73 pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  74                int reg, int len, u32 value)
  75 {
  76         u64 addr;
  77         int mode, result;
  78
  79         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  80                 return -EINVAL;
  81
  82         if ((seg | reg) <= 255) {
  83                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  84                 mode = 0;
  85         } else {
  86                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  87                 mode = 1;
  88         }
  89         result = ia64_sal_pci_config_write(addr, mode, len, value);
  90         if (result != 0)
  91                 return -EINVAL;
  92         return 0;
  93 }
  94
  95 static struct pci_raw_ops pci_sal_ops = {
  96         .read =         pci_sal_read,
  97         .write =        pci_sal_write
  98 };
  99
 100 struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
 101
 102 static int
 103 pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 104 {
 105         return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
 106                                  devfn, where, size, value);
 107 }
 108
 109 static int
 110 pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 111 {
 112         return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
 113                                   devfn, where, size, value);
 114 }
 115
 116 struct pci_ops pci_root_ops = {
 117         .read = pci_read,
 118         .write = pci_write,
 119 };
 120
 121 /* Called by ACPI when it finds a new root bus.  */
 122
 123 static struct pci_controller * __devinit
 124 alloc_pci_controller (int seg)
 125 {
 126         struct pci_controller *controller;
 127
 128         controller = kmalloc(sizeof(*controller), GFP_KERNEL);
 129         if (!controller)
 130                 return NULL;
 131
 132         memset(controller, 0, sizeof(*controller));
 133         controller->segment = seg;
 134         controller->node = -1;
 135         return controller;
 136 }
 137
 138 struct pci_root_info {
 139         struct pci_controller *controller;
 140         char *name;
 141 };
 142
 143 static unsigned int
 144 new_space (u64 phys_base, int sparse)
 145 {
 146         u64 mmio_base;
 147         int i;
 148
 149         if (phys_base == 0)
 150                 return 0;       /* legacy I/O port space */
 151
 152         mmio_base = (u64) ioremap(phys_base, 0);
 153         for (i = 0; i < num_io_spaces; i++)
 154                 if (io_space[i].mmio_base == mmio_base &&
 155                     io_space[i].sparse == sparse)
 156                         return i;
 157
 158         if (num_io_spaces == MAX_IO_SPACES) {
 159                 printk(KERN_ERR "PCI: Too many IO port spaces "
 160                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 161                 return ~0;
 162         }
 163
 164         i = num_io_spaces++;
 165         io_space[i].mmio_base = mmio_base;
 166         io_space[i].sparse = sparse;
 167
 168         return i;
 169 }
 170
 171 static u64 __devinit
 172 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
 173 {
 174         struct resource *resource;
 175         char *name;
 176         u64 base, min, max, base_port;
 177         unsigned int sparse = 0, space_nr, len;
 178
 179         resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 180         if (!resource) {
 181                 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 182                         info->name);
 183                 goto out;
 184         }
 185
 186         len = strlen(info->name) + 32;
 187         name = kzalloc(len, GFP_KERNEL);
 188         if (!name) {
 189                 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
 190                         info->name);
 191                 goto free_resource;
 192         }
 193
 194         min = addr->minimum;
 195         max = min + addr->address_length - 1;
 196         if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
 197                 sparse = 1;
 198
 199         space_nr = new_space(addr->translation_offset, sparse);
 200         if (space_nr == ~0)
 201                 goto free_name;
 202
 203         base = __pa(io_space[space_nr].mmio_base);
 204         base_port = IO_SPACE_BASE(space_nr);
 205         snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
 206                 base_port + min, base_port + max);
 207
 208         /*
 209          * The SDM guarantees the legacy 0-64K space is sparse, but if the
 210          * mapping is done by the processor (not the bridge), ACPI may not
 211          * mark it as sparse.
 212          */
 213         if (space_nr == 0)
 214                 sparse = 1;
 215
 216         resource->name  = name;
 217         resource->flags = IORESOURCE_MEM;
 218         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 219         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
 220         insert_resource(&iomem_resource, resource);
 221
 222         return base_port;
 223
 224 free_name:
 225         kfree(name);
 226 free_resource:
 227         kfree(resource);
 228 out:
 229         return ~0;
 230 }
 231
 232 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
 233         struct acpi_resource_address64 *addr)
 234 {
 235         acpi_status status;
 236
 237         /*
 238          * We're only interested in _CRS descriptors that are
 239          *      - address space descriptors for memory or I/O space
 240          *      - non-zero size
 241          *      - producers, i.e., the address space is routed downstream,
 242          *        not consumed by the bridge itself
 243          */
 244         status = acpi_resource_to_address64(resource, addr);
 245         if (ACPI_SUCCESS(status) &&
 246             (addr->resource_type == ACPI_MEMORY_RANGE ||
 247              addr->resource_type == ACPI_IO_RANGE) &&
 248             addr->address_length &&
 249             addr->producer_consumer == ACPI_PRODUCER)
 250                 return AE_OK;
 251
 252         return AE_ERROR;
 253 }
 254
 255 static acpi_status __devinit
 256 count_window (struct acpi_resource *resource, void *data)
 257 {
 258         unsigned int *windows = (unsigned int *) data;
 259         struct acpi_resource_address64 addr;
 260         acpi_status status;
 261
 262         status = resource_to_window(resource, &addr);
 263         if (ACPI_SUCCESS(status))
 264                 (*windows)++;
 265
 266         return AE_OK;
 267 }
 268
 269 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 270 {
 271         struct pci_root_info *info = data;
 272         struct pci_window *window;
 273         struct acpi_resource_address64 addr;
 274         acpi_status status;
 275         unsigned long flags, offset = 0;
 276         struct resource *root;
 277
 278         /* Return AE_OK for non-window resources to keep scanning for more */
 279         status = resource_to_window(res, &addr);
 280         if (!ACPI_SUCCESS(status))
 281                 return AE_OK;
 282
 283         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 284                 flags = IORESOURCE_MEM;
 285                 root = &iomem_resource;
 286                 offset = addr.translation_offset;
 287         } else if (addr.resource_type == ACPI_IO_RANGE) {
 288                 flags = IORESOURCE_IO;
 289                 root = &ioport_resource;
 290                 offset = add_io_space(info, &addr);
 291                 if (offset == ~0)
 292                         return AE_OK;
 293         } else
 294                 return AE_OK;
 295
 296         window = &info->controller->window[info->controller->windows++];
 297         window->resource.name = info->name;
 298         window->resource.flags = flags;
 299         window->resource.start = addr.minimum + offset;
 300         window->resource.end = window->resource.start + addr.address_length - 1;
 301         window->resource.child = NULL;
 302         window->offset = offset;
 303
 304         if (insert_resource(root, &window->resource)) {
 305                 printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
 306                         window->resource.start, window->resource.end,
 307                         root->name, info->name);
 308         }
 309
 310         return AE_OK;
 311 }
 312
 313 static void __devinit
 314 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 315 {
 316         int i, j;
 317
 318         j = 0;
 319         for (i = 0; i < ctrl->windows; i++) {
 320                 struct resource *res = &ctrl->window[i].resource;
 321                 /* HP's firmware has a hack to work around a Windows bug.
 322                  * Ignore these tiny memory ranges */
 323                 if ((res->flags & IORESOURCE_MEM) &&
 324                     (res->end - res->start < 16))
 325                         continue;
 326                 if (j >= PCI_BUS_NUM_RESOURCES) {
 327                         printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
 328                                         res->end, res->flags);
 329                         continue;
 330                 }
 331                 bus->resource[j++] = res;
 332         }
 333 }
 334
 335 struct pci_bus * __devinit
 336 pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
 337 {
 338         struct pci_root_info info;
 339         struct pci_controller *controller;
 340         unsigned int windows = 0;
 341         struct pci_bus *pbus;
 342         char *name;
 343         int pxm;
 344
 345         controller = alloc_pci_controller(domain);
 346         if (!controller)
 347                 goto out1;
 348
 349         controller->acpi_handle = device->handle;
 350
 351         pxm = acpi_get_pxm(controller->acpi_handle);
 352 #ifdef CONFIG_NUMA
 353         if (pxm >= 0)
 354                 controller->node = pxm_to_node(pxm);
 355 #endif
 356
 357         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 358                         &windows);
 359         controller->window = kmalloc_node(sizeof(*controller->window) * windows,
 360                         GFP_KERNEL, controller->node);
 361         if (!controller->window)
 362                 goto out2;
 363
 364         name = kmalloc(16, GFP_KERNEL);
 365         if (!name)
 366                 goto out3;
 367
 368         sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 369         info.controller = controller;
 370         info.name = name;
 371         acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
 372                         &info);
 373
 374         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 375         if (pbus)
 376                 pcibios_setup_root_windows(pbus, controller);
 377
 378         return pbus;
 379
 380 out3:
 381         kfree(controller->window);
 382 out2:
 383         kfree(controller);
 384 out1:
 385         return NULL;
 386 }
 387
 388 void pcibios_resource_to_bus(struct pci_dev *dev,
 389                 struct pci_bus_region *region, struct resource *res)
 390 {
 391         struct pci_controller *controller = PCI_CONTROLLER(dev);
 392         unsigned long offset = 0;
 393         int i;
 394
 395         for (i = 0; i < controller->windows; i++) {
 396                 struct pci_window *window = &controller->window[i];
 397                 if (!(window->resource.flags & res->flags))
 398                         continue;
 399                 if (window->resource.start > res->start)
 400                         continue;
 401                 if (window->resource.end < res->end)
 402                         continue;
 403                 offset = window->offset;
 404                 break;
 405         }
 406
 407         region->start = res->start - offset;
 408         region->end = res->end - offset;
 409 }
 410 EXPORT_SYMBOL(pcibios_resource_to_bus);
 411
 412 void pcibios_bus_to_resource(struct pci_dev *dev,
 413                 struct resource *res, struct pci_bus_region *region)
 414 {
 415         struct pci_controller *controller = PCI_CONTROLLER(dev);
 416         unsigned long offset = 0;
 417         int i;
 418
 419         for (i = 0; i < controller->windows; i++) {
 420                 struct pci_window *window = &controller->window[i];
 421                 if (!(window->resource.flags & res->flags))
 422                         continue;
 423                 if (window->resource.start - window->offset > region->start)
 424                         continue;
 425                 if (window->resource.end - window->offset < region->end)
 426                         continue;
 427                 offset = window->offset;
 428                 break;
 429         }
 430
 431         res->start = region->start + offset;
 432         res->end = region->end + offset;
 433 }
 434 EXPORT_SYMBOL(pcibios_bus_to_resource);
 435
 436 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 437 {
 438         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 439         struct resource *devr = &dev->resource[idx];
 440
 441         if (!dev->bus)
 442                 return 0;
 443         for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
 444                 struct resource *busr = dev->bus->resource[i];
 445
 446                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 447                         continue;
 448                 if ((devr->start) && (devr->start >= busr->start) &&
 449                                 (devr->end <= busr->end))
 450                         return 1;
 451         }
 452         return 0;
 453 }
 454
 455 static void __devinit
 456 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 457 {
 458         struct pci_bus_region region;
 459         int i;
 460
 461         for (i = start; i < limit; i++) {
 462                 if (!dev->resource[i].flags)
 463                         continue;
 464                 region.start = dev->resource[i].start;
 465                 region.end = dev->resource[i].end;
 466                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 467                 if ((is_valid_resource(dev, i)))
 468                         pci_claim_resource(dev, i);
 469         }
 470 }
 471
 472 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 473 {
 474         pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 475 }
 476 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 477
 478 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 479 {
 480         pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
 481 }
 482
 483 /*
 484  *  Called after each bus is probed, but before its children are examined.
 485  */
 486 void __devinit
 487 pcibios_fixup_bus (struct pci_bus *b)
 488 {
 489         struct pci_dev *dev;
 490
 491         if (b->self) {
 492                 pci_read_bridge_bases(b);
 493                 pcibios_fixup_bridge_resources(b->self);
 494         }
 495         list_for_each_entry(dev, &b->devices, bus_list)
 496                 pcibios_fixup_device_resources(dev);
 497         platform_pci_fixup_bus(b);
 498
 499         return;
 500 }
 501
 502 void __devinit
 503 pcibios_update_irq (struct pci_dev *dev, int irq)
 504 {
 505         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 506
 507         /* ??? FIXME -- record old value for shutdown.  */
 508 }
 509
 510 static inline int
 511 pcibios_enable_resources (struct pci_dev *dev, int mask)
 512 {
 513         u16 cmd, old_cmd;
 514         int idx;
 515         struct resource *r;
 516         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 517
 518         if (!dev)
 519                 return -EINVAL;
 520
 521         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 522         old_cmd = cmd;
 523         for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
 524                 /* Only set up the desired resources.  */
 525                 if (!(mask & (1 << idx)))
 526                         continue;
 527
 528                 r = &dev->resource[idx];
 529                 if (!(r->flags & type_mask))
 530                         continue;
 531                 if ((idx == PCI_ROM_RESOURCE) &&
 532                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 533                         continue;
 534                 if (!r->start && r->end) {
 535                         printk(KERN_ERR
 536                                "PCI: Device %s not available because of resource collisions\n",
 537                                pci_name(dev));
 538                         return -EINVAL;
 539                 }
 540                 if (r->flags & IORESOURCE_IO)
 541                         cmd |= PCI_COMMAND_IO;
 542                 if (r->flags & IORESOURCE_MEM)
 543                         cmd |= PCI_COMMAND_MEMORY;
 544         }
 545         if (cmd != old_cmd) {
 546                 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
 547                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 548         }
 549         return 0;
 550 }
 551
 552 int
 553 pcibios_enable_device (struct pci_dev *dev, int mask)
 554 {
 555         int ret;
 556
 557         ret = pcibios_enable_resources(dev, mask);
 558         if (ret < 0)
 559                 return ret;
 560
 561         return acpi_pci_irq_enable(dev);
 562 }
 563
 564 void
 565 pcibios_disable_device (struct pci_dev *dev)
 566 {
 567         if (dev->is_enabled)
 568                 acpi_pci_irq_disable(dev);
 569 }
 570
 571 void
 572 pcibios_align_resource (void *data, struct resource *res,
 573                         resource_size_t size, resource_size_t align)
 574 {
 575 }
 576
 577 /*
 578  * PCI BIOS setup, always defaults to SAL interface
 579  */
 580 char * __init
 581 pcibios_setup (char *str)
 582 {
 583         return str;
 584 }
 585
 586 int
 587 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 588                      enum pci_mmap_state mmap_state, int write_combine)
 589 {
 590         /*
 591          * I/O space cannot be accessed via normal processor loads and
 592          * stores on this platform.
 593          */
 594         if (mmap_state == pci_mmap_io)
 595                 /*
 596                  * XXX we could relax this for I/O spaces for which ACPI
 597                  * indicates that the space is 1-to-1 mapped.  But at the
 598                  * moment, we don't support multiple PCI address spaces and
 599                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 600                  */
 601                 return -EINVAL;
 602
 603         /*
 604          * Leave vm_pgoff as-is, the PCI space address is the physical
 605          * address on this platform.
 606          */
 607         if (write_combine && efi_range_is_wc(vma->vm_start,
 608                                              vma->vm_end - vma->vm_start))
 609                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 610         else
 611                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 612
 613         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 614                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 615                 return -EAGAIN;
 616
 617         return 0;
 618 }
 619
 620 /**
 621  * ia64_pci_get_legacy_mem - generic legacy mem routine
 622  * @bus: bus to get legacy memory base address for
 623  *
 624  * Find the base of legacy memory for @bus.  This is typically the first
 625  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 626  * chipsets support legacy I/O and memory routing.  Returns the base address
 627  * or an error pointer if an error occurred.
 628  *
 629  * This is the ia64 generic version of this routine.  Other platforms
 630  * are free to override it with a machine vector.
 631  */
 632 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 633 {
 634         return (char *)__IA64_UNCACHED_OFFSET;
 635 }
 636
 637 /**
 638  * pci_mmap_legacy_page_range - map legacy memory space to userland
 639  * @bus: bus whose legacy space we're mapping
 640  * @vma: vma passed in by mmap
 641  *
 642  * Map legacy memory space for this device back to userspace using a machine
 643  * vector to get the base address.
 644  */
 645 int
 646 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
 647 {
 648         unsigned long size = vma->vm_end - vma->vm_start;
 649         pgprot_t prot;
 650         char *addr;
 651
 652         /*
 653          * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
 654          * for more details.
 655          */
 656         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 657                 return -EINVAL;
 658         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 659                                     vma->vm_page_prot);
 660         if (pgprot_val(prot) != pgprot_val(pgprot_noncached(vma->vm_page_prot)))
 661                 return -EINVAL;
 662
 663         addr = pci_get_legacy_mem(bus);
 664         if (IS_ERR(addr))
 665                 return PTR_ERR(addr);
 666
 667         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 668         vma->vm_page_prot = prot;
 669
 670         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 671                             size, vma->vm_page_prot))
 672                 return -EAGAIN;
 673
 674         return 0;
 675 }
 676
 677 /**
 678  * ia64_pci_legacy_read - read from legacy I/O space
 679  * @bus: bus to read
 680  * @port: legacy port value
 681  * @val: caller allocated storage for returned value
 682  * @size: number of bytes to read
 683  *
 684  * Simply reads @size bytes from @port and puts the result in @val.
 685  *
 686  * Again, this (and the write routine) are generic versions that can be
 687  * overridden by the platform.  This is necessary on platforms that don't
 688  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 689  */
 690 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 691 {
 692         int ret = size;
 693
 694         switch (size) {
 695         case 1:
 696                 *val = inb(port);
 697                 break;
 698         case 2:
 699                 *val = inw(port);
 700                 break;
 701         case 4:
 702                 *val = inl(port);
 703                 break;
 704         default:
 705                 ret = -EINVAL;
 706                 break;
 707         }
 708
 709         return ret;
 710 }
 711
 712 /**
 713  * ia64_pci_legacy_write - perform a legacy I/O write
 714  * @bus: bus pointer
 715  * @port: port to write
 716  * @val: value to write
 717  * @size: number of bytes to write from @val
 718  *
 719  * Simply writes @size bytes of @val to @port.
 720  */
 721 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 722 {
 723         int ret = size;
 724
 725         switch (size) {
 726         case 1:
 727                 outb(val, port);
 728                 break;
 729         case 2:
 730                 outw(val, port);
 731                 break;
 732         case 4:
 733                 outl(val, port);
 734                 break;
 735         default:
 736                 ret = -EINVAL;
 737                 break;
 738         }
 739
 740         return ret;
 741 }
 742
 743 /* It's defined in drivers/pci/pci.c */
 744 extern u8 pci_cache_line_size;
 745
 746 /**
 747  * set_pci_cacheline_size - determine cacheline size for PCI devices
 748  *
 749  * We want to use the line-size of the outer-most cache.  We assume
 750  * that this line-size is the same for all CPUs.
 751  *
 752  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 753  */
 754 static void __init set_pci_cacheline_size(void)
 755 {
 756         u64 levels, unique_caches;
 757         s64 status;
 758         pal_cache_config_info_t cci;
 759
 760         status = ia64_pal_cache_summary(&levels, &unique_caches);
 761         if (status != 0) {
 762                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
 763                         "(status=%ld)\n", __FUNCTION__, status);
 764                 return;
 765         }
 766
 767         status = ia64_pal_cache_config_info(levels - 1,
 768                                 /* cache_type (data_or_unified)= */ 2, &cci);
 769         if (status != 0) {
 770                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
 771                         "(status=%ld)\n", __FUNCTION__, status);
 772                 return;
 773         }
 774         pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 775 }
 776
 777 static int __init pcibios_init(void)
 778 {
 779         set_pci_cacheline_size();
 780         return 0;
 781 }
 782
 783 subsys_initcall(pcibios_init);