arch/mips/emma2rh/common/irq.c

   1 /*
   2  *  arch/mips/emma2rh/common/irq.c
   3  *      This file is common irq dispatcher.
   4  *
   5  *  Copyright (C) NEC Electronics Corporation 2005-2006
   6  *
   7  *  This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
   8  *
   9  *      Copyright 2001 MontaVista Software Inc.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  */
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/irq.h>
  28 #include <linux/types.h>
  29
  30 #include <asm/i8259.h>
  31 #include <asm/system.h>
  32 #include <asm/mipsregs.h>
  33 #include <asm/debug.h>
  34 #include <asm/addrspace.h>
  35 #include <asm/bootinfo.h>
  36
  37 #include <asm/emma2rh/emma2rh.h>
  38
  39 /*
  40  * the first level int-handler will jump here if it is a emma2rh irq
  41  */
  42 asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
  43 {
  44         u32 intStatus;
  45         u32 bitmask;
  46         u32 i;
  47
  48         intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
  49             & emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);
  50
  51 #ifdef EMMA2RH_SW_CASCADE
  52         if (intStatus &
  53             (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
  54                 u32 swIntStatus;
  55                 swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
  56                     & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
  57                 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  58                         if (swIntStatus & bitmask) {
  59                                 do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
  60                                 return;
  61                         }
  62                 }
  63         }
  64 #endif
  65
  66         for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  67                 if (intStatus & bitmask) {
  68                         do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
  69                         return;
  70                 }
  71         }
  72
  73         intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
  74             & emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);
  75
  76 #ifdef EMMA2RH_GPIO_CASCADE
  77         if (intStatus &
  78             (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
  79                 u32 gpioIntStatus;
  80                 gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
  81                     & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
  82                 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
  83                         if (gpioIntStatus & bitmask) {
  84                                 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
  85                                 return;
  86                         }
  87                 }
  88         }
  89 #endif
  90
  91         for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
  92                 if (intStatus & bitmask) {
  93                         do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
  94                         return;
  95                 }
  96         }
  97
  98         intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
  99             & emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);
 100
 101         for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
 102                 if (intStatus & bitmask) {
 103                         do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
 104                         return;
 105                 }
 106         }
 107 }