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[PATCH] powerpc: Remove device_node addrs/n_addr
[linux-2.6.22.y-op.git] / drivers / serial / pmac_zilog.c
blobea24129eb6b9f50911c960524af4650dc023202a
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/tty.h>
48
49 #include <linux/tty_flip.h>
50 #include <linux/major.h>
51 #include <linux/string.h>
52 #include <linux/fcntl.h>
53 #include <linux/mm.h>
54 #include <linux/kernel.h>
55 #include <linux/delay.h>
56 #include <linux/init.h>
57 #include <linux/console.h>
58 #include <linux/slab.h>
59 #include <linux/adb.h>
60 #include <linux/pmu.h>
61 #include <linux/bitops.h>
62 #include <linux/sysrq.h>
63 #include <asm/sections.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66 #include <asm/prom.h>
67 #include <asm/machdep.h>
68 #include <asm/pmac_feature.h>
69 #include <asm/dbdma.h>
70 #include <asm/macio.h>
71 #include <asm/semaphore.h>
72
73 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
74 #define SUPPORT_SYSRQ
75 #endif
76
77 #include <linux/serial.h>
78 #include <linux/serial_core.h>
79
80 #include "pmac_zilog.h"
81
82 /* Not yet implemented */
83 #undef HAS_DBDMA
84
85 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
86 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
87 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
88 MODULE_LICENSE("GPL");
89
90 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
91
92
93 /*
94 * For the sake of early serial console, we can do a pre-probe
95 * (optional) of the ports at rather early boot time.
96 */
97 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
98 static int pmz_ports_count;
99 static DECLARE_MUTEX(pmz_irq_sem);
100
101 static struct uart_driver pmz_uart_reg = {
102 .owner = THIS_MODULE,
103 .driver_name = "ttyS",
104 .devfs_name = "tts/",
105 .dev_name = "ttyS",
106 .major = TTY_MAJOR,
107 };
108
109
110 /*
111 * Load all registers to reprogram the port
112 * This function must only be called when the TX is not busy. The UART
113 * port lock must be held and local interrupts disabled.
114 */
115 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
116 {
117 int i;
118
119 if (ZS_IS_ASLEEP(uap))
120 return;
121
122 /* Let pending transmits finish. */
123 for (i = 0; i < 1000; i++) {
124 unsigned char stat = read_zsreg(uap, R1);
125 if (stat & ALL_SNT)
126 break;
127 udelay(100);
128 }
129
130 ZS_CLEARERR(uap);
131 zssync(uap);
132 ZS_CLEARFIFO(uap);
133 zssync(uap);
134 ZS_CLEARERR(uap);
135
136 /* Disable all interrupts. */
137 write_zsreg(uap, R1,
138 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
139
140 /* Set parity, sync config, stop bits, and clock divisor. */
141 write_zsreg(uap, R4, regs[R4]);
142
143 /* Set misc. TX/RX control bits. */
144 write_zsreg(uap, R10, regs[R10]);
145
146 /* Set TX/RX controls sans the enable bits. */
147 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
148 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
149
150 /* now set R7 "prime" on ESCC */
151 write_zsreg(uap, R15, regs[R15] | EN85C30);
152 write_zsreg(uap, R7, regs[R7P]);
153
154 /* make sure we use R7 "non-prime" on ESCC */
155 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
156
157 /* Synchronous mode config. */
158 write_zsreg(uap, R6, regs[R6]);
159 write_zsreg(uap, R7, regs[R7]);
160
161 /* Disable baud generator. */
162 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
163
164 /* Clock mode control. */
165 write_zsreg(uap, R11, regs[R11]);
166
167 /* Lower and upper byte of baud rate generator divisor. */
168 write_zsreg(uap, R12, regs[R12]);
169 write_zsreg(uap, R13, regs[R13]);
170
171 /* Now rewrite R14, with BRENAB (if set). */
172 write_zsreg(uap, R14, regs[R14]);
173
174 /* Reset external status interrupts. */
175 write_zsreg(uap, R0, RES_EXT_INT);
176 write_zsreg(uap, R0, RES_EXT_INT);
177
178 /* Rewrite R3/R5, this time without enables masked. */
179 write_zsreg(uap, R3, regs[R3]);
180 write_zsreg(uap, R5, regs[R5]);
181
182 /* Rewrite R1, this time without IRQ enabled masked. */
183 write_zsreg(uap, R1, regs[R1]);
184
185 /* Enable interrupts */
186 write_zsreg(uap, R9, regs[R9]);
187 }
188
189 /*
190 * We do like sunzilog to avoid disrupting pending Tx
191 * Reprogram the Zilog channel HW registers with the copies found in the
192 * software state struct. If the transmitter is busy, we defer this update
193 * until the next TX complete interrupt. Else, we do it right now.
194 *
195 * The UART port lock must be held and local interrupts disabled.
196 */
197 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
198 {
199 if (!ZS_REGS_HELD(uap)) {
200 if (ZS_TX_ACTIVE(uap)) {
201 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
202 } else {
203 pmz_debug("pmz: maybe_update_regs: updating\n");
204 pmz_load_zsregs(uap, uap->curregs);
205 }
206 }
207 }
208
209 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap,
210 struct pt_regs *regs)
211 {
212 struct tty_struct *tty = NULL;
213 unsigned char ch, r1, drop, error;
214 int loops = 0;
215
216 retry:
217 /* The interrupt can be enabled when the port isn't open, typically
218 * that happens when using one port is open and the other closed (stale
219 * interrupt) or when one port is used as a console.
220 */
221 if (!ZS_IS_OPEN(uap)) {
222 pmz_debug("pmz: draining input\n");
223 /* Port is closed, drain input data */
224 for (;;) {
225 if ((++loops) > 1000)
226 goto flood;
227 (void)read_zsreg(uap, R1);
228 write_zsreg(uap, R0, ERR_RES);
229 (void)read_zsdata(uap);
230 ch = read_zsreg(uap, R0);
231 if (!(ch & Rx_CH_AV))
232 break;
233 }
234 return NULL;
235 }
236
237 /* Sanity check, make sure the old bug is no longer happening */
238 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
239 WARN_ON(1);
240 (void)read_zsdata(uap);
241 return NULL;
242 }
243 tty = uap->port.info->tty;
244
245 while (1) {
246 error = 0;
247 drop = 0;
248
249 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
250 /* Have to drop the lock here */
251 pmz_debug("pmz: flip overflow\n");
252 spin_unlock(&uap->port.lock);
253 tty->flip.work.func((void *)tty);
254 spin_lock(&uap->port.lock);
255 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
256 drop = 1;
257 if (ZS_IS_ASLEEP(uap))
258 return NULL;
259 if (!ZS_IS_OPEN(uap))
260 goto retry;
261 }
262
263 r1 = read_zsreg(uap, R1);
264 ch = read_zsdata(uap);
265
266 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
267 write_zsreg(uap, R0, ERR_RES);
268 zssync(uap);
269 }
270
271 ch &= uap->parity_mask;
272 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
273 uap->flags &= ~PMACZILOG_FLAG_BREAK;
274 }
275
276 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
277 #ifdef USE_CTRL_O_SYSRQ
278 /* Handle the SysRq ^O Hack */
279 if (ch == '\x0f') {
280 uap->port.sysrq = jiffies + HZ*5;
281 goto next_char;
282 }
283 #endif /* USE_CTRL_O_SYSRQ */
284 if (uap->port.sysrq) {
285 int swallow;
286 spin_unlock(&uap->port.lock);
287 swallow = uart_handle_sysrq_char(&uap->port, ch, regs);
288 spin_lock(&uap->port.lock);
289 if (swallow)
290 goto next_char;
291 }
292 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
293
294 /* A real serial line, record the character and status. */
295 if (drop)
296 goto next_char;
297
298 *tty->flip.char_buf_ptr = ch;
299 *tty->flip.flag_buf_ptr = TTY_NORMAL;
300 uap->port.icount.rx++;
301
302 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
303 error = 1;
304 if (r1 & BRK_ABRT) {
305 pmz_debug("pmz: got break !\n");
306 r1 &= ~(PAR_ERR | CRC_ERR);
307 uap->port.icount.brk++;
308 if (uart_handle_break(&uap->port))
309 goto next_char;
310 }
311 else if (r1 & PAR_ERR)
312 uap->port.icount.parity++;
313 else if (r1 & CRC_ERR)
314 uap->port.icount.frame++;
315 if (r1 & Rx_OVR)
316 uap->port.icount.overrun++;
317 r1 &= uap->port.read_status_mask;
318 if (r1 & BRK_ABRT)
319 *tty->flip.flag_buf_ptr = TTY_BREAK;
320 else if (r1 & PAR_ERR)
321 *tty->flip.flag_buf_ptr = TTY_PARITY;
322 else if (r1 & CRC_ERR)
323 *tty->flip.flag_buf_ptr = TTY_FRAME;
324 }
325
326 if (uap->port.ignore_status_mask == 0xff ||
327 (r1 & uap->port.ignore_status_mask) == 0) {
328 tty->flip.flag_buf_ptr++;
329 tty->flip.char_buf_ptr++;
330 tty->flip.count++;
331 }
332 if ((r1 & Rx_OVR) &&
333 tty->flip.count < TTY_FLIPBUF_SIZE) {
334 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
335 tty->flip.flag_buf_ptr++;
336 tty->flip.char_buf_ptr++;
337 tty->flip.count++;
338 }
339 next_char:
340 /* We can get stuck in an infinite loop getting char 0 when the
341 * line is in a wrong HW state, we break that here.
342 * When that happens, I disable the receive side of the driver.
343 * Note that what I've been experiencing is a real irq loop where
344 * I'm getting flooded regardless of the actual port speed.
345 * Something stange is going on with the HW
346 */
347 if ((++loops) > 1000)
348 goto flood;
349 ch = read_zsreg(uap, R0);
350 if (!(ch & Rx_CH_AV))
351 break;
352 }
353
354 return tty;
355 flood:
356 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
357 write_zsreg(uap, R1, uap->curregs[R1]);
358 zssync(uap);
359 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
360 return tty;
361 }
362
363 static void pmz_status_handle(struct uart_pmac_port *uap, struct pt_regs *regs)
364 {
365 unsigned char status;
366
367 status = read_zsreg(uap, R0);
368 write_zsreg(uap, R0, RES_EXT_INT);
369 zssync(uap);
370
371 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
372 if (status & SYNC_HUNT)
373 uap->port.icount.dsr++;
374
375 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
376 * But it does not tell us which bit has changed, we have to keep
377 * track of this ourselves.
378 * The CTS input is inverted for some reason. -- paulus
379 */
380 if ((status ^ uap->prev_status) & DCD)
381 uart_handle_dcd_change(&uap->port,
382 (status & DCD));
383 if ((status ^ uap->prev_status) & CTS)
384 uart_handle_cts_change(&uap->port,
385 !(status & CTS));
386
387 wake_up_interruptible(&uap->port.info->delta_msr_wait);
388 }
389
390 if (status & BRK_ABRT)
391 uap->flags |= PMACZILOG_FLAG_BREAK;
392
393 uap->prev_status = status;
394 }
395
396 static void pmz_transmit_chars(struct uart_pmac_port *uap)
397 {
398 struct circ_buf *xmit;
399
400 if (ZS_IS_ASLEEP(uap))
401 return;
402 if (ZS_IS_CONS(uap)) {
403 unsigned char status = read_zsreg(uap, R0);
404
405 /* TX still busy? Just wait for the next TX done interrupt.
406 *
407 * It can occur because of how we do serial console writes. It would
408 * be nice to transmit console writes just like we normally would for
409 * a TTY line. (ie. buffered and TX interrupt driven). That is not
410 * easy because console writes cannot sleep. One solution might be
411 * to poll on enough port->xmit space becomming free. -DaveM
412 */
413 if (!(status & Tx_BUF_EMP))
414 return;
415 }
416
417 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
418
419 if (ZS_REGS_HELD(uap)) {
420 pmz_load_zsregs(uap, uap->curregs);
421 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
422 }
423
424 if (ZS_TX_STOPPED(uap)) {
425 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
426 goto ack_tx_int;
427 }
428
429 if (uap->port.x_char) {
430 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
431 write_zsdata(uap, uap->port.x_char);
432 zssync(uap);
433 uap->port.icount.tx++;
434 uap->port.x_char = 0;
435 return;
436 }
437
438 if (uap->port.info == NULL)
439 goto ack_tx_int;
440 xmit = &uap->port.info->xmit;
441 if (uart_circ_empty(xmit)) {
442 uart_write_wakeup(&uap->port);
443 goto ack_tx_int;
444 }
445 if (uart_tx_stopped(&uap->port))
446 goto ack_tx_int;
447
448 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
449 write_zsdata(uap, xmit->buf[xmit->tail]);
450 zssync(uap);
451
452 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
453 uap->port.icount.tx++;
454
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(&uap->port);
457
458 return;
459
460 ack_tx_int:
461 write_zsreg(uap, R0, RES_Tx_P);
462 zssync(uap);
463 }
464
465 /* Hrm... we register that twice, fixme later.... */
466 static irqreturn_t pmz_interrupt(int irq, void *dev_id, struct pt_regs *regs)
467 {
468 struct uart_pmac_port *uap = dev_id;
469 struct uart_pmac_port *uap_a;
470 struct uart_pmac_port *uap_b;
471 int rc = IRQ_NONE;
472 struct tty_struct *tty;
473 u8 r3;
474
475 uap_a = pmz_get_port_A(uap);
476 uap_b = uap_a->mate;
477
478 spin_lock(&uap_a->port.lock);
479 r3 = read_zsreg(uap_a, R3);
480
481 #ifdef DEBUG_HARD
482 pmz_debug("irq, r3: %x\n", r3);
483 #endif
484 /* Channel A */
485 tty = NULL;
486 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
487 write_zsreg(uap_a, R0, RES_H_IUS);
488 zssync(uap_a);
489 if (r3 & CHAEXT)
490 pmz_status_handle(uap_a, regs);
491 if (r3 & CHARxIP)
492 tty = pmz_receive_chars(uap_a, regs);
493 if (r3 & CHATxIP)
494 pmz_transmit_chars(uap_a);
495 rc = IRQ_HANDLED;
496 }
497 spin_unlock(&uap_a->port.lock);
498 if (tty != NULL)
499 tty_flip_buffer_push(tty);
500
501 if (uap_b->node == NULL)
502 goto out;
503
504 spin_lock(&uap_b->port.lock);
505 tty = NULL;
506 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
507 write_zsreg(uap_b, R0, RES_H_IUS);
508 zssync(uap_b);
509 if (r3 & CHBEXT)
510 pmz_status_handle(uap_b, regs);
511 if (r3 & CHBRxIP)
512 tty = pmz_receive_chars(uap_b, regs);
513 if (r3 & CHBTxIP)
514 pmz_transmit_chars(uap_b);
515 rc = IRQ_HANDLED;
516 }
517 spin_unlock(&uap_b->port.lock);
518 if (tty != NULL)
519 tty_flip_buffer_push(tty);
520
521 out:
522 #ifdef DEBUG_HARD
523 pmz_debug("irq done.\n");
524 #endif
525 return rc;
526 }
527
528 /*
529 * Peek the status register, lock not held by caller
530 */
531 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
532 {
533 unsigned long flags;
534 u8 status;
535
536 spin_lock_irqsave(&uap->port.lock, flags);
537 status = read_zsreg(uap, R0);
538 spin_unlock_irqrestore(&uap->port.lock, flags);
539
540 return status;
541 }
542
543 /*
544 * Check if transmitter is empty
545 * The port lock is not held.
546 */
547 static unsigned int pmz_tx_empty(struct uart_port *port)
548 {
549 struct uart_pmac_port *uap = to_pmz(port);
550 unsigned char status;
551
552 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
553 return TIOCSER_TEMT;
554
555 status = pmz_peek_status(to_pmz(port));
556 if (status & Tx_BUF_EMP)
557 return TIOCSER_TEMT;
558 return 0;
559 }
560
561 /*
562 * Set Modem Control (RTS & DTR) bits
563 * The port lock is held and interrupts are disabled.
564 * Note: Shall we really filter out RTS on external ports or
565 * should that be dealt at higher level only ?
566 */
567 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
568 {
569 struct uart_pmac_port *uap = to_pmz(port);
570 unsigned char set_bits, clear_bits;
571
572 /* Do nothing for irda for now... */
573 if (ZS_IS_IRDA(uap))
574 return;
575 /* We get called during boot with a port not up yet */
576 if (ZS_IS_ASLEEP(uap) ||
577 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
578 return;
579
580 set_bits = clear_bits = 0;
581
582 if (ZS_IS_INTMODEM(uap)) {
583 if (mctrl & TIOCM_RTS)
584 set_bits |= RTS;
585 else
586 clear_bits |= RTS;
587 }
588 if (mctrl & TIOCM_DTR)
589 set_bits |= DTR;
590 else
591 clear_bits |= DTR;
592
593 /* NOTE: Not subject to 'transmitter active' rule. */
594 uap->curregs[R5] |= set_bits;
595 uap->curregs[R5] &= ~clear_bits;
596 if (ZS_IS_ASLEEP(uap))
597 return;
598 write_zsreg(uap, R5, uap->curregs[R5]);
599 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
600 set_bits, clear_bits, uap->curregs[R5]);
601 zssync(uap);
602 }
603
604 /*
605 * Get Modem Control bits (only the input ones, the core will
606 * or that with a cached value of the control ones)
607 * The port lock is held and interrupts are disabled.
608 */
609 static unsigned int pmz_get_mctrl(struct uart_port *port)
610 {
611 struct uart_pmac_port *uap = to_pmz(port);
612 unsigned char status;
613 unsigned int ret;
614
615 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
616 return 0;
617
618 status = read_zsreg(uap, R0);
619
620 ret = 0;
621 if (status & DCD)
622 ret |= TIOCM_CAR;
623 if (status & SYNC_HUNT)
624 ret |= TIOCM_DSR;
625 if (!(status & CTS))
626 ret |= TIOCM_CTS;
627
628 return ret;
629 }
630
631 /*
632 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
633 * though for DMA, we will have to do a bit more.
634 * The port lock is held and interrupts are disabled.
635 */
636 static void pmz_stop_tx(struct uart_port *port)
637 {
638 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
639 }
640
641 /*
642 * Kick the Tx side.
643 * The port lock is held and interrupts are disabled.
644 */
645 static void pmz_start_tx(struct uart_port *port)
646 {
647 struct uart_pmac_port *uap = to_pmz(port);
648 unsigned char status;
649
650 pmz_debug("pmz: start_tx()\n");
651
652 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
653 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
654
655 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
656 return;
657
658 status = read_zsreg(uap, R0);
659
660 /* TX busy? Just wait for the TX done interrupt. */
661 if (!(status & Tx_BUF_EMP))
662 return;
663
664 /* Send the first character to jump-start the TX done
665 * IRQ sending engine.
666 */
667 if (port->x_char) {
668 write_zsdata(uap, port->x_char);
669 zssync(uap);
670 port->icount.tx++;
671 port->x_char = 0;
672 } else {
673 struct circ_buf *xmit = &port->info->xmit;
674
675 write_zsdata(uap, xmit->buf[xmit->tail]);
676 zssync(uap);
677 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
678 port->icount.tx++;
679
680 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
681 uart_write_wakeup(&uap->port);
682 }
683 pmz_debug("pmz: start_tx() done.\n");
684 }
685
686 /*
687 * Stop Rx side, basically disable emitting of
688 * Rx interrupts on the port. We don't disable the rx
689 * side of the chip proper though
690 * The port lock is held.
691 */
692 static void pmz_stop_rx(struct uart_port *port)
693 {
694 struct uart_pmac_port *uap = to_pmz(port);
695
696 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
697 return;
698
699 pmz_debug("pmz: stop_rx()()\n");
700
701 /* Disable all RX interrupts. */
702 uap->curregs[R1] &= ~RxINT_MASK;
703 pmz_maybe_update_regs(uap);
704
705 pmz_debug("pmz: stop_rx() done.\n");
706 }
707
708 /*
709 * Enable modem status change interrupts
710 * The port lock is held.
711 */
712 static void pmz_enable_ms(struct uart_port *port)
713 {
714 struct uart_pmac_port *uap = to_pmz(port);
715 unsigned char new_reg;
716
717 if (ZS_IS_IRDA(uap) || uap->node == NULL)
718 return;
719 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
720 if (new_reg != uap->curregs[R15]) {
721 uap->curregs[R15] = new_reg;
722
723 if (ZS_IS_ASLEEP(uap))
724 return;
725 /* NOTE: Not subject to 'transmitter active' rule. */
726 write_zsreg(uap, R15, uap->curregs[R15]);
727 }
728 }
729
730 /*
731 * Control break state emission
732 * The port lock is not held.
733 */
734 static void pmz_break_ctl(struct uart_port *port, int break_state)
735 {
736 struct uart_pmac_port *uap = to_pmz(port);
737 unsigned char set_bits, clear_bits, new_reg;
738 unsigned long flags;
739
740 if (uap->node == NULL)
741 return;
742 set_bits = clear_bits = 0;
743
744 if (break_state)
745 set_bits |= SND_BRK;
746 else
747 clear_bits |= SND_BRK;
748
749 spin_lock_irqsave(&port->lock, flags);
750
751 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
752 if (new_reg != uap->curregs[R5]) {
753 uap->curregs[R5] = new_reg;
754
755 /* NOTE: Not subject to 'transmitter active' rule. */
756 if (ZS_IS_ASLEEP(uap))
757 return;
758 write_zsreg(uap, R5, uap->curregs[R5]);
759 }
760
761 spin_unlock_irqrestore(&port->lock, flags);
762 }
763
764 /*
765 * Turn power on or off to the SCC and associated stuff
766 * (port drivers, modem, IR port, etc.)
767 * Returns the number of milliseconds we should wait before
768 * trying to use the port.
769 */
770 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
771 {
772 int delay = 0;
773 int rc;
774
775 if (state) {
776 rc = pmac_call_feature(
777 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
778 pmz_debug("port power on result: %d\n", rc);
779 if (ZS_IS_INTMODEM(uap)) {
780 rc = pmac_call_feature(
781 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
782 delay = 2500; /* wait for 2.5s before using */
783 pmz_debug("modem power result: %d\n", rc);
784 }
785 } else {
786 /* TODO: Make that depend on a timer, don't power down
787 * immediately
788 */
789 if (ZS_IS_INTMODEM(uap)) {
790 rc = pmac_call_feature(
791 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
792 pmz_debug("port power off result: %d\n", rc);
793 }
794 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
795 }
796 return delay;
797 }
798
799 /*
800 * FixZeroBug....Works around a bug in the SCC receving channel.
801 * Inspired from Darwin code, 15 Sept. 2000 -DanM
802 *
803 * The following sequence prevents a problem that is seen with O'Hare ASICs
804 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
805 * at the input to the receiver becomes 'stuck' and locks up the receiver.
806 * This problem can occur as a result of a zero bit at the receiver input
807 * coincident with any of the following events:
808 *
809 * The SCC is initialized (hardware or software).
810 * A framing error is detected.
811 * The clocking option changes from synchronous or X1 asynchronous
812 * clocking to X16, X32, or X64 asynchronous clocking.
813 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
814 *
815 * This workaround attempts to recover from the lockup condition by placing
816 * the SCC in synchronous loopback mode with a fast clock before programming
817 * any of the asynchronous modes.
818 */
819 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
820 {
821 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
822 zssync(uap);
823 udelay(10);
824 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
825 zssync(uap);
826
827 write_zsreg(uap, 4, X1CLK | MONSYNC);
828 write_zsreg(uap, 3, Rx8);
829 write_zsreg(uap, 5, Tx8 | RTS);
830 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
831 write_zsreg(uap, 11, RCBR | TCBR);
832 write_zsreg(uap, 12, 0);
833 write_zsreg(uap, 13, 0);
834 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
835 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
836 write_zsreg(uap, 3, Rx8 | RxENABLE);
837 write_zsreg(uap, 0, RES_EXT_INT);
838 write_zsreg(uap, 0, RES_EXT_INT);
839 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
840
841 /* The channel should be OK now, but it is probably receiving
842 * loopback garbage.
843 * Switch to asynchronous mode, disable the receiver,
844 * and discard everything in the receive buffer.
845 */
846 write_zsreg(uap, 9, NV);
847 write_zsreg(uap, 4, X16CLK | SB_MASK);
848 write_zsreg(uap, 3, Rx8);
849
850 while (read_zsreg(uap, 0) & Rx_CH_AV) {
851 (void)read_zsreg(uap, 8);
852 write_zsreg(uap, 0, RES_EXT_INT);
853 write_zsreg(uap, 0, ERR_RES);
854 }
855 }
856
857 /*
858 * Real startup routine, powers up the hardware and sets up
859 * the SCC. Returns a delay in ms where you need to wait before
860 * actually using the port, this is typically the internal modem
861 * powerup delay. This routine expect the lock to be taken.
862 */
863 static int __pmz_startup(struct uart_pmac_port *uap)
864 {
865 int pwr_delay = 0;
866
867 memset(&uap->curregs, 0, sizeof(uap->curregs));
868
869 /* Power up the SCC & underlying hardware (modem/irda) */
870 pwr_delay = pmz_set_scc_power(uap, 1);
871
872 /* Nice buggy HW ... */
873 pmz_fix_zero_bug_scc(uap);
874
875 /* Reset the channel */
876 uap->curregs[R9] = 0;
877 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
878 zssync(uap);
879 udelay(10);
880 write_zsreg(uap, 9, 0);
881 zssync(uap);
882
883 /* Clear the interrupt registers */
884 write_zsreg(uap, R1, 0);
885 write_zsreg(uap, R0, ERR_RES);
886 write_zsreg(uap, R0, ERR_RES);
887 write_zsreg(uap, R0, RES_H_IUS);
888 write_zsreg(uap, R0, RES_H_IUS);
889
890 /* Setup some valid baud rate */
891 uap->curregs[R4] = X16CLK | SB1;
892 uap->curregs[R3] = Rx8;
893 uap->curregs[R5] = Tx8 | RTS;
894 if (!ZS_IS_IRDA(uap))
895 uap->curregs[R5] |= DTR;
896 uap->curregs[R12] = 0;
897 uap->curregs[R13] = 0;
898 uap->curregs[R14] = BRENAB;
899
900 /* Clear handshaking, enable BREAK interrupts */
901 uap->curregs[R15] = BRKIE;
902
903 /* Master interrupt enable */
904 uap->curregs[R9] |= NV | MIE;
905
906 pmz_load_zsregs(uap, uap->curregs);
907
908 /* Enable receiver and transmitter. */
909 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
910 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
911
912 /* Remember status for DCD/CTS changes */
913 uap->prev_status = read_zsreg(uap, R0);
914
915
916 return pwr_delay;
917 }
918
919 static void pmz_irda_reset(struct uart_pmac_port *uap)
920 {
921 uap->curregs[R5] |= DTR;
922 write_zsreg(uap, R5, uap->curregs[R5]);
923 zssync(uap);
924 mdelay(110);
925 uap->curregs[R5] &= ~DTR;
926 write_zsreg(uap, R5, uap->curregs[R5]);
927 zssync(uap);
928 mdelay(10);
929 }
930
931 /*
932 * This is the "normal" startup routine, using the above one
933 * wrapped with the lock and doing a schedule delay
934 */
935 static int pmz_startup(struct uart_port *port)
936 {
937 struct uart_pmac_port *uap = to_pmz(port);
938 unsigned long flags;
939 int pwr_delay = 0;
940
941 pmz_debug("pmz: startup()\n");
942
943 if (ZS_IS_ASLEEP(uap))
944 return -EAGAIN;
945 if (uap->node == NULL)
946 return -ENODEV;
947
948 down(&pmz_irq_sem);
949
950 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
951
952 /* A console is never powered down. Else, power up and
953 * initialize the chip
954 */
955 if (!ZS_IS_CONS(uap)) {
956 spin_lock_irqsave(&port->lock, flags);
957 pwr_delay = __pmz_startup(uap);
958 spin_unlock_irqrestore(&port->lock, flags);
959 }
960
961 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
962 if (request_irq(uap->port.irq, pmz_interrupt, SA_SHIRQ, "PowerMac Zilog", uap)) {
963 dev_err(&uap->dev->ofdev.dev,
964 "Unable to register zs interrupt handler.\n");
965 pmz_set_scc_power(uap, 0);
966 up(&pmz_irq_sem);
967 return -ENXIO;
968 }
969
970 up(&pmz_irq_sem);
971
972 /* Right now, we deal with delay by blocking here, I'll be
973 * smarter later on
974 */
975 if (pwr_delay != 0) {
976 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
977 msleep(pwr_delay);
978 }
979
980 /* IrDA reset is done now */
981 if (ZS_IS_IRDA(uap))
982 pmz_irda_reset(uap);
983
984 /* Enable interrupts emission from the chip */
985 spin_lock_irqsave(&port->lock, flags);
986 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
987 if (!ZS_IS_EXTCLK(uap))
988 uap->curregs[R1] |= EXT_INT_ENAB;
989 write_zsreg(uap, R1, uap->curregs[R1]);
990 spin_unlock_irqrestore(&port->lock, flags);
991
992 pmz_debug("pmz: startup() done.\n");
993
994 return 0;
995 }
996
997 static void pmz_shutdown(struct uart_port *port)
998 {
999 struct uart_pmac_port *uap = to_pmz(port);
1000 unsigned long flags;
1001
1002 pmz_debug("pmz: shutdown()\n");
1003
1004 if (uap->node == NULL)
1005 return;
1006
1007 down(&pmz_irq_sem);
1008
1009 /* Release interrupt handler */
1010 free_irq(uap->port.irq, uap);
1011
1012 spin_lock_irqsave(&port->lock, flags);
1013
1014 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1015
1016 if (!ZS_IS_OPEN(uap->mate))
1017 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1018
1019 /* Disable interrupts */
1020 if (!ZS_IS_ASLEEP(uap)) {
1021 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1022 write_zsreg(uap, R1, uap->curregs[R1]);
1023 zssync(uap);
1024 }
1025
1026 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1027 spin_unlock_irqrestore(&port->lock, flags);
1028 up(&pmz_irq_sem);
1029 return;
1030 }
1031
1032 /* Disable receiver and transmitter. */
1033 uap->curregs[R3] &= ~RxENABLE;
1034 uap->curregs[R5] &= ~TxENABLE;
1035
1036 /* Disable all interrupts and BRK assertion. */
1037 uap->curregs[R5] &= ~SND_BRK;
1038 pmz_maybe_update_regs(uap);
1039
1040 /* Shut the chip down */
1041 pmz_set_scc_power(uap, 0);
1042
1043 spin_unlock_irqrestore(&port->lock, flags);
1044
1045 up(&pmz_irq_sem);
1046
1047 pmz_debug("pmz: shutdown() done.\n");
1048 }
1049
1050 /* Shared by TTY driver and serial console setup. The port lock is held
1051 * and local interrupts are disabled.
1052 */
1053 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1054 unsigned int iflag, unsigned long baud)
1055 {
1056 int brg;
1057
1058
1059 /* Switch to external clocking for IrDA high clock rates. That
1060 * code could be re-used for Midi interfaces with different
1061 * multipliers
1062 */
1063 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1064 uap->curregs[R4] = X1CLK;
1065 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1066 uap->curregs[R14] = 0; /* BRG off */
1067 uap->curregs[R12] = 0;
1068 uap->curregs[R13] = 0;
1069 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1070 } else {
1071 switch (baud) {
1072 case ZS_CLOCK/16: /* 230400 */
1073 uap->curregs[R4] = X16CLK;
1074 uap->curregs[R11] = 0;
1075 uap->curregs[R14] = 0;
1076 break;
1077 case ZS_CLOCK/32: /* 115200 */
1078 uap->curregs[R4] = X32CLK;
1079 uap->curregs[R11] = 0;
1080 uap->curregs[R14] = 0;
1081 break;
1082 default:
1083 uap->curregs[R4] = X16CLK;
1084 uap->curregs[R11] = TCBR | RCBR;
1085 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1086 uap->curregs[R12] = (brg & 255);
1087 uap->curregs[R13] = ((brg >> 8) & 255);
1088 uap->curregs[R14] = BRENAB;
1089 }
1090 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1091 }
1092
1093 /* Character size, stop bits, and parity. */
1094 uap->curregs[3] &= ~RxN_MASK;
1095 uap->curregs[5] &= ~TxN_MASK;
1096
1097 switch (cflag & CSIZE) {
1098 case CS5:
1099 uap->curregs[3] |= Rx5;
1100 uap->curregs[5] |= Tx5;
1101 uap->parity_mask = 0x1f;
1102 break;
1103 case CS6:
1104 uap->curregs[3] |= Rx6;
1105 uap->curregs[5] |= Tx6;
1106 uap->parity_mask = 0x3f;
1107 break;
1108 case CS7:
1109 uap->curregs[3] |= Rx7;
1110 uap->curregs[5] |= Tx7;
1111 uap->parity_mask = 0x7f;
1112 break;
1113 case CS8:
1114 default:
1115 uap->curregs[3] |= Rx8;
1116 uap->curregs[5] |= Tx8;
1117 uap->parity_mask = 0xff;
1118 break;
1119 };
1120 uap->curregs[4] &= ~(SB_MASK);
1121 if (cflag & CSTOPB)
1122 uap->curregs[4] |= SB2;
1123 else
1124 uap->curregs[4] |= SB1;
1125 if (cflag & PARENB)
1126 uap->curregs[4] |= PAR_ENAB;
1127 else
1128 uap->curregs[4] &= ~PAR_ENAB;
1129 if (!(cflag & PARODD))
1130 uap->curregs[4] |= PAR_EVEN;
1131 else
1132 uap->curregs[4] &= ~PAR_EVEN;
1133
1134 uap->port.read_status_mask = Rx_OVR;
1135 if (iflag & INPCK)
1136 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1137 if (iflag & (BRKINT | PARMRK))
1138 uap->port.read_status_mask |= BRK_ABRT;
1139
1140 uap->port.ignore_status_mask = 0;
1141 if (iflag & IGNPAR)
1142 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1143 if (iflag & IGNBRK) {
1144 uap->port.ignore_status_mask |= BRK_ABRT;
1145 if (iflag & IGNPAR)
1146 uap->port.ignore_status_mask |= Rx_OVR;
1147 }
1148
1149 if ((cflag & CREAD) == 0)
1150 uap->port.ignore_status_mask = 0xff;
1151 }
1152
1153
1154 /*
1155 * Set the irda codec on the imac to the specified baud rate.
1156 */
1157 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1158 {
1159 u8 cmdbyte;
1160 int t, version;
1161
1162 switch (*baud) {
1163 /* SIR modes */
1164 case 2400:
1165 cmdbyte = 0x53;
1166 break;
1167 case 4800:
1168 cmdbyte = 0x52;
1169 break;
1170 case 9600:
1171 cmdbyte = 0x51;
1172 break;
1173 case 19200:
1174 cmdbyte = 0x50;
1175 break;
1176 case 38400:
1177 cmdbyte = 0x4f;
1178 break;
1179 case 57600:
1180 cmdbyte = 0x4e;
1181 break;
1182 case 115200:
1183 cmdbyte = 0x4d;
1184 break;
1185 /* The FIR modes aren't really supported at this point, how
1186 * do we select the speed ? via the FCR on KeyLargo ?
1187 */
1188 case 1152000:
1189 cmdbyte = 0;
1190 break;
1191 case 4000000:
1192 cmdbyte = 0;
1193 break;
1194 default: /* 9600 */
1195 cmdbyte = 0x51;
1196 *baud = 9600;
1197 break;
1198 }
1199
1200 /* Wait for transmitter to drain */
1201 t = 10000;
1202 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1203 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1204 if (--t <= 0) {
1205 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1206 return;
1207 }
1208 udelay(10);
1209 }
1210
1211 /* Drain the receiver too */
1212 t = 100;
1213 (void)read_zsdata(uap);
1214 (void)read_zsdata(uap);
1215 (void)read_zsdata(uap);
1216 mdelay(10);
1217 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1218 read_zsdata(uap);
1219 mdelay(10);
1220 if (--t <= 0) {
1221 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1222 return;
1223 }
1224 }
1225
1226 /* Switch to command mode */
1227 uap->curregs[R5] |= DTR;
1228 write_zsreg(uap, R5, uap->curregs[R5]);
1229 zssync(uap);
1230 mdelay(1);
1231
1232 /* Switch SCC to 19200 */
1233 pmz_convert_to_zs(uap, CS8, 0, 19200);
1234 pmz_load_zsregs(uap, uap->curregs);
1235 mdelay(1);
1236
1237 /* Write get_version command byte */
1238 write_zsdata(uap, 1);
1239 t = 5000;
1240 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1241 if (--t <= 0) {
1242 dev_err(&uap->dev->ofdev.dev,
1243 "irda_setup timed out on get_version byte\n");
1244 goto out;
1245 }
1246 udelay(10);
1247 }
1248 version = read_zsdata(uap);
1249
1250 if (version < 4) {
1251 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1252 version);
1253 goto out;
1254 }
1255
1256 /* Send speed mode */
1257 write_zsdata(uap, cmdbyte);
1258 t = 5000;
1259 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1260 if (--t <= 0) {
1261 dev_err(&uap->dev->ofdev.dev,
1262 "irda_setup timed out on speed mode byte\n");
1263 goto out;
1264 }
1265 udelay(10);
1266 }
1267 t = read_zsdata(uap);
1268 if (t != cmdbyte)
1269 dev_err(&uap->dev->ofdev.dev,
1270 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1271
1272 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1273 *baud, version);
1274
1275 (void)read_zsdata(uap);
1276 (void)read_zsdata(uap);
1277 (void)read_zsdata(uap);
1278
1279 out:
1280 /* Switch back to data mode */
1281 uap->curregs[R5] &= ~DTR;
1282 write_zsreg(uap, R5, uap->curregs[R5]);
1283 zssync(uap);
1284
1285 (void)read_zsdata(uap);
1286 (void)read_zsdata(uap);
1287 (void)read_zsdata(uap);
1288 }
1289
1290
1291 static void __pmz_set_termios(struct uart_port *port, struct termios *termios,
1292 struct termios *old)
1293 {
1294 struct uart_pmac_port *uap = to_pmz(port);
1295 unsigned long baud;
1296
1297 pmz_debug("pmz: set_termios()\n");
1298
1299 if (ZS_IS_ASLEEP(uap))
1300 return;
1301
1302 memcpy(&uap->termios_cache, termios, sizeof(struct termios));
1303
1304 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1305 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1306 * about the FIR mode and high speed modes. So these are unused. For
1307 * implementing proper support for these, we should probably add some
1308 * DMA as well, at least on the Rx side, which isn't a simple thing
1309 * at this point.
1310 */
1311 if (ZS_IS_IRDA(uap)) {
1312 /* Calc baud rate */
1313 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1314 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1315 /* Cet the irda codec to the right rate */
1316 pmz_irda_setup(uap, &baud);
1317 /* Set final baud rate */
1318 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1319 pmz_load_zsregs(uap, uap->curregs);
1320 zssync(uap);
1321 } else {
1322 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1323 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1324 /* Make sure modem status interrupts are correctly configured */
1325 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1326 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1327 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1328 } else {
1329 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1330 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1331 }
1332
1333 /* Load registers to the chip */
1334 pmz_maybe_update_regs(uap);
1335 }
1336 uart_update_timeout(port, termios->c_cflag, baud);
1337
1338 pmz_debug("pmz: set_termios() done.\n");
1339 }
1340
1341 /* The port lock is not held. */
1342 static void pmz_set_termios(struct uart_port *port, struct termios *termios,
1343 struct termios *old)
1344 {
1345 struct uart_pmac_port *uap = to_pmz(port);
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&port->lock, flags);
1349
1350 /* Disable IRQs on the port */
1351 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1352 write_zsreg(uap, R1, uap->curregs[R1]);
1353
1354 /* Setup new port configuration */
1355 __pmz_set_termios(port, termios, old);
1356
1357 /* Re-enable IRQs on the port */
1358 if (ZS_IS_OPEN(uap)) {
1359 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1360 if (!ZS_IS_EXTCLK(uap))
1361 uap->curregs[R1] |= EXT_INT_ENAB;
1362 write_zsreg(uap, R1, uap->curregs[R1]);
1363 }
1364 spin_unlock_irqrestore(&port->lock, flags);
1365 }
1366
1367 static const char *pmz_type(struct uart_port *port)
1368 {
1369 struct uart_pmac_port *uap = to_pmz(port);
1370
1371 if (ZS_IS_IRDA(uap))
1372 return "Z85c30 ESCC - Infrared port";
1373 else if (ZS_IS_INTMODEM(uap))
1374 return "Z85c30 ESCC - Internal modem";
1375 return "Z85c30 ESCC - Serial port";
1376 }
1377
1378 /* We do not request/release mappings of the registers here, this
1379 * happens at early serial probe time.
1380 */
1381 static void pmz_release_port(struct uart_port *port)
1382 {
1383 }
1384
1385 static int pmz_request_port(struct uart_port *port)
1386 {
1387 return 0;
1388 }
1389
1390 /* These do not need to do anything interesting either. */
1391 static void pmz_config_port(struct uart_port *port, int flags)
1392 {
1393 }
1394
1395 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1396 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1397 {
1398 return -EINVAL;
1399 }
1400
1401 static struct uart_ops pmz_pops = {
1402 .tx_empty = pmz_tx_empty,
1403 .set_mctrl = pmz_set_mctrl,
1404 .get_mctrl = pmz_get_mctrl,
1405 .stop_tx = pmz_stop_tx,
1406 .start_tx = pmz_start_tx,
1407 .stop_rx = pmz_stop_rx,
1408 .enable_ms = pmz_enable_ms,
1409 .break_ctl = pmz_break_ctl,
1410 .startup = pmz_startup,
1411 .shutdown = pmz_shutdown,
1412 .set_termios = pmz_set_termios,
1413 .type = pmz_type,
1414 .release_port = pmz_release_port,
1415 .request_port = pmz_request_port,
1416 .config_port = pmz_config_port,
1417 .verify_port = pmz_verify_port,
1418 };
1419
1420 /*
1421 * Setup one port structure after probing, HW is down at this point,
1422 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1423 * register our console before uart_add_one_port() is called
1424 */
1425 static int __init pmz_init_port(struct uart_pmac_port *uap)
1426 {
1427 struct device_node *np = uap->node;
1428 char *conn;
1429 struct slot_names_prop {
1430 int count;
1431 char name[1];
1432 } *slots;
1433 int len;
1434 struct resource r_ports, r_rxdma, r_txdma;
1435
1436 /*
1437 * Request & map chip registers
1438 */
1439 if (of_address_to_resource(np, 0, &r_ports))
1440 return -ENODEV;
1441 uap->port.mapbase = r_ports.start;
1442 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1443
1444 uap->control_reg = uap->port.membase;
1445 uap->data_reg = uap->control_reg + 0x10;
1446
1447 /*
1448 * Request & map DBDMA registers
1449 */
1450 #ifdef HAS_DBDMA
1451 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1452 of_address_to_resource(np, 2, &r_rxdma) == 0)
1453 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1454 #else
1455 memset(&r_txdma, 0, sizeof(struct resource));
1456 memset(&r_rxdma, 0, sizeof(struct resource));
1457 #endif
1458 if (ZS_HAS_DMA(uap)) {
1459 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1460 if (uap->tx_dma_regs == NULL) {
1461 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1462 goto no_dma;
1463 }
1464 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1465 if (uap->rx_dma_regs == NULL) {
1466 iounmap(uap->tx_dma_regs);
1467 uap->tx_dma_regs = NULL;
1468 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1469 goto no_dma;
1470 }
1471 uap->tx_dma_irq = np->intrs[1].line;
1472 uap->rx_dma_irq = np->intrs[2].line;
1473 }
1474 no_dma:
1475
1476 /*
1477 * Detect port type
1478 */
1479 if (device_is_compatible(np, "cobalt"))
1480 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1481 conn = get_property(np, "AAPL,connector", &len);
1482 if (conn && (strcmp(conn, "infrared") == 0))
1483 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1484 uap->port_type = PMAC_SCC_ASYNC;
1485 /* 1999 Powerbook G3 has slot-names property instead */
1486 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
1487 if (slots && slots->count > 0) {
1488 if (strcmp(slots->name, "IrDA") == 0)
1489 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1490 else if (strcmp(slots->name, "Modem") == 0)
1491 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1492 }
1493 if (ZS_IS_IRDA(uap))
1494 uap->port_type = PMAC_SCC_IRDA;
1495 if (ZS_IS_INTMODEM(uap)) {
1496 struct device_node* i2c_modem = find_devices("i2c-modem");
1497 if (i2c_modem) {
1498 char* mid = get_property(i2c_modem, "modem-id", NULL);
1499 if (mid) switch(*mid) {
1500 case 0x04 :
1501 case 0x05 :
1502 case 0x07 :
1503 case 0x08 :
1504 case 0x0b :
1505 case 0x0c :
1506 uap->port_type = PMAC_SCC_I2S1;
1507 }
1508 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1509 mid ? (*mid) : 0);
1510 } else {
1511 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1512 }
1513 }
1514
1515 /*
1516 * Init remaining bits of "port" structure
1517 */
1518 uap->port.iotype = SERIAL_IO_MEM;
1519 uap->port.irq = np->intrs[0].line;
1520 uap->port.uartclk = ZS_CLOCK;
1521 uap->port.fifosize = 1;
1522 uap->port.ops = &pmz_pops;
1523 uap->port.type = PORT_PMAC_ZILOG;
1524 uap->port.flags = 0;
1525
1526 /* Setup some valid baud rate information in the register
1527 * shadows so we don't write crap there before baud rate is
1528 * first initialized.
1529 */
1530 pmz_convert_to_zs(uap, CS8, 0, 9600);
1531
1532 return 0;
1533 }
1534
1535 /*
1536 * Get rid of a port on module removal
1537 */
1538 static void pmz_dispose_port(struct uart_pmac_port *uap)
1539 {
1540 struct device_node *np;
1541
1542 np = uap->node;
1543 iounmap(uap->rx_dma_regs);
1544 iounmap(uap->tx_dma_regs);
1545 iounmap(uap->control_reg);
1546 uap->node = NULL;
1547 of_node_put(np);
1548 memset(uap, 0, sizeof(struct uart_pmac_port));
1549 }
1550
1551 /*
1552 * Called upon match with an escc node in the devive-tree.
1553 */
1554 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1555 {
1556 int i;
1557
1558 /* Iterate the pmz_ports array to find a matching entry
1559 */
1560 for (i = 0; i < MAX_ZS_PORTS; i++)
1561 if (pmz_ports[i].node == mdev->ofdev.node) {
1562 struct uart_pmac_port *uap = &pmz_ports[i];
1563
1564 uap->dev = mdev;
1565 dev_set_drvdata(&mdev->ofdev.dev, uap);
1566 if (macio_request_resources(uap->dev, "pmac_zilog"))
1567 printk(KERN_WARNING "%s: Failed to request resource"
1568 ", port still active\n",
1569 uap->node->name);
1570 else
1571 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1572 return 0;
1573 }
1574 return -ENODEV;
1575 }
1576
1577 /*
1578 * That one should not be called, macio isn't really a hotswap device,
1579 * we don't expect one of those serial ports to go away...
1580 */
1581 static int pmz_detach(struct macio_dev *mdev)
1582 {
1583 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1584
1585 if (!uap)
1586 return -ENODEV;
1587
1588 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1589 macio_release_resources(uap->dev);
1590 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1591 }
1592 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1593 uap->dev = NULL;
1594
1595 return 0;
1596 }
1597
1598
1599 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1600 {
1601 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1602 struct uart_state *state;
1603 unsigned long flags;
1604
1605 if (uap == NULL) {
1606 printk("HRM... pmz_suspend with NULL uap\n");
1607 return 0;
1608 }
1609
1610 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1611 return 0;
1612
1613 pmz_debug("suspend, switching to state %d\n", pm_state);
1614
1615 state = pmz_uart_reg.state + uap->port.line;
1616
1617 down(&pmz_irq_sem);
1618 down(&state->sem);
1619
1620 spin_lock_irqsave(&uap->port.lock, flags);
1621
1622 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1623 /* Disable receiver and transmitter. */
1624 uap->curregs[R3] &= ~RxENABLE;
1625 uap->curregs[R5] &= ~TxENABLE;
1626
1627 /* Disable all interrupts and BRK assertion. */
1628 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1629 uap->curregs[R5] &= ~SND_BRK;
1630 pmz_load_zsregs(uap, uap->curregs);
1631 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1632 mb();
1633 }
1634
1635 spin_unlock_irqrestore(&uap->port.lock, flags);
1636
1637 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1638 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1639 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1640 disable_irq(uap->port.irq);
1641 }
1642
1643 if (ZS_IS_CONS(uap))
1644 uap->port.cons->flags &= ~CON_ENABLED;
1645
1646 /* Shut the chip down */
1647 pmz_set_scc_power(uap, 0);
1648
1649 up(&state->sem);
1650 up(&pmz_irq_sem);
1651
1652 pmz_debug("suspend, switching complete\n");
1653
1654 mdev->ofdev.dev.power.power_state = pm_state;
1655
1656 return 0;
1657 }
1658
1659
1660 static int pmz_resume(struct macio_dev *mdev)
1661 {
1662 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1663 struct uart_state *state;
1664 unsigned long flags;
1665 int pwr_delay = 0;
1666
1667 if (uap == NULL)
1668 return 0;
1669
1670 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1671 return 0;
1672
1673 pmz_debug("resume, switching to state 0\n");
1674
1675 state = pmz_uart_reg.state + uap->port.line;
1676
1677 down(&pmz_irq_sem);
1678 down(&state->sem);
1679
1680 spin_lock_irqsave(&uap->port.lock, flags);
1681 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1682 spin_unlock_irqrestore(&uap->port.lock, flags);
1683 goto bail;
1684 }
1685 pwr_delay = __pmz_startup(uap);
1686
1687 /* Take care of config that may have changed while asleep */
1688 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1689
1690 if (ZS_IS_OPEN(uap)) {
1691 /* Enable interrupts */
1692 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1693 if (!ZS_IS_EXTCLK(uap))
1694 uap->curregs[R1] |= EXT_INT_ENAB;
1695 write_zsreg(uap, R1, uap->curregs[R1]);
1696 }
1697
1698 spin_unlock_irqrestore(&uap->port.lock, flags);
1699
1700 if (ZS_IS_CONS(uap))
1701 uap->port.cons->flags |= CON_ENABLED;
1702
1703 /* Re-enable IRQ on the controller */
1704 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1705 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1706 enable_irq(uap->port.irq);
1707 }
1708
1709 bail:
1710 up(&state->sem);
1711 up(&pmz_irq_sem);
1712
1713 /* Right now, we deal with delay by blocking here, I'll be
1714 * smarter later on
1715 */
1716 if (pwr_delay != 0) {
1717 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1718 msleep(pwr_delay);
1719 }
1720
1721 pmz_debug("resume, switching complete\n");
1722
1723 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1724
1725 return 0;
1726 }
1727
1728 /*
1729 * Probe all ports in the system and build the ports array, we register
1730 * with the serial layer at this point, the macio-type probing is only
1731 * used later to "attach" to the sysfs tree so we get power management
1732 * events
1733 */
1734 static int __init pmz_probe(void)
1735 {
1736 struct device_node *node_p, *node_a, *node_b, *np;
1737 int count = 0;
1738 int rc;
1739
1740 /*
1741 * Find all escc chips in the system
1742 */
1743 node_p = of_find_node_by_name(NULL, "escc");
1744 while (node_p) {
1745 /*
1746 * First get channel A/B node pointers
1747 *
1748 * TODO: Add routines with proper locking to do that...
1749 */
1750 node_a = node_b = NULL;
1751 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1752 if (strncmp(np->name, "ch-a", 4) == 0)
1753 node_a = of_node_get(np);
1754 else if (strncmp(np->name, "ch-b", 4) == 0)
1755 node_b = of_node_get(np);
1756 }
1757 if (!node_a && !node_b) {
1758 of_node_put(node_a);
1759 of_node_put(node_b);
1760 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1761 (!node_a) ? 'a' : 'b', node_p->full_name);
1762 goto next;
1763 }
1764
1765 /*
1766 * Fill basic fields in the port structures
1767 */
1768 pmz_ports[count].mate = &pmz_ports[count+1];
1769 pmz_ports[count+1].mate = &pmz_ports[count];
1770 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1771 pmz_ports[count].node = node_a;
1772 pmz_ports[count+1].node = node_b;
1773 pmz_ports[count].port.line = count;
1774 pmz_ports[count+1].port.line = count+1;
1775
1776 /*
1777 * Setup the ports for real
1778 */
1779 rc = pmz_init_port(&pmz_ports[count]);
1780 if (rc == 0 && node_b != NULL)
1781 rc = pmz_init_port(&pmz_ports[count+1]);
1782 if (rc != 0) {
1783 of_node_put(node_a);
1784 of_node_put(node_b);
1785 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1786 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1787 goto next;
1788 }
1789 count += 2;
1790 next:
1791 node_p = of_find_node_by_name(node_p, "escc");
1792 }
1793 pmz_ports_count = count;
1794
1795 return 0;
1796 }
1797
1798 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1799
1800 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1801 static int __init pmz_console_setup(struct console *co, char *options);
1802
1803 static struct console pmz_console = {
1804 .name = "ttyS",
1805 .write = pmz_console_write,
1806 .device = uart_console_device,
1807 .setup = pmz_console_setup,
1808 .flags = CON_PRINTBUFFER,
1809 .index = -1,
1810 .data = &pmz_uart_reg,
1811 };
1812
1813 #define PMACZILOG_CONSOLE &pmz_console
1814 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1815 #define PMACZILOG_CONSOLE (NULL)
1816 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1817
1818 /*
1819 * Register the driver, console driver and ports with the serial
1820 * core
1821 */
1822 static int __init pmz_register(void)
1823 {
1824 int i, rc;
1825
1826 pmz_uart_reg.nr = pmz_ports_count;
1827 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1828 pmz_uart_reg.minor = 64;
1829
1830 /*
1831 * Register this driver with the serial core
1832 */
1833 rc = uart_register_driver(&pmz_uart_reg);
1834 if (rc)
1835 return rc;
1836
1837 /*
1838 * Register each port with the serial core
1839 */
1840 for (i = 0; i < pmz_ports_count; i++) {
1841 struct uart_pmac_port *uport = &pmz_ports[i];
1842 /* NULL node may happen on wallstreet */
1843 if (uport->node != NULL)
1844 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1845 if (rc)
1846 goto err_out;
1847 }
1848
1849 return 0;
1850 err_out:
1851 while (i-- > 0) {
1852 struct uart_pmac_port *uport = &pmz_ports[i];
1853 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1854 }
1855 uart_unregister_driver(&pmz_uart_reg);
1856 return rc;
1857 }
1858
1859 static struct of_device_id pmz_match[] =
1860 {
1861 {
1862 .name = "ch-a",
1863 },
1864 {
1865 .name = "ch-b",
1866 },
1867 {},
1868 };
1869 MODULE_DEVICE_TABLE (of, pmz_match);
1870
1871 static struct macio_driver pmz_driver =
1872 {
1873 .name = "pmac_zilog",
1874 .match_table = pmz_match,
1875 .probe = pmz_attach,
1876 .remove = pmz_detach,
1877 .suspend = pmz_suspend,
1878 .resume = pmz_resume,
1879 };
1880
1881 static int __init init_pmz(void)
1882 {
1883 int rc, i;
1884 printk(KERN_INFO "%s\n", version);
1885
1886 /*
1887 * First, we need to do a direct OF-based probe pass. We
1888 * do that because we want serial console up before the
1889 * macio stuffs calls us back, and since that makes it
1890 * easier to pass the proper number of channels to
1891 * uart_register_driver()
1892 */
1893 if (pmz_ports_count == 0)
1894 pmz_probe();
1895
1896 /*
1897 * Bail early if no port found
1898 */
1899 if (pmz_ports_count == 0)
1900 return -ENODEV;
1901
1902 /*
1903 * Now we register with the serial layer
1904 */
1905 rc = pmz_register();
1906 if (rc) {
1907 printk(KERN_ERR
1908 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1909 "pmac_zilog: Did another serial driver already claim the minors?\n");
1910 /* effectively "pmz_unprobe()" */
1911 for (i=0; i < pmz_ports_count; i++)
1912 pmz_dispose_port(&pmz_ports[i]);
1913 return rc;
1914 }
1915
1916 /*
1917 * Then we register the macio driver itself
1918 */
1919 return macio_register_driver(&pmz_driver);
1920 }
1921
1922 static void __exit exit_pmz(void)
1923 {
1924 int i;
1925
1926 /* Get rid of macio-driver (detach from macio) */
1927 macio_unregister_driver(&pmz_driver);
1928
1929 for (i = 0; i < pmz_ports_count; i++) {
1930 struct uart_pmac_port *uport = &pmz_ports[i];
1931 if (uport->node != NULL) {
1932 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1933 pmz_dispose_port(uport);
1934 }
1935 }
1936 /* Unregister UART driver */
1937 uart_unregister_driver(&pmz_uart_reg);
1938 }
1939
1940 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1941
1942 /*
1943 * Print a string to the serial port trying not to disturb
1944 * any possible real use of the port...
1945 */
1946 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1947 {
1948 struct uart_pmac_port *uap = &pmz_ports[con->index];
1949 unsigned long flags;
1950 int i;
1951
1952 if (ZS_IS_ASLEEP(uap))
1953 return;
1954 spin_lock_irqsave(&uap->port.lock, flags);
1955
1956 /* Turn of interrupts and enable the transmitter. */
1957 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1958 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1959
1960 for (i = 0; i < count; i++) {
1961 /* Wait for the transmit buffer to empty. */
1962 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1963 udelay(5);
1964 write_zsdata(uap, s[i]);
1965 if (s[i] == 10) {
1966 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1967 udelay(5);
1968 write_zsdata(uap, R13);
1969 }
1970 }
1971
1972 /* Restore the values in the registers. */
1973 write_zsreg(uap, R1, uap->curregs[1]);
1974 /* Don't disable the transmitter. */
1975
1976 spin_unlock_irqrestore(&uap->port.lock, flags);
1977 }
1978
1979 /*
1980 * Setup the serial console
1981 */
1982 static int __init pmz_console_setup(struct console *co, char *options)
1983 {
1984 struct uart_pmac_port *uap;
1985 struct uart_port *port;
1986 int baud = 38400;
1987 int bits = 8;
1988 int parity = 'n';
1989 int flow = 'n';
1990 unsigned long pwr_delay;
1991
1992 /*
1993 * XServe's default to 57600 bps
1994 */
1995 if (machine_is_compatible("RackMac1,1")
1996 || machine_is_compatible("RackMac1,2")
1997 || machine_is_compatible("MacRISC4"))
1998 baud = 57600;
1999
2000 /*
2001 * Check whether an invalid uart number has been specified, and
2002 * if so, search for the first available port that does have
2003 * console support.
2004 */
2005 if (co->index >= pmz_ports_count)
2006 co->index = 0;
2007 uap = &pmz_ports[co->index];
2008 if (uap->node == NULL)
2009 return -ENODEV;
2010 port = &uap->port;
2011
2012 /*
2013 * Mark port as beeing a console
2014 */
2015 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2016
2017 /*
2018 * Temporary fix for uart layer who didn't setup the spinlock yet
2019 */
2020 spin_lock_init(&port->lock);
2021
2022 /*
2023 * Enable the hardware
2024 */
2025 pwr_delay = __pmz_startup(uap);
2026 if (pwr_delay)
2027 mdelay(pwr_delay);
2028
2029 if (options)
2030 uart_parse_options(options, &baud, &parity, &bits, &flow);
2031
2032 return uart_set_options(port, co, baud, parity, bits, flow);
2033 }
2034
2035 static int __init pmz_console_init(void)
2036 {
2037 /* Probe ports */
2038 pmz_probe();
2039
2040 /* TODO: Autoprobe console based on OF */
2041 /* pmz_console.index = i; */
2042 register_console(&pmz_console);
2043
2044 return 0;
2045
2046 }
2047 console_initcall(pmz_console_init);
2048 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2049
2050 module_init(init_pmz);
2051 module_exit(exit_pmz);
linux v2.6.22.y-op