drivers/net/tulip/tulip.h

   1 /*
   2         drivers/net/tulip/tulip.h
   3
   4         Copyright 2000,2001  The Linux Kernel Team
   5         Written/copyright 1994-2001 by Donald Becker.
   6
   7         This software may be used and distributed according to the terms
   8         of the GNU General Public License, incorporated herein by reference.
   9
  10         Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11         for more information on this driver, or visit the project
  12         Web page at http://sourceforge.net/projects/tulip/
  13
  14 */
  15
  16 #ifndef __NET_TULIP_H__
  17 #define __NET_TULIP_H__
  18
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/timer.h>
  24 #include <linux/delay.h>
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28
  29
  30 /* undefine, or define to various debugging levels (>4 == obscene levels) */
  31 #define TULIP_DEBUG 1
  32
  33 /* undefine USE_IO_OPS for MMIO, define for PIO */
  34 #ifdef CONFIG_TULIP_MMIO
  35 # undef USE_IO_OPS
  36 #else
  37 # define USE_IO_OPS 1
  38 #endif
  39
  40
  41
  42 struct tulip_chip_table {
  43         char *chip_name;
  44         int io_size;
  45         int valid_intrs;        /* CSR7 interrupt enable settings */
  46         int flags;
  47         void (*media_timer) (unsigned long data);
  48 };
  49
  50
  51 enum tbl_flag {
  52         HAS_MII                 = 0x0001,
  53         HAS_MEDIA_TABLE         = 0x0002,
  54         CSR12_IN_SROM           = 0x0004,
  55         ALWAYS_CHECK_MII        = 0x0008,
  56         HAS_ACPI                = 0x0010,
  57         MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  58         HAS_PNICNWAY            = 0x0080,
  59         HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  60         HAS_INTR_MITIGATION     = 0x0100,
  61         IS_ASIX                 = 0x0200,
  62         HAS_8023X               = 0x0400,
  63         COMET_MAC_ADDR          = 0x0800,
  64         HAS_PCI_MWI             = 0x1000,
  65         HAS_PHY_IRQ             = 0x2000,
  66         HAS_SWAPPED_SEEPROM     = 0x4000,
  67         NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  68 };
  69
  70
  71 /* chip types.  careful!  order is VERY IMPORTANT here, as these
  72  * are used throughout the driver as indices into arrays */
  73 /* Note 21142 == 21143. */
  74 enum chips {
  75         DC21040 = 0,
  76         DC21041 = 1,
  77         DC21140 = 2,
  78         DC21142 = 3, DC21143 = 3,
  79         LC82C168,
  80         MX98713,
  81         MX98715,
  82         MX98725,
  83         AX88140,
  84         PNIC2,
  85         COMET,
  86         COMPEX9881,
  87         I21145,
  88         DM910X,
  89         CONEXANT,
  90 };
  91
  92
  93 enum MediaIs {
  94         MediaIsFD = 1,
  95         MediaAlwaysFD = 2,
  96         MediaIsMII = 4,
  97         MediaIsFx = 8,
  98         MediaIs100 = 16
  99 };
 100
 101
 102 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
 103    must be longword instructions and quadword aligned. */
 104 enum tulip_offsets {
 105         CSR0 = 0,
 106         CSR1 = 0x08,
 107         CSR2 = 0x10,
 108         CSR3 = 0x18,
 109         CSR4 = 0x20,
 110         CSR5 = 0x28,
 111         CSR6 = 0x30,
 112         CSR7 = 0x38,
 113         CSR8 = 0x40,
 114         CSR9 = 0x48,
 115         CSR10 = 0x50,
 116         CSR11 = 0x58,
 117         CSR12 = 0x60,
 118         CSR13 = 0x68,
 119         CSR14 = 0x70,
 120         CSR15 = 0x78,
 121 };
 122
 123 /* register offset and bits for CFDD PCI config reg */
 124 enum pci_cfg_driver_reg {
 125         CFDD = 0x40,
 126         CFDD_Sleep = (1 << 31),
 127         CFDD_Snooze = (1 << 30),
 128 };
 129
 130 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 131
 132 /* The bits in the CSR5 status registers, mostly interrupt sources. */
 133 enum status_bits {
 134         TimerInt = 0x800,
 135         SytemError = 0x2000,
 136         TPLnkFail = 0x1000,
 137         TPLnkPass = 0x10,
 138         NormalIntr = 0x10000,
 139         AbnormalIntr = 0x8000,
 140         RxJabber = 0x200,
 141         RxDied = 0x100,
 142         RxNoBuf = 0x80,
 143         RxIntr = 0x40,
 144         TxFIFOUnderflow = 0x20,
 145         TxJabber = 0x08,
 146         TxNoBuf = 0x04,
 147         TxDied = 0x02,
 148         TxIntr = 0x01,
 149 };
 150
 151 /* bit mask for CSR5 TX/RX process state */
 152 #define CSR5_TS 0x00700000
 153 #define CSR5_RS 0x000e0000
 154
 155 enum tulip_mode_bits {
 156         TxThreshold             = (1 << 22),
 157         FullDuplex              = (1 << 9),
 158         TxOn                    = 0x2000,
 159         AcceptBroadcast         = 0x0100,
 160         AcceptAllMulticast      = 0x0080,
 161         AcceptAllPhys           = 0x0040,
 162         AcceptRunt              = 0x0008,
 163         RxOn                    = 0x0002,
 164         RxTx                    = (TxOn | RxOn),
 165 };
 166
 167
 168 enum tulip_busconfig_bits {
 169         MWI                     = (1 << 24),
 170         MRL                     = (1 << 23),
 171         MRM                     = (1 << 21),
 172         CALShift                = 14,
 173         BurstLenShift           = 8,
 174 };
 175
 176
 177 /* The Tulip Rx and Tx buffer descriptors. */
 178 struct tulip_rx_desc {
 179         s32 status;
 180         s32 length;
 181         u32 buffer1;
 182         u32 buffer2;
 183 };
 184
 185
 186 struct tulip_tx_desc {
 187         s32 status;
 188         s32 length;
 189         u32 buffer1;
 190         u32 buffer2;            /* We use only buffer 1.  */
 191 };
 192
 193
 194 enum desc_status_bits {
 195         DescOwned = 0x80000000,
 196         RxDescFatalErr = 0x8000,
 197         RxWholePkt = 0x0300,
 198 };
 199
 200
 201 enum t21143_csr6_bits {
 202         csr6_sc = (1<<31),
 203         csr6_ra = (1<<30),
 204         csr6_ign_dest_msb = (1<<26),
 205         csr6_mbo = (1<<25),
 206         csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 207         csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 208         csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 209         csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 210         csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 211         csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 212         csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 213         csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 214         csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 215
 216         /***************************************************************
 217          * This table shows transmit threshold values based on media   *
 218          * and these two registers (from PNIC1 & 2 docs) Note: this is *
 219          * all meaningless if sf is set.                               *
 220          ***************************************************************/
 221
 222         /***********************************
 223          * (trh,trl) * 100BaseTX * 10BaseT *
 224          ***********************************
 225          *   (0,0)   *     128   *    72   *
 226          *   (0,1)   *     256   *    96   *
 227          *   (1,0)   *     512   *   128   *
 228          *   (1,1)   *    1024   *   160   *
 229          ***********************************/
 230
 231         csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 232         csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 233         csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 234         /* set both and you get (PHY) loopback */
 235         csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 236         csr6_pm = (1<<7),    /* Pass All Multicast */
 237         csr6_pr = (1<<6),    /* Promiscuous mode */
 238         csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 239         csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 240         csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 241         csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 242         csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 243
 244         csr6_mask_capture = (csr6_sc | csr6_ca),
 245         csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 246         csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 247         csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 248         csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 249         csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 250         csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 251         csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 252 };
 253
 254
 255 /* Keep the ring sizes a power of two for efficiency.
 256    Making the Tx ring too large decreases the effectiveness of channel
 257    bonding and packet priority.
 258    There are no ill effects from too-large receive rings. */
 259
 260 #define TX_RING_SIZE    32
 261 #define RX_RING_SIZE    128
 262 #define MEDIA_MASK     31
 263
 264 #define PKT_BUF_SZ              1536    /* Size of each temporary Rx buffer. */
 265
 266 #define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 267
 268 #if defined(__sparc__) || defined(__hppa__)
 269 /* The UltraSparc PCI controllers will disconnect at every 64-byte
 270  * crossing anyways so it makes no sense to tell Tulip to burst
 271  * any more than that.
 272  */
 273 #define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 274 #else
 275 #define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 276 #endif
 277
 278
 279 /* Ring-wrap flag in length field, use for last ring entry.
 280         0x01000000 means chain on buffer2 address,
 281         0x02000000 means use the ring start address in CSR2/3.
 282    Note: Some work-alike chips do not function correctly in chained mode.
 283    The ASIX chip works only in chained mode.
 284    Thus we indicates ring mode, but always write the 'next' field for
 285    chained mode as well.
 286 */
 287 #define DESC_RING_WRAP 0x02000000
 288
 289
 290 #define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 291
 292
 293 #define RUN_AT(x) (jiffies + (x))
 294
 295 #if defined(__i386__)                   /* AKA get_unaligned() */
 296 #define get_u16(ptr) (*(u16 *)(ptr))
 297 #else
 298 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
 299 #endif
 300
 301 struct medialeaf {
 302         u8 type;
 303         u8 media;
 304         unsigned char *leafdata;
 305 };
 306
 307
 308 struct mediatable {
 309         u16 defaultmedia;
 310         u8 leafcount;
 311         u8 csr12dir;            /* General purpose pin directions. */
 312         unsigned has_mii:1;
 313         unsigned has_nonmii:1;
 314         unsigned has_reset:6;
 315         u32 csr15dir;
 316         u32 csr15val;           /* 21143 NWay setting. */
 317         struct medialeaf mleaf[0];
 318 };
 319
 320
 321 struct mediainfo {
 322         struct mediainfo *next;
 323         int info_type;
 324         int index;
 325         unsigned char *info;
 326 };
 327
 328 struct ring_info {
 329         struct sk_buff  *skb;
 330         dma_addr_t      mapping;
 331 };
 332
 333
 334 struct tulip_private {
 335         const char *product_name;
 336         struct net_device *next_module;
 337         struct tulip_rx_desc *rx_ring;
 338         struct tulip_tx_desc *tx_ring;
 339         dma_addr_t rx_ring_dma;
 340         dma_addr_t tx_ring_dma;
 341         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 342         struct ring_info tx_buffers[TX_RING_SIZE];
 343         /* The addresses of receive-in-place skbuffs. */
 344         struct ring_info rx_buffers[RX_RING_SIZE];
 345         u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 346         int chip_id;
 347         int revision;
 348         int flags;
 349         struct net_device_stats stats;
 350         struct timer_list timer;        /* Media selection timer. */
 351         struct timer_list oom_timer;    /* Out of memory timer. */
 352         u32 mc_filter[2];
 353         spinlock_t lock;
 354         spinlock_t mii_lock;
 355         unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 356         unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 357
 358 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 359         int mit_on;
 360 #endif
 361         unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 362         unsigned int full_duplex_lock:1;
 363         unsigned int fake_addr:1;       /* Multiport board faked address. */
 364         unsigned int default_port:4;    /* Last dev->if_port value. */
 365         unsigned int media2:4;  /* Secondary monitored media port. */
 366         unsigned int medialock:1;       /* Don't sense media type. */
 367         unsigned int mediasense:1;      /* Media sensing in progress. */
 368         unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 369         unsigned int csr0;      /* CSR0 setting. */
 370         unsigned int csr6;      /* Current CSR6 control settings. */
 371         unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 372         void (*link_change) (struct net_device * dev, int csr5);
 373         u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 374         u16 lpar;               /* 21143 Link partner ability. */
 375         u16 advertising[4];
 376         signed char phys[4], mii_cnt;   /* MII device addresses. */
 377         struct mediatable *mtable;
 378         int cur_index;          /* Current media index. */
 379         int saved_if_port;
 380         struct pci_dev *pdev;
 381         int ttimer;
 382         int susp_rx;
 383         unsigned long nir;
 384         void __iomem *base_addr;
 385         int csr12_shadow;
 386         int pad0;               /* Used for 8-byte alignment */
 387 };
 388
 389
 390 struct eeprom_fixup {
 391         char *name;
 392         unsigned char addr0;
 393         unsigned char addr1;
 394         unsigned char addr2;
 395         u16 newtable[32];       /* Max length below. */
 396 };
 397
 398
 399 /* 21142.c */
 400 extern u16 t21142_csr14[];
 401 void t21142_timer(unsigned long data);
 402 void t21142_start_nway(struct net_device *dev);
 403 void t21142_lnk_change(struct net_device *dev, int csr5);
 404
 405
 406 /* PNIC2.c */
 407 void pnic2_lnk_change(struct net_device *dev, int csr5);
 408 void pnic2_timer(unsigned long data);
 409 void pnic2_start_nway(struct net_device *dev);
 410 void pnic2_lnk_change(struct net_device *dev, int csr5);
 411
 412 /* eeprom.c */
 413 void tulip_parse_eeprom(struct net_device *dev);
 414 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 415
 416 /* interrupt.c */
 417 extern unsigned int tulip_max_interrupt_work;
 418 extern int tulip_rx_copybreak;
 419 irqreturn_t tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
 420 int tulip_refill_rx(struct net_device *dev);
 421 #ifdef CONFIG_TULIP_NAPI
 422 int tulip_poll(struct net_device *dev, int *budget);
 423 #endif
 424
 425
 426 /* media.c */
 427 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 428 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 429 void tulip_select_media(struct net_device *dev, int startup);
 430 int tulip_check_duplex(struct net_device *dev);
 431 void tulip_find_mii (struct net_device *dev, int board_idx);
 432
 433 /* pnic.c */
 434 void pnic_do_nway(struct net_device *dev);
 435 void pnic_lnk_change(struct net_device *dev, int csr5);
 436 void pnic_timer(unsigned long data);
 437
 438 /* timer.c */
 439 void tulip_timer(unsigned long data);
 440 void mxic_timer(unsigned long data);
 441 void comet_timer(unsigned long data);
 442
 443 /* tulip_core.c */
 444 extern int tulip_debug;
 445 extern const char * const medianame[];
 446 extern const char tulip_media_cap[];
 447 extern struct tulip_chip_table tulip_tbl[];
 448 void oom_timer(unsigned long data);
 449 extern u8 t21040_csr13[];
 450
 451 static inline void tulip_start_rxtx(struct tulip_private *tp)
 452 {
 453         void __iomem *ioaddr = tp->base_addr;
 454         iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 455         barrier();
 456         (void) ioread32(ioaddr + CSR6); /* mmio sync */
 457 }
 458
 459 static inline void tulip_stop_rxtx(struct tulip_private *tp)
 460 {
 461         void __iomem *ioaddr = tp->base_addr;
 462         u32 csr6 = ioread32(ioaddr + CSR6);
 463
 464         if (csr6 & RxTx) {
 465                 unsigned i=1300/10;
 466                 iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 467                 barrier();
 468                 /* wait until in-flight frame completes.
 469                  * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 470                  * Typically expect this loop to end in < 50 us on 100BT.
 471                  */
 472                 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 473                         udelay(10);
 474
 475                 if (!i)
 476                         printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
 477                                         pci_name(tp->pdev));
 478         }
 479 }
 480
 481 static inline void tulip_restart_rxtx(struct tulip_private *tp)
 482 {
 483         tulip_stop_rxtx(tp);
 484         udelay(5);
 485         tulip_start_rxtx(tp);
 486 }
 487
 488 #endif /* __NET_TULIP_H__ */