?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] sata_sil24: fix on-memory structure byteorder
[linux-2.6.22.y-op.git] / drivers / scsi / sata_sil24.c
blob8ef51d0dcda77b5e6808d398523d902297ec49f6
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <asm/io.h>
32
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
35
36 /*
37 * Port request block (PRB) 32 bytes
38 */
39 struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44 };
45
46 /*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49 struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53 };
54
55 /*
56 * Port multiplier
57 */
58 struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61 };
62
63 enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
102
103 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
104 /* 32 bit regs */
105 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
106 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
107 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
108 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
109 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
110 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
111 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
112 PORT_CMD_ERR = 0x1024, /* command error number */
113 PORT_FIS_CFG = 0x1028,
114 PORT_FIFO_THRES = 0x102c,
115 /* 16 bit regs */
116 PORT_DECODE_ERR_CNT = 0x1040,
117 PORT_DECODE_ERR_THRESH = 0x1042,
118 PORT_CRC_ERR_CNT = 0x1044,
119 PORT_CRC_ERR_THRESH = 0x1046,
120 PORT_HSHK_ERR_CNT = 0x1048,
121 PORT_HSHK_ERR_THRESH = 0x104a,
122 /* 32 bit regs */
123 PORT_PHY_CFG = 0x1050,
124 PORT_SLOT_STAT = 0x1800,
125 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
126 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
127 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
128 PORT_SCONTROL = 0x1f00,
129 PORT_SSTATUS = 0x1f04,
130 PORT_SERROR = 0x1f08,
131 PORT_SACTIVE = 0x1f0c,
132
133 /* PORT_CTRL_STAT bits */
134 PORT_CS_PORT_RST = (1 << 0), /* port reset */
135 PORT_CS_DEV_RST = (1 << 1), /* device reset */
136 PORT_CS_INIT = (1 << 2), /* port initialize */
137 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
138 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
139 PORT_CS_RESUME = (1 << 6), /* port resume */
140 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
141 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
142 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
143
144 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
145 /* bits[11:0] are masked */
146 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
147 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
148 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
149 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
150 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
151 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
152 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
153 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
154 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
155 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
156 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
157 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
158
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
163
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
167
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
191
192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
198
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
206
207 /*
208 * Other constants
209 */
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
215
216 /* board id */
217 BID_SIL3124 = 0,
218 BID_SIL3132 = 1,
219 BID_SIL3131 = 2,
220
221 /* host flags */
222 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
224 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
225
226 IRQ_STAT_4PORTS = 0xf,
227 };
228
229 struct sil24_ata_block {
230 struct sil24_prb prb;
231 struct sil24_sge sge[LIBATA_MAX_PRD];
232 };
233
234 struct sil24_atapi_block {
235 struct sil24_prb prb;
236 u8 cdb[16];
237 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
238 };
239
240 union sil24_cmd_block {
241 struct sil24_ata_block ata;
242 struct sil24_atapi_block atapi;
243 };
244
245 /*
246 * ap->private_data
247 *
248 * The preview driver always returned 0 for status. We emulate it
249 * here from the previous interrupt.
250 */
251 struct sil24_port_priv {
252 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
253 dma_addr_t cmd_block_dma; /* DMA base addr for them */
254 struct ata_taskfile tf; /* Cached taskfile registers */
255 };
256
257 /* ap->host_set->private_data */
258 struct sil24_host_priv {
259 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
260 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
261 };
262
263 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
264 static u8 sil24_check_status(struct ata_port *ap);
265 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
266 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
267 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
268 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
269 static void sil24_qc_prep(struct ata_queued_cmd *qc);
270 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
271 static void sil24_irq_clear(struct ata_port *ap);
272 static void sil24_eng_timeout(struct ata_port *ap);
273 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
274 static int sil24_port_start(struct ata_port *ap);
275 static void sil24_port_stop(struct ata_port *ap);
276 static void sil24_host_stop(struct ata_host_set *host_set);
277 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
278
279 static const struct pci_device_id sil24_pci_tbl[] = {
280 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
281 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
282 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
283 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
284 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
285 { } /* terminate list */
286 };
287
288 static struct pci_driver sil24_pci_driver = {
289 .name = DRV_NAME,
290 .id_table = sil24_pci_tbl,
291 .probe = sil24_init_one,
292 .remove = ata_pci_remove_one, /* safe? */
293 };
294
295 static struct scsi_host_template sil24_sht = {
296 .module = THIS_MODULE,
297 .name = DRV_NAME,
298 .ioctl = ata_scsi_ioctl,
299 .queuecommand = ata_scsi_queuecmd,
300 .can_queue = ATA_DEF_QUEUE,
301 .this_id = ATA_SHT_THIS_ID,
302 .sg_tablesize = LIBATA_MAX_PRD,
303 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
304 .emulated = ATA_SHT_EMULATED,
305 .use_clustering = ATA_SHT_USE_CLUSTERING,
306 .proc_name = DRV_NAME,
307 .dma_boundary = ATA_DMA_BOUNDARY,
308 .slave_configure = ata_scsi_slave_config,
309 .bios_param = ata_std_bios_param,
310 };
311
312 static const struct ata_port_operations sil24_ops = {
313 .port_disable = ata_port_disable,
314
315 .dev_config = sil24_dev_config,
316
317 .check_status = sil24_check_status,
318 .check_altstatus = sil24_check_status,
319 .dev_select = ata_noop_dev_select,
320
321 .tf_read = sil24_tf_read,
322
323 .probe_reset = sil24_probe_reset,
324
325 .qc_prep = sil24_qc_prep,
326 .qc_issue = sil24_qc_issue,
327
328 .eng_timeout = sil24_eng_timeout,
329
330 .irq_handler = sil24_interrupt,
331 .irq_clear = sil24_irq_clear,
332
333 .scr_read = sil24_scr_read,
334 .scr_write = sil24_scr_write,
335
336 .port_start = sil24_port_start,
337 .port_stop = sil24_port_stop,
338 .host_stop = sil24_host_stop,
339 };
340
341 /*
342 * Use bits 30-31 of host_flags to encode available port numbers.
343 * Current maxium is 4.
344 */
345 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
346 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
347
348 static struct ata_port_info sil24_port_info[] = {
349 /* sil_3124 */
350 {
351 .sht = &sil24_sht,
352 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
353 SIL24_FLAG_PCIX_IRQ_WOC,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .mwdma_mask = 0x07, /* mwdma0-2 */
356 .udma_mask = 0x3f, /* udma0-5 */
357 .port_ops = &sil24_ops,
358 },
359 /* sil_3132 */
360 {
361 .sht = &sil24_sht,
362 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
363 .pio_mask = 0x1f, /* pio0-4 */
364 .mwdma_mask = 0x07, /* mwdma0-2 */
365 .udma_mask = 0x3f, /* udma0-5 */
366 .port_ops = &sil24_ops,
367 },
368 /* sil_3131/sil_3531 */
369 {
370 .sht = &sil24_sht,
371 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
372 .pio_mask = 0x1f, /* pio0-4 */
373 .mwdma_mask = 0x07, /* mwdma0-2 */
374 .udma_mask = 0x3f, /* udma0-5 */
375 .port_ops = &sil24_ops,
376 },
377 };
378
379 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
380 {
381 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
382
383 if (dev->cdb_len == 16)
384 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
385 else
386 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
387 }
388
389 static inline void sil24_update_tf(struct ata_port *ap)
390 {
391 struct sil24_port_priv *pp = ap->private_data;
392 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
393 struct sil24_prb __iomem *prb = port;
394 u8 fis[6 * 4];
395
396 memcpy_fromio(fis, prb->fis, 6 * 4);
397 ata_tf_from_fis(fis, &pp->tf);
398 }
399
400 static u8 sil24_check_status(struct ata_port *ap)
401 {
402 struct sil24_port_priv *pp = ap->private_data;
403 return pp->tf.command;
404 }
405
406 static int sil24_scr_map[] = {
407 [SCR_CONTROL] = 0,
408 [SCR_STATUS] = 1,
409 [SCR_ERROR] = 2,
410 [SCR_ACTIVE] = 3,
411 };
412
413 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
414 {
415 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
416 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
417 void __iomem *addr;
418 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
419 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
420 }
421 return 0xffffffffU;
422 }
423
424 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
425 {
426 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
427 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
428 void __iomem *addr;
429 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
430 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
431 }
432 }
433
434 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
435 {
436 struct sil24_port_priv *pp = ap->private_data;
437 *tf = pp->tf;
438 }
439
440 static int sil24_init_port(struct ata_port *ap)
441 {
442 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
443 u32 tmp;
444
445 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
446 ata_wait_register(port + PORT_CTRL_STAT,
447 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
448 tmp = ata_wait_register(port + PORT_CTRL_STAT,
449 PORT_CS_RDY, 0, 10, 100);
450
451 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
452 return -EIO;
453 return 0;
454 }
455
456 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
457 {
458 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
459 struct sil24_port_priv *pp = ap->private_data;
460 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
461 dma_addr_t paddr = pp->cmd_block_dma;
462 u32 mask, irq_enable, irq_stat;
463 const char *reason;
464
465 DPRINTK("ENTER\n");
466
467 if (!sata_dev_present(ap)) {
468 DPRINTK("PHY reports no device\n");
469 *class = ATA_DEV_NONE;
470 goto out;
471 }
472
473 /* temporarily turn off IRQs during SRST */
474 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
475 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
476
477 /* put the port into known state */
478 if (sil24_init_port(ap)) {
479 reason ="port not ready";
480 goto err;
481 }
482
483 /* do SRST */
484 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
485 prb->fis[1] = 0; /* no PM yet */
486
487 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
488
489 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
490 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
491 100, ATA_TMOUT_BOOT / HZ * 1000);
492
493 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
494 irq_stat >>= PORT_IRQ_RAW_SHIFT;
495
496 /* restore IRQs */
497 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
498
499 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
500 if (irq_stat & PORT_IRQ_ERROR)
501 reason = "SRST command error";
502 else
503 reason = "timeout";
504 goto err;
505 }
506
507 sil24_update_tf(ap);
508 *class = ata_dev_classify(&pp->tf);
509
510 if (*class == ATA_DEV_UNKNOWN)
511 *class = ATA_DEV_NONE;
512
513 out:
514 DPRINTK("EXIT, class=%u\n", *class);
515 return 0;
516
517 err:
518 printk(KERN_ERR "ata%u: softreset failed (%s)\n", ap->id, reason);
519 return -EIO;
520 }
521
522 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
523 {
524 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
525 const char *reason;
526 int tout_msec;
527 u32 tmp;
528
529 /* sil24 does the right thing(tm) without any protection */
530 ata_set_sata_spd(ap);
531
532 tout_msec = 100;
533 if (sata_dev_present(ap))
534 tout_msec = 5000;
535
536 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
537 tmp = ata_wait_register(port + PORT_CTRL_STAT,
538 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
539
540 /* SStatus oscillates between zero and valid status for short
541 * duration after DEV_RST, give it time to settle.
542 */
543 msleep(100);
544
545 if (tmp & PORT_CS_DEV_RST) {
546 if (!sata_dev_present(ap))
547 return 0;
548 reason = "link not ready";
549 goto err;
550 }
551
552 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
553 reason = "device not ready";
554 goto err;
555 }
556
557 /* sil24 doesn't report device class code after hardreset,
558 * leave *class alone.
559 */
560 return 0;
561
562 err:
563 printk(KERN_ERR "ata%u: hardreset failed (%s)\n", ap->id, reason);
564 return -EIO;
565 }
566
567 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
568 {
569 return ata_drive_probe_reset(ap, ata_std_probeinit,
570 sil24_softreset, sil24_hardreset,
571 ata_std_postreset, classes);
572 }
573
574 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
575 struct sil24_sge *sge)
576 {
577 struct scatterlist *sg;
578 unsigned int idx = 0;
579
580 ata_for_each_sg(sg, qc) {
581 sge->addr = cpu_to_le64(sg_dma_address(sg));
582 sge->cnt = cpu_to_le32(sg_dma_len(sg));
583 if (ata_sg_is_last(sg, qc))
584 sge->flags = cpu_to_le32(SGE_TRM);
585 else
586 sge->flags = 0;
587
588 sge++;
589 idx++;
590 }
591 }
592
593 static void sil24_qc_prep(struct ata_queued_cmd *qc)
594 {
595 struct ata_port *ap = qc->ap;
596 struct sil24_port_priv *pp = ap->private_data;
597 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
598 struct sil24_prb *prb;
599 struct sil24_sge *sge;
600 u16 ctrl = 0;
601
602 switch (qc->tf.protocol) {
603 case ATA_PROT_PIO:
604 case ATA_PROT_DMA:
605 case ATA_PROT_NODATA:
606 prb = &cb->ata.prb;
607 sge = cb->ata.sge;
608 break;
609
610 case ATA_PROT_ATAPI:
611 case ATA_PROT_ATAPI_DMA:
612 case ATA_PROT_ATAPI_NODATA:
613 prb = &cb->atapi.prb;
614 sge = cb->atapi.sge;
615 memset(cb->atapi.cdb, 0, 32);
616 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
617
618 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
619 if (qc->tf.flags & ATA_TFLAG_WRITE)
620 ctrl = PRB_CTRL_PACKET_WRITE;
621 else
622 ctrl = PRB_CTRL_PACKET_READ;
623 }
624 break;
625
626 default:
627 prb = NULL; /* shut up, gcc */
628 sge = NULL;
629 BUG();
630 }
631
632 prb->ctrl = cpu_to_le16(ctrl);
633 ata_tf_to_fis(&qc->tf, prb->fis, 0);
634
635 if (qc->flags & ATA_QCFLAG_DMAMAP)
636 sil24_fill_sg(qc, sge);
637 }
638
639 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
640 {
641 struct ata_port *ap = qc->ap;
642 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
643 struct sil24_port_priv *pp = ap->private_data;
644 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
645
646 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
647 return 0;
648 }
649
650 static void sil24_irq_clear(struct ata_port *ap)
651 {
652 /* unused */
653 }
654
655 static int __sil24_restart_controller(void __iomem *port)
656 {
657 u32 tmp;
658 int cnt;
659
660 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
661
662 /* Max ~10ms */
663 for (cnt = 0; cnt < 10000; cnt++) {
664 tmp = readl(port + PORT_CTRL_STAT);
665 if (tmp & PORT_CS_RDY)
666 return 0;
667 udelay(1);
668 }
669
670 return -1;
671 }
672
673 static void sil24_restart_controller(struct ata_port *ap)
674 {
675 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
676 printk(KERN_ERR DRV_NAME
677 " ata%u: failed to restart controller\n", ap->id);
678 }
679
680 static int __sil24_reset_controller(void __iomem *port)
681 {
682 int cnt;
683 u32 tmp;
684
685 /* Reset controller state. Is this correct? */
686 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
687 readl(port + PORT_CTRL_STAT); /* sync */
688
689 /* Max ~100ms */
690 for (cnt = 0; cnt < 1000; cnt++) {
691 udelay(100);
692 tmp = readl(port + PORT_CTRL_STAT);
693 if (!(tmp & PORT_CS_DEV_RST))
694 break;
695 }
696
697 if (tmp & PORT_CS_DEV_RST)
698 return -1;
699
700 if (tmp & PORT_CS_RDY)
701 return 0;
702
703 return __sil24_restart_controller(port);
704 }
705
706 static void sil24_reset_controller(struct ata_port *ap)
707 {
708 printk(KERN_NOTICE DRV_NAME
709 " ata%u: resetting controller...\n", ap->id);
710 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
711 printk(KERN_ERR DRV_NAME
712 " ata%u: failed to reset controller\n", ap->id);
713 }
714
715 static void sil24_eng_timeout(struct ata_port *ap)
716 {
717 struct ata_queued_cmd *qc;
718
719 qc = ata_qc_from_tag(ap, ap->active_tag);
720
721 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
722 qc->err_mask |= AC_ERR_TIMEOUT;
723 ata_eh_qc_complete(qc);
724
725 sil24_reset_controller(ap);
726 }
727
728 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
729 {
730 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
731 struct sil24_port_priv *pp = ap->private_data;
732 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
733 u32 irq_stat, cmd_err, sstatus, serror;
734 unsigned int err_mask;
735
736 irq_stat = readl(port + PORT_IRQ_STAT);
737 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
738
739 if (!(irq_stat & PORT_IRQ_ERROR)) {
740 /* ignore non-completion, non-error irqs for now */
741 printk(KERN_WARNING DRV_NAME
742 "ata%u: non-error exception irq (irq_stat %x)\n",
743 ap->id, irq_stat);
744 return;
745 }
746
747 cmd_err = readl(port + PORT_CMD_ERR);
748 sstatus = readl(port + PORT_SSTATUS);
749 serror = readl(port + PORT_SERROR);
750 if (serror)
751 writel(serror, port + PORT_SERROR);
752
753 /*
754 * Don't log ATAPI device errors. They're supposed to happen
755 * and any serious errors will be logged using sense data by
756 * the SCSI layer.
757 */
758 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
759 printk("ata%u: error interrupt on port%d\n"
760 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
761 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
762
763 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
764 /*
765 * Device is reporting error, tf registers are valid.
766 */
767 sil24_update_tf(ap);
768 err_mask = ac_err_mask(pp->tf.command);
769 sil24_restart_controller(ap);
770 } else {
771 /*
772 * Other errors. libata currently doesn't have any
773 * mechanism to report these errors. Just turn on
774 * ATA_ERR.
775 */
776 err_mask = AC_ERR_OTHER;
777 sil24_reset_controller(ap);
778 }
779
780 if (qc) {
781 qc->err_mask |= err_mask;
782 ata_qc_complete(qc);
783 }
784 }
785
786 static inline void sil24_host_intr(struct ata_port *ap)
787 {
788 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
789 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
790 u32 slot_stat;
791
792 slot_stat = readl(port + PORT_SLOT_STAT);
793 if (!(slot_stat & HOST_SSTAT_ATTN)) {
794 struct sil24_port_priv *pp = ap->private_data;
795
796 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
797 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
798
799 /*
800 * !HOST_SSAT_ATTN guarantees successful completion,
801 * so reading back tf registers is unnecessary for
802 * most commands. TODO: read tf registers for
803 * commands which require these values on successful
804 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
805 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
806 */
807 sil24_update_tf(ap);
808
809 if (qc) {
810 qc->err_mask |= ac_err_mask(pp->tf.command);
811 ata_qc_complete(qc);
812 }
813 } else
814 sil24_error_intr(ap, slot_stat);
815 }
816
817 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
818 {
819 struct ata_host_set *host_set = dev_instance;
820 struct sil24_host_priv *hpriv = host_set->private_data;
821 unsigned handled = 0;
822 u32 status;
823 int i;
824
825 status = readl(hpriv->host_base + HOST_IRQ_STAT);
826
827 if (status == 0xffffffff) {
828 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
829 "PCI fault or device removal?\n");
830 goto out;
831 }
832
833 if (!(status & IRQ_STAT_4PORTS))
834 goto out;
835
836 spin_lock(&host_set->lock);
837
838 for (i = 0; i < host_set->n_ports; i++)
839 if (status & (1 << i)) {
840 struct ata_port *ap = host_set->ports[i];
841 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
842 sil24_host_intr(host_set->ports[i]);
843 handled++;
844 } else
845 printk(KERN_ERR DRV_NAME
846 ": interrupt from disabled port %d\n", i);
847 }
848
849 spin_unlock(&host_set->lock);
850 out:
851 return IRQ_RETVAL(handled);
852 }
853
854 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
855 {
856 const size_t cb_size = sizeof(*pp->cmd_block);
857
858 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
859 }
860
861 static int sil24_port_start(struct ata_port *ap)
862 {
863 struct device *dev = ap->host_set->dev;
864 struct sil24_port_priv *pp;
865 union sil24_cmd_block *cb;
866 size_t cb_size = sizeof(*cb);
867 dma_addr_t cb_dma;
868 int rc = -ENOMEM;
869
870 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
871 if (!pp)
872 goto err_out;
873
874 pp->tf.command = ATA_DRDY;
875
876 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
877 if (!cb)
878 goto err_out_pp;
879 memset(cb, 0, cb_size);
880
881 rc = ata_pad_alloc(ap, dev);
882 if (rc)
883 goto err_out_pad;
884
885 pp->cmd_block = cb;
886 pp->cmd_block_dma = cb_dma;
887
888 ap->private_data = pp;
889
890 return 0;
891
892 err_out_pad:
893 sil24_cblk_free(pp, dev);
894 err_out_pp:
895 kfree(pp);
896 err_out:
897 return rc;
898 }
899
900 static void sil24_port_stop(struct ata_port *ap)
901 {
902 struct device *dev = ap->host_set->dev;
903 struct sil24_port_priv *pp = ap->private_data;
904
905 sil24_cblk_free(pp, dev);
906 ata_pad_free(ap, dev);
907 kfree(pp);
908 }
909
910 static void sil24_host_stop(struct ata_host_set *host_set)
911 {
912 struct sil24_host_priv *hpriv = host_set->private_data;
913 struct pci_dev *pdev = to_pci_dev(host_set->dev);
914
915 pci_iounmap(pdev, hpriv->host_base);
916 pci_iounmap(pdev, hpriv->port_base);
917 kfree(hpriv);
918 }
919
920 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
921 {
922 static int printed_version = 0;
923 unsigned int board_id = (unsigned int)ent->driver_data;
924 struct ata_port_info *pinfo = &sil24_port_info[board_id];
925 struct ata_probe_ent *probe_ent = NULL;
926 struct sil24_host_priv *hpriv = NULL;
927 void __iomem *host_base = NULL;
928 void __iomem *port_base = NULL;
929 int i, rc;
930 u32 tmp;
931
932 if (!printed_version++)
933 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
934
935 rc = pci_enable_device(pdev);
936 if (rc)
937 return rc;
938
939 rc = pci_request_regions(pdev, DRV_NAME);
940 if (rc)
941 goto out_disable;
942
943 rc = -ENOMEM;
944 /* map mmio registers */
945 host_base = pci_iomap(pdev, 0, 0);
946 if (!host_base)
947 goto out_free;
948 port_base = pci_iomap(pdev, 2, 0);
949 if (!port_base)
950 goto out_free;
951
952 /* allocate & init probe_ent and hpriv */
953 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
954 if (!probe_ent)
955 goto out_free;
956
957 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
958 if (!hpriv)
959 goto out_free;
960
961 probe_ent->dev = pci_dev_to_dev(pdev);
962 INIT_LIST_HEAD(&probe_ent->node);
963
964 probe_ent->sht = pinfo->sht;
965 probe_ent->host_flags = pinfo->host_flags;
966 probe_ent->pio_mask = pinfo->pio_mask;
967 probe_ent->mwdma_mask = pinfo->mwdma_mask;
968 probe_ent->udma_mask = pinfo->udma_mask;
969 probe_ent->port_ops = pinfo->port_ops;
970 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
971
972 probe_ent->irq = pdev->irq;
973 probe_ent->irq_flags = SA_SHIRQ;
974 probe_ent->mmio_base = port_base;
975 probe_ent->private_data = hpriv;
976
977 hpriv->host_base = host_base;
978 hpriv->port_base = port_base;
979
980 /*
981 * Configure the device
982 */
983 /*
984 * FIXME: This device is certainly 64-bit capable. We just
985 * don't know how to use it. After fixing 32bit activation in
986 * this function, enable 64bit masks here.
987 */
988 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
989 if (rc) {
990 dev_printk(KERN_ERR, &pdev->dev,
991 "32-bit DMA enable failed\n");
992 goto out_free;
993 }
994 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
995 if (rc) {
996 dev_printk(KERN_ERR, &pdev->dev,
997 "32-bit consistent DMA enable failed\n");
998 goto out_free;
999 }
1000
1001 /* GPIO off */
1002 writel(0, host_base + HOST_FLASH_CMD);
1003
1004 /* Apply workaround for completion IRQ loss on PCI-X errata */
1005 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1006 tmp = readl(host_base + HOST_CTRL);
1007 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1008 dev_printk(KERN_INFO, &pdev->dev,
1009 "Applying completion IRQ loss on PCI-X "
1010 "errata fix\n");
1011 else
1012 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1013 }
1014
1015 /* clear global reset & mask interrupts during initialization */
1016 writel(0, host_base + HOST_CTRL);
1017
1018 for (i = 0; i < probe_ent->n_ports; i++) {
1019 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1020 unsigned long portu = (unsigned long)port;
1021
1022 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
1023 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1024
1025 ata_std_ports(&probe_ent->port[i]);
1026
1027 /* Initial PHY setting */
1028 writel(0x20c, port + PORT_PHY_CFG);
1029
1030 /* Clear port RST */
1031 tmp = readl(port + PORT_CTRL_STAT);
1032 if (tmp & PORT_CS_PORT_RST) {
1033 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1034 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1035 PORT_CS_PORT_RST,
1036 PORT_CS_PORT_RST, 10, 100);
1037 if (tmp & PORT_CS_PORT_RST)
1038 dev_printk(KERN_ERR, &pdev->dev,
1039 "failed to clear port RST\n");
1040 }
1041
1042 /* Configure IRQ WoC */
1043 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1044 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1045 else
1046 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1047
1048 /* Zero error counters. */
1049 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1050 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1051 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1052 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1053 writel(0x0000, port + PORT_CRC_ERR_CNT);
1054 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1055
1056 /* FIXME: 32bit activation? */
1057 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
1058 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
1059
1060 /* Configure interrupts */
1061 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
1062 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
1063 PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET);
1064
1065 /* Clear interrupts */
1066 writel(0x0fff0fff, port + PORT_IRQ_STAT);
1067 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1068
1069 /* Clear port multiplier enable and resume bits */
1070 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1071 }
1072
1073 /* Turn on interrupts */
1074 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1075
1076 pci_set_master(pdev);
1077
1078 /* FIXME: check ata_device_add return value */
1079 ata_device_add(probe_ent);
1080
1081 kfree(probe_ent);
1082 return 0;
1083
1084 out_free:
1085 if (host_base)
1086 pci_iounmap(pdev, host_base);
1087 if (port_base)
1088 pci_iounmap(pdev, port_base);
1089 kfree(probe_ent);
1090 kfree(hpriv);
1091 pci_release_regions(pdev);
1092 out_disable:
1093 pci_disable_device(pdev);
1094 return rc;
1095 }
1096
1097 static int __init sil24_init(void)
1098 {
1099 return pci_module_init(&sil24_pci_driver);
1100 }
1101
1102 static void __exit sil24_exit(void)
1103 {
1104 pci_unregister_driver(&sil24_pci_driver);
1105 }
1106
1107 MODULE_AUTHOR("Tejun Heo");
1108 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1109 MODULE_LICENSE("GPL");
1110 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1111
1112 module_init(sil24_init);
1113 module_exit(sil24_exit);
linux v2.6.22.y-op