1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 * Authors: Phil Blundell <philb@gnu.org>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
28 * In addition, there are some optional registers:
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
45 #include <linux/module.h>
46 #include <linux/init.h>
47 #include <linux/sched.h>
48 #include <linux/delay.h>
49 #include <linux/errno.h>
50 #include <linux/interrupt.h>
51 #include <linux/ioport.h>
52 #include <linux/kernel.h>
53 #include <linux/slab.h>
54 #include <linux/pci.h>
55 #include <linux/pnp.h>
56 #include <linux/platform_device.h>
57 #include <linux/sysctl.h>
61 #include <asm/uaccess.h>
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <linux/via.h>
66 #include <asm/parport.h>
68 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
70 #ifdef CONFIG_ISA_DMA_API
83 #define ECR_MODE_MASK 0xe0
84 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
89 #define DPRINTK printk
91 #define DPRINTK(stuff...)
96 static struct superio_struct
{ /* For Super-IO chips autodetection */
100 } superios
[NR_SUPERIOS
] = { {0,},};
102 static int user_specified
;
103 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
104 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
105 static int verbose_probing
;
107 static int pci_registered_parport
;
108 static int pnp_registered_parport
;
110 /* frob_control, but for ECR */
111 static void frob_econtrol (struct parport
*pb
, unsigned char m
,
114 unsigned char ectr
= 0;
117 ectr
= inb (ECONTROL (pb
));
119 DPRINTK (KERN_DEBUG
"frob_econtrol(%02x,%02x): %02x -> %02x\n",
120 m
, v
, ectr
, (ectr
& ~m
) ^ v
);
122 outb ((ectr
& ~m
) ^ v
, ECONTROL (pb
));
125 static __inline__
void frob_set_mode (struct parport
*p
, int mode
)
127 frob_econtrol (p
, ECR_MODE_MASK
, mode
<< 5);
130 #ifdef CONFIG_PARPORT_PC_FIFO
131 /* Safely change the mode bits in the ECR
134 -EBUSY: Could not drain FIFO in some finite amount of time,
137 static int change_mode(struct parport
*p
, int m
)
139 const struct parport_pc_private
*priv
= p
->physport
->private_data
;
143 DPRINTK(KERN_INFO
"parport change_mode ECP-ISA to mode 0x%02x\n",m
);
146 printk (KERN_DEBUG
"change_mode: but there's no ECR!\n");
150 /* Bits <7:5> contain the mode. */
151 oecr
= inb (ECONTROL (p
));
152 mode
= (oecr
>> 5) & 0x7;
153 if (mode
== m
) return 0;
155 if (mode
>= 2 && !(priv
->ctr
& 0x20)) {
156 /* This mode resets the FIFO, so we may
157 * have to wait for it to drain first. */
158 unsigned long expire
= jiffies
+ p
->physport
->cad
->timeout
;
161 case ECR_PPF
: /* Parallel Port FIFO mode */
162 case ECR_ECP
: /* ECP Parallel Port mode */
163 /* Busy wait for 200us */
164 for (counter
= 0; counter
< 40; counter
++) {
165 if (inb (ECONTROL (p
)) & 0x01)
167 if (signal_pending (current
)) break;
172 while (!(inb (ECONTROL (p
)) & 0x01)) {
173 if (time_after_eq (jiffies
, expire
))
174 /* The FIFO is stuck. */
176 schedule_timeout_interruptible(msecs_to_jiffies(10));
177 if (signal_pending (current
))
183 if (mode
>= 2 && m
>= 2) {
184 /* We have to go through mode 001 */
186 oecr
|= ECR_PS2
<< 5;
197 #ifdef CONFIG_PARPORT_1284
198 /* Find FIFO lossage; FIFO is reset */
200 static int get_fifo_residue (struct parport
*p
)
204 const struct parport_pc_private
*priv
= p
->physport
->private_data
;
206 /* Adjust for the contents of the FIFO. */
207 for (residue
= priv
->fifo_depth
; ; residue
--) {
208 if (inb (ECONTROL (p
)) & 0x2)
215 printk (KERN_DEBUG
"%s: %d PWords were left in FIFO\n", p
->name
,
218 /* Reset the FIFO. */
219 frob_set_mode (p
, ECR_PS2
);
221 /* Now change to config mode and clean up. FIXME */
222 frob_set_mode (p
, ECR_CNF
);
223 cnfga
= inb (CONFIGA (p
));
224 printk (KERN_DEBUG
"%s: cnfgA contains 0x%02x\n", p
->name
, cnfga
);
226 if (!(cnfga
& (1<<2))) {
227 printk (KERN_DEBUG
"%s: Accounting for extra byte\n", p
->name
);
231 /* Don't care about partial PWords until support is added for
232 * PWord != 1 byte. */
234 /* Back to PS2 mode. */
235 frob_set_mode (p
, ECR_PS2
);
237 DPRINTK (KERN_DEBUG
"*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p
)));
241 #endif /* IEEE 1284 support */
242 #endif /* FIFO support */
245 * Clear TIMEOUT BIT in EPP MODE
247 * This is also used in SPP detection.
249 static int clear_epp_timeout(struct parport
*pb
)
253 if (!(parport_pc_read_status(pb
) & 0x01))
256 /* To clear timeout some chips require double read */
257 parport_pc_read_status(pb
);
258 r
= parport_pc_read_status(pb
);
259 outb (r
| 0x01, STATUS (pb
)); /* Some reset by writing 1 */
260 outb (r
& 0xfe, STATUS (pb
)); /* Others by writing 0 */
261 r
= parport_pc_read_status(pb
);
269 * Most of these aren't static because they may be used by the
270 * parport_xxx_yyy macros. extern __inline__ versions of several
271 * of these are in parport_pc.h.
274 static irqreturn_t
parport_pc_interrupt(int irq
, void *dev_id
)
276 parport_generic_irq(irq
, (struct parport
*) dev_id
);
277 /* FIXME! Was it really ours? */
281 static void parport_pc_init_state(struct pardevice
*dev
, struct parport_state
*s
)
285 dev
->port
->irq
!= PARPORT_IRQ_NONE
)
289 s
->u
.pc
.ecr
= 0x34; /* NetMos chip can cause problems 0x24;
293 static void parport_pc_save_state(struct parport
*p
, struct parport_state
*s
)
295 const struct parport_pc_private
*priv
= p
->physport
->private_data
;
296 s
->u
.pc
.ctr
= priv
->ctr
;
298 s
->u
.pc
.ecr
= inb (ECONTROL (p
));
301 static void parport_pc_restore_state(struct parport
*p
, struct parport_state
*s
)
303 struct parport_pc_private
*priv
= p
->physport
->private_data
;
304 register unsigned char c
= s
->u
.pc
.ctr
& priv
->ctr_writable
;
305 outb (c
, CONTROL (p
));
308 ECR_WRITE (p
, s
->u
.pc
.ecr
);
311 #ifdef CONFIG_PARPORT_1284
312 static size_t parport_pc_epp_read_data (struct parport
*port
, void *buf
,
313 size_t length
, int flags
)
317 if (flags
& PARPORT_W91284PIC
) {
318 unsigned char status
;
319 size_t left
= length
;
321 /* use knowledge about data lines..:
322 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
323 * pError is 1 if there are 16 bytes in the Warp's FIFO
325 status
= inb (STATUS (port
));
327 while (!(status
& 0x08) && (got
< length
)) {
328 if ((left
>= 16) && (status
& 0x20) && !(status
& 0x08)) {
329 /* can grab 16 bytes from warp fifo */
330 if (!((long)buf
& 0x03)) {
331 insl (EPPDATA (port
), buf
, 4);
333 insb (EPPDATA (port
), buf
, 16);
339 /* grab single byte from the warp fifo */
340 *((char *)buf
) = inb (EPPDATA (port
));
345 status
= inb (STATUS (port
));
347 /* EPP timeout should never occur... */
348 printk (KERN_DEBUG
"%s: EPP timeout occurred while talking to "
349 "w91284pic (should not have done)\n", port
->name
);
350 clear_epp_timeout (port
);
355 if ((flags
& PARPORT_EPP_FAST
) && (length
> 1)) {
356 if (!(((long)buf
| length
) & 0x03)) {
357 insl (EPPDATA (port
), buf
, (length
>> 2));
359 insb (EPPDATA (port
), buf
, length
);
361 if (inb (STATUS (port
)) & 0x01) {
362 clear_epp_timeout (port
);
367 for (; got
< length
; got
++) {
368 *((char*)buf
) = inb (EPPDATA(port
));
370 if (inb (STATUS (port
)) & 0x01) {
372 clear_epp_timeout (port
);
380 static size_t parport_pc_epp_write_data (struct parport
*port
, const void *buf
,
381 size_t length
, int flags
)
385 if ((flags
& PARPORT_EPP_FAST
) && (length
> 1)) {
386 if (!(((long)buf
| length
) & 0x03)) {
387 outsl (EPPDATA (port
), buf
, (length
>> 2));
389 outsb (EPPDATA (port
), buf
, length
);
391 if (inb (STATUS (port
)) & 0x01) {
392 clear_epp_timeout (port
);
397 for (; written
< length
; written
++) {
398 outb (*((char*)buf
), EPPDATA(port
));
400 if (inb (STATUS(port
)) & 0x01) {
401 clear_epp_timeout (port
);
409 static size_t parport_pc_epp_read_addr (struct parport
*port
, void *buf
,
410 size_t length
, int flags
)
414 if ((flags
& PARPORT_EPP_FAST
) && (length
> 1)) {
415 insb (EPPADDR (port
), buf
, length
);
416 if (inb (STATUS (port
)) & 0x01) {
417 clear_epp_timeout (port
);
422 for (; got
< length
; got
++) {
423 *((char*)buf
) = inb (EPPADDR (port
));
425 if (inb (STATUS (port
)) & 0x01) {
426 clear_epp_timeout (port
);
434 static size_t parport_pc_epp_write_addr (struct parport
*port
,
435 const void *buf
, size_t length
,
440 if ((flags
& PARPORT_EPP_FAST
) && (length
> 1)) {
441 outsb (EPPADDR (port
), buf
, length
);
442 if (inb (STATUS (port
)) & 0x01) {
443 clear_epp_timeout (port
);
448 for (; written
< length
; written
++) {
449 outb (*((char*)buf
), EPPADDR (port
));
451 if (inb (STATUS (port
)) & 0x01) {
452 clear_epp_timeout (port
);
460 static size_t parport_pc_ecpepp_read_data (struct parport
*port
, void *buf
,
461 size_t length
, int flags
)
465 frob_set_mode (port
, ECR_EPP
);
466 parport_pc_data_reverse (port
);
467 parport_pc_write_control (port
, 0x4);
468 got
= parport_pc_epp_read_data (port
, buf
, length
, flags
);
469 frob_set_mode (port
, ECR_PS2
);
474 static size_t parport_pc_ecpepp_write_data (struct parport
*port
,
475 const void *buf
, size_t length
,
480 frob_set_mode (port
, ECR_EPP
);
481 parport_pc_write_control (port
, 0x4);
482 parport_pc_data_forward (port
);
483 written
= parport_pc_epp_write_data (port
, buf
, length
, flags
);
484 frob_set_mode (port
, ECR_PS2
);
489 static size_t parport_pc_ecpepp_read_addr (struct parport
*port
, void *buf
,
490 size_t length
, int flags
)
494 frob_set_mode (port
, ECR_EPP
);
495 parport_pc_data_reverse (port
);
496 parport_pc_write_control (port
, 0x4);
497 got
= parport_pc_epp_read_addr (port
, buf
, length
, flags
);
498 frob_set_mode (port
, ECR_PS2
);
503 static size_t parport_pc_ecpepp_write_addr (struct parport
*port
,
504 const void *buf
, size_t length
,
509 frob_set_mode (port
, ECR_EPP
);
510 parport_pc_write_control (port
, 0x4);
511 parport_pc_data_forward (port
);
512 written
= parport_pc_epp_write_addr (port
, buf
, length
, flags
);
513 frob_set_mode (port
, ECR_PS2
);
517 #endif /* IEEE 1284 support */
519 #ifdef CONFIG_PARPORT_PC_FIFO
520 static size_t parport_pc_fifo_write_block_pio (struct parport
*port
,
521 const void *buf
, size_t length
)
524 const unsigned char *bufp
= buf
;
525 size_t left
= length
;
526 unsigned long expire
= jiffies
+ port
->physport
->cad
->timeout
;
527 const int fifo
= FIFO (port
);
528 int poll_for
= 8; /* 80 usecs */
529 const struct parport_pc_private
*priv
= port
->physport
->private_data
;
530 const int fifo_depth
= priv
->fifo_depth
;
532 port
= port
->physport
;
534 /* We don't want to be interrupted every character. */
535 parport_pc_disable_irq (port
);
536 /* set nErrIntrEn and serviceIntr */
537 frob_econtrol (port
, (1<<4) | (1<<2), (1<<4) | (1<<2));
540 parport_pc_data_forward (port
); /* Must be in PS2 mode */
544 unsigned char ecrval
= inb (ECONTROL (port
));
547 if (need_resched() && time_before (jiffies
, expire
))
548 /* Can't yield the port. */
551 /* Anyone else waiting for the port? */
552 if (port
->waithead
) {
553 printk (KERN_DEBUG
"Somebody wants the port\n");
558 /* FIFO is full. Wait for interrupt. */
560 /* Clear serviceIntr */
561 ECR_WRITE (port
, ecrval
& ~(1<<2));
563 ret
= parport_wait_event (port
, HZ
);
566 if (!time_before (jiffies
, expire
)) {
568 printk (KERN_DEBUG
"FIFO write timed out\n");
571 ecrval
= inb (ECONTROL (port
));
572 if (!(ecrval
& (1<<2))) {
573 if (need_resched() &&
574 time_before (jiffies
, expire
))
583 /* Can't fail now. */
584 expire
= jiffies
+ port
->cad
->timeout
;
587 if (signal_pending (current
))
591 /* FIFO is empty. Blast it full. */
592 const int n
= left
< fifo_depth
? left
: fifo_depth
;
593 outsb (fifo
, bufp
, n
);
597 /* Adjust the poll time. */
598 if (i
< (poll_for
- 2)) poll_for
--;
600 } else if (i
++ < poll_for
) {
602 ecrval
= inb (ECONTROL (port
));
606 /* Half-full (call me an optimist) */
612 dump_parport_state ("leave fifo_write_block_pio", port
);
613 return length
- left
;
617 static size_t parport_pc_fifo_write_block_dma (struct parport
*port
,
618 const void *buf
, size_t length
)
621 unsigned long dmaflag
;
622 size_t left
= length
;
623 const struct parport_pc_private
*priv
= port
->physport
->private_data
;
624 struct device
*dev
= port
->physport
->dev
;
625 dma_addr_t dma_addr
, dma_handle
;
626 size_t maxlen
= 0x10000; /* max 64k per DMA transfer */
627 unsigned long start
= (unsigned long) buf
;
628 unsigned long end
= (unsigned long) buf
+ length
- 1;
630 dump_parport_state ("enter fifo_write_block_dma", port
);
631 if (end
< MAX_DMA_ADDRESS
) {
632 /* If it would cross a 64k boundary, cap it at the end. */
633 if ((start
^ end
) & ~0xffffUL
)
634 maxlen
= 0x10000 - (start
& 0xffff);
636 dma_addr
= dma_handle
= dma_map_single(dev
, (void *)buf
, length
,
639 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
640 maxlen
= PAGE_SIZE
; /* sizeof(priv->dma_buf) */
641 dma_addr
= priv
->dma_handle
;
645 port
= port
->physport
;
647 /* We don't want to be interrupted every character. */
648 parport_pc_disable_irq (port
);
649 /* set nErrIntrEn and serviceIntr */
650 frob_econtrol (port
, (1<<4) | (1<<2), (1<<4) | (1<<2));
653 parport_pc_data_forward (port
); /* Must be in PS2 mode */
656 unsigned long expire
= jiffies
+ port
->physport
->cad
->timeout
;
663 if (!dma_handle
) /* bounce buffer ! */
664 memcpy(priv
->dma_buf
, buf
, count
);
666 dmaflag
= claim_dma_lock();
667 disable_dma(port
->dma
);
668 clear_dma_ff(port
->dma
);
669 set_dma_mode(port
->dma
, DMA_MODE_WRITE
);
670 set_dma_addr(port
->dma
, dma_addr
);
671 set_dma_count(port
->dma
, count
);
674 frob_econtrol (port
, 1<<3, 1<<3);
676 /* Clear serviceIntr */
677 frob_econtrol (port
, 1<<2, 0);
679 enable_dma(port
->dma
);
680 release_dma_lock(dmaflag
);
682 /* assume DMA will be successful */
685 if (dma_handle
) dma_addr
+= count
;
687 /* Wait for interrupt. */
689 ret
= parport_wait_event (port
, HZ
);
692 if (!time_before (jiffies
, expire
)) {
694 printk (KERN_DEBUG
"DMA write timed out\n");
697 /* Is serviceIntr set? */
698 if (!(inb (ECONTROL (port
)) & (1<<2))) {
704 dmaflag
= claim_dma_lock();
705 disable_dma(port
->dma
);
706 clear_dma_ff(port
->dma
);
707 count
= get_dma_residue(port
->dma
);
708 release_dma_lock(dmaflag
);
710 cond_resched(); /* Can't yield the port. */
712 /* Anyone else waiting for the port? */
713 if (port
->waithead
) {
714 printk (KERN_DEBUG
"Somebody wants the port\n");
718 /* update for possible DMA residue ! */
721 if (dma_handle
) dma_addr
-= count
;
724 /* Maybe got here through break, so adjust for DMA residue! */
725 dmaflag
= claim_dma_lock();
726 disable_dma(port
->dma
);
727 clear_dma_ff(port
->dma
);
728 left
+= get_dma_residue(port
->dma
);
729 release_dma_lock(dmaflag
);
731 /* Turn off DMA mode */
732 frob_econtrol (port
, 1<<3, 0);
735 dma_unmap_single(dev
, dma_handle
, length
, DMA_TO_DEVICE
);
737 dump_parport_state ("leave fifo_write_block_dma", port
);
738 return length
- left
;
742 static inline size_t parport_pc_fifo_write_block(struct parport
*port
,
743 const void *buf
, size_t length
)
746 if (port
->dma
!= PARPORT_DMA_NONE
)
747 return parport_pc_fifo_write_block_dma (port
, buf
, length
);
749 return parport_pc_fifo_write_block_pio (port
, buf
, length
);
752 /* Parallel Port FIFO mode (ECP chipsets) */
753 static size_t parport_pc_compat_write_block_pio (struct parport
*port
,
754 const void *buf
, size_t length
,
759 unsigned long expire
;
760 const struct parport_pc_private
*priv
= port
->physport
->private_data
;
762 /* Special case: a timeout of zero means we cannot call schedule().
763 * Also if O_NONBLOCK is set then use the default implementation. */
764 if (port
->physport
->cad
->timeout
<= PARPORT_INACTIVITY_O_NONBLOCK
)
765 return parport_ieee1284_write_compat (port
, buf
,
768 /* Set up parallel port FIFO mode.*/
769 parport_pc_data_forward (port
); /* Must be in PS2 mode */
770 parport_pc_frob_control (port
, PARPORT_CONTROL_STROBE
, 0);
771 r
= change_mode (port
, ECR_PPF
); /* Parallel port FIFO */
772 if (r
) printk (KERN_DEBUG
"%s: Warning change_mode ECR_PPF failed\n", port
->name
);
774 port
->physport
->ieee1284
.phase
= IEEE1284_PH_FWD_DATA
;
776 /* Write the data to the FIFO. */
777 written
= parport_pc_fifo_write_block(port
, buf
, length
);
780 /* For some hardware we don't want to touch the mode until
781 * the FIFO is empty, so allow 4 seconds for each position
784 expire
= jiffies
+ (priv
->fifo_depth
* HZ
* 4);
786 /* Wait for the FIFO to empty */
787 r
= change_mode (port
, ECR_PS2
);
791 } while (time_before (jiffies
, expire
));
794 printk (KERN_DEBUG
"%s: FIFO is stuck\n", port
->name
);
796 /* Prevent further data transfer. */
797 frob_set_mode (port
, ECR_TST
);
799 /* Adjust for the contents of the FIFO. */
800 for (written
-= priv
->fifo_depth
; ; written
++) {
801 if (inb (ECONTROL (port
)) & 0x2) {
805 outb (0, FIFO (port
));
808 /* Reset the FIFO and return to PS2 mode. */
809 frob_set_mode (port
, ECR_PS2
);
812 r
= parport_wait_peripheral (port
,
814 PARPORT_STATUS_BUSY
);
817 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
820 port
->physport
->ieee1284
.phase
= IEEE1284_PH_FWD_IDLE
;
826 #ifdef CONFIG_PARPORT_1284
827 static size_t parport_pc_ecp_write_block_pio (struct parport
*port
,
828 const void *buf
, size_t length
,
833 unsigned long expire
;
834 const struct parport_pc_private
*priv
= port
->physport
->private_data
;
836 /* Special case: a timeout of zero means we cannot call schedule().
837 * Also if O_NONBLOCK is set then use the default implementation. */
838 if (port
->physport
->cad
->timeout
<= PARPORT_INACTIVITY_O_NONBLOCK
)
839 return parport_ieee1284_ecp_write_data (port
, buf
,
842 /* Switch to forward mode if necessary. */
843 if (port
->physport
->ieee1284
.phase
!= IEEE1284_PH_FWD_IDLE
) {
844 /* Event 47: Set nInit high. */
845 parport_frob_control (port
,
847 | PARPORT_CONTROL_AUTOFD
,
849 | PARPORT_CONTROL_AUTOFD
);
851 /* Event 49: PError goes high. */
852 r
= parport_wait_peripheral (port
,
853 PARPORT_STATUS_PAPEROUT
,
854 PARPORT_STATUS_PAPEROUT
);
856 printk (KERN_DEBUG
"%s: PError timeout (%d) "
857 "in ecp_write_block_pio\n", port
->name
, r
);
861 /* Set up ECP parallel port mode.*/
862 parport_pc_data_forward (port
); /* Must be in PS2 mode */
863 parport_pc_frob_control (port
,
864 PARPORT_CONTROL_STROBE
|
865 PARPORT_CONTROL_AUTOFD
,
867 r
= change_mode (port
, ECR_ECP
); /* ECP FIFO */
868 if (r
) printk (KERN_DEBUG
"%s: Warning change_mode ECR_ECP failed\n", port
->name
);
869 port
->physport
->ieee1284
.phase
= IEEE1284_PH_FWD_DATA
;
871 /* Write the data to the FIFO. */
872 written
= parport_pc_fifo_write_block(port
, buf
, length
);
875 /* For some hardware we don't want to touch the mode until
876 * the FIFO is empty, so allow 4 seconds for each position
879 expire
= jiffies
+ (priv
->fifo_depth
* (HZ
* 4));
881 /* Wait for the FIFO to empty */
882 r
= change_mode (port
, ECR_PS2
);
886 } while (time_before (jiffies
, expire
));
889 printk (KERN_DEBUG
"%s: FIFO is stuck\n", port
->name
);
891 /* Prevent further data transfer. */
892 frob_set_mode (port
, ECR_TST
);
894 /* Adjust for the contents of the FIFO. */
895 for (written
-= priv
->fifo_depth
; ; written
++) {
896 if (inb (ECONTROL (port
)) & 0x2) {
900 outb (0, FIFO (port
));
903 /* Reset the FIFO and return to PS2 mode. */
904 frob_set_mode (port
, ECR_PS2
);
906 /* Host transfer recovery. */
907 parport_pc_data_reverse (port
); /* Must be in PS2 mode */
909 parport_frob_control (port
, PARPORT_CONTROL_INIT
, 0);
910 r
= parport_wait_peripheral (port
, PARPORT_STATUS_PAPEROUT
, 0);
912 printk (KERN_DEBUG
"%s: PE,1 timeout (%d) "
913 "in ecp_write_block_pio\n", port
->name
, r
);
915 parport_frob_control (port
,
916 PARPORT_CONTROL_INIT
,
917 PARPORT_CONTROL_INIT
);
918 r
= parport_wait_peripheral (port
,
919 PARPORT_STATUS_PAPEROUT
,
920 PARPORT_STATUS_PAPEROUT
);
922 printk (KERN_DEBUG
"%s: PE,2 timeout (%d) "
923 "in ecp_write_block_pio\n", port
->name
, r
);
926 r
= parport_wait_peripheral (port
,
928 PARPORT_STATUS_BUSY
);
931 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
934 port
->physport
->ieee1284
.phase
= IEEE1284_PH_FWD_IDLE
;
940 static size_t parport_pc_ecp_read_block_pio (struct parport
*port
,
941 void *buf
, size_t length
,
944 size_t left
= length
;
947 const int fifo
= FIFO(port
);
948 const struct parport_pc_private
*priv
= port
->physport
->private_data
;
949 const int fifo_depth
= priv
->fifo_depth
;
952 port
= port
->physport
;
953 DPRINTK (KERN_DEBUG
"parport_pc: parport_pc_ecp_read_block_pio\n");
954 dump_parport_state ("enter fcn", port
);
956 /* Special case: a timeout of zero means we cannot call schedule().
957 * Also if O_NONBLOCK is set then use the default implementation. */
958 if (port
->cad
->timeout
<= PARPORT_INACTIVITY_O_NONBLOCK
)
959 return parport_ieee1284_ecp_read_data (port
, buf
,
962 if (port
->ieee1284
.mode
== IEEE1284_MODE_ECPRLE
) {
963 /* If the peripheral is allowed to send RLE compressed
964 * data, it is possible for a byte to expand to 128
965 * bytes in the FIFO. */
968 fifofull
= fifo_depth
;
971 /* If the caller wants less than a full FIFO's worth of data,
972 * go through software emulation. Otherwise we may have to throw
974 if (length
< fifofull
)
975 return parport_ieee1284_ecp_read_data (port
, buf
,
978 if (port
->ieee1284
.phase
!= IEEE1284_PH_REV_IDLE
) {
979 /* change to reverse-idle phase (must be in forward-idle) */
981 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
982 parport_frob_control (port
,
983 PARPORT_CONTROL_AUTOFD
984 | PARPORT_CONTROL_STROBE
,
985 PARPORT_CONTROL_AUTOFD
);
986 parport_pc_data_reverse (port
); /* Must be in PS2 mode */
988 /* Event 39: Set nInit low to initiate bus reversal */
989 parport_frob_control (port
,
990 PARPORT_CONTROL_INIT
,
992 /* Event 40: Wait for nAckReverse (PError) to go low */
993 r
= parport_wait_peripheral (port
, PARPORT_STATUS_PAPEROUT
, 0);
995 printk (KERN_DEBUG
"%s: PE timeout Event 40 (%d) "
996 "in ecp_read_block_pio\n", port
->name
, r
);
1001 /* Set up ECP FIFO mode.*/
1002 /* parport_pc_frob_control (port,
1003 PARPORT_CONTROL_STROBE |
1004 PARPORT_CONTROL_AUTOFD,
1005 PARPORT_CONTROL_AUTOFD); */
1006 r
= change_mode (port
, ECR_ECP
); /* ECP FIFO */
1007 if (r
) printk (KERN_DEBUG
"%s: Warning change_mode ECR_ECP failed\n", port
->name
);
1009 port
->ieee1284
.phase
= IEEE1284_PH_REV_DATA
;
1011 /* the first byte must be collected manually */
1012 dump_parport_state ("pre 43", port
);
1013 /* Event 43: Wait for nAck to go low */
1014 r
= parport_wait_peripheral (port
, PARPORT_STATUS_ACK
, 0);
1016 /* timed out while reading -- no data */
1017 printk (KERN_DEBUG
"PIO read timed out (initial byte)\n");
1021 *bufp
++ = inb (DATA (port
));
1023 dump_parport_state ("43-44", port
);
1024 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1025 parport_pc_frob_control (port
,
1026 PARPORT_CONTROL_AUTOFD
,
1028 dump_parport_state ("pre 45", port
);
1029 /* Event 45: Wait for nAck to go high */
1030 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1031 dump_parport_state ("post 45", port
);
1034 /* timed out while waiting for peripheral to respond to ack */
1035 printk (KERN_DEBUG
"ECP PIO read timed out (waiting for nAck)\n");
1037 /* keep hold of the byte we've got already */
1040 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1041 parport_pc_frob_control (port
,
1042 PARPORT_CONTROL_AUTOFD
,
1043 PARPORT_CONTROL_AUTOFD
);
1046 dump_parport_state ("rev idle", port
);
1047 /* Do the transfer. */
1048 while (left
> fifofull
) {
1050 unsigned long expire
= jiffies
+ port
->cad
->timeout
;
1051 unsigned char ecrval
= inb (ECONTROL (port
));
1053 if (need_resched() && time_before (jiffies
, expire
))
1054 /* Can't yield the port. */
1057 /* At this point, the FIFO may already be full. In
1058 * that case ECP is already holding back the
1059 * peripheral (assuming proper design) with a delayed
1060 * handshake. Work fast to avoid a peripheral
1063 if (ecrval
& 0x01) {
1064 /* FIFO is empty. Wait for interrupt. */
1065 dump_parport_state ("FIFO empty", port
);
1067 /* Anyone else waiting for the port? */
1068 if (port
->waithead
) {
1069 printk (KERN_DEBUG
"Somebody wants the port\n");
1073 /* Clear serviceIntr */
1074 ECR_WRITE (port
, ecrval
& ~(1<<2));
1076 dump_parport_state ("waiting", port
);
1077 ret
= parport_wait_event (port
, HZ
);
1078 DPRINTK (KERN_DEBUG
"parport_wait_event returned %d\n", ret
);
1082 if (!time_before (jiffies
, expire
)) {
1084 dump_parport_state ("timeout", port
);
1085 printk (KERN_DEBUG
"PIO read timed out\n");
1088 ecrval
= inb (ECONTROL (port
));
1089 if (!(ecrval
& (1<<2))) {
1090 if (need_resched() &&
1091 time_before (jiffies
, expire
)) {
1097 /* Depending on how the FIFO threshold was
1098 * set, how long interrupt service took, and
1099 * how fast the peripheral is, we might be
1100 * lucky and have a just filled FIFO. */
1104 if (ecrval
& 0x02) {
1106 dump_parport_state ("FIFO full", port
);
1107 insb (fifo
, bufp
, fifo_depth
);
1113 DPRINTK (KERN_DEBUG
"*** ecp_read_block_pio: reading one byte from the FIFO\n");
1115 /* FIFO not filled. We will cycle this loop for a while
1116 * and either the peripheral will fill it faster,
1117 * tripping a fast empty with insb, or we empty it. */
1118 *bufp
++ = inb (fifo
);
1122 /* scoop up anything left in the FIFO */
1123 while (left
&& !(inb (ECONTROL (port
) & 0x01))) {
1124 *bufp
++ = inb (fifo
);
1128 port
->ieee1284
.phase
= IEEE1284_PH_REV_IDLE
;
1129 dump_parport_state ("rev idle2", port
);
1133 /* Go to forward idle mode to shut the peripheral up (event 47). */
1134 parport_frob_control (port
, PARPORT_CONTROL_INIT
, PARPORT_CONTROL_INIT
);
1136 /* event 49: PError goes high */
1137 r
= parport_wait_peripheral (port
,
1138 PARPORT_STATUS_PAPEROUT
,
1139 PARPORT_STATUS_PAPEROUT
);
1142 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1146 port
->ieee1284
.phase
= IEEE1284_PH_FWD_IDLE
;
1150 int lost
= get_fifo_residue (port
);
1152 /* Shouldn't happen with compliant peripherals. */
1153 printk (KERN_DEBUG
"%s: DATA LOSS (%d bytes)!\n",
1157 dump_parport_state ("fwd idle", port
);
1158 return length
- left
;
1161 #endif /* IEEE 1284 support */
1162 #endif /* Allowed to use FIFO/DMA */
1166 * ******************************************
1167 * INITIALISATION AND MODULE STUFF BELOW HERE
1168 * ******************************************
1171 /* GCC is not inlining extern inline function later overwriten to non-inline,
1172 so we use outlined_ variants here. */
1173 static const struct parport_operations parport_pc_ops
=
1175 .write_data
= parport_pc_write_data
,
1176 .read_data
= parport_pc_read_data
,
1178 .write_control
= parport_pc_write_control
,
1179 .read_control
= parport_pc_read_control
,
1180 .frob_control
= parport_pc_frob_control
,
1182 .read_status
= parport_pc_read_status
,
1184 .enable_irq
= parport_pc_enable_irq
,
1185 .disable_irq
= parport_pc_disable_irq
,
1187 .data_forward
= parport_pc_data_forward
,
1188 .data_reverse
= parport_pc_data_reverse
,
1190 .init_state
= parport_pc_init_state
,
1191 .save_state
= parport_pc_save_state
,
1192 .restore_state
= parport_pc_restore_state
,
1194 .epp_write_data
= parport_ieee1284_epp_write_data
,
1195 .epp_read_data
= parport_ieee1284_epp_read_data
,
1196 .epp_write_addr
= parport_ieee1284_epp_write_addr
,
1197 .epp_read_addr
= parport_ieee1284_epp_read_addr
,
1199 .ecp_write_data
= parport_ieee1284_ecp_write_data
,
1200 .ecp_read_data
= parport_ieee1284_ecp_read_data
,
1201 .ecp_write_addr
= parport_ieee1284_ecp_write_addr
,
1203 .compat_write_data
= parport_ieee1284_write_compat
,
1204 .nibble_read_data
= parport_ieee1284_read_nibble
,
1205 .byte_read_data
= parport_ieee1284_read_byte
,
1207 .owner
= THIS_MODULE
,
1210 #ifdef CONFIG_PARPORT_PC_SUPERIO
1211 /* Super-IO chipset detection, Winbond, SMSC */
1212 static void __devinit
show_parconfig_smsc37c669(int io
, int key
)
1214 int cr1
,cr4
,cra
,cr23
,cr26
,cr27
,i
=0;
1215 static const char *const modes
[]={
1216 "SPP and Bidirectional (PS/2)",
1237 if (verbose_probing
) {
1238 printk (KERN_INFO
"SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1239 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1240 cr1
,cr4
,cra
,cr23
,cr26
,cr27
);
1242 /* The documentation calls DMA and IRQ-Lines by letters, so
1243 the board maker can/will wire them
1244 appropriately/randomly... G=reserved H=IDE-irq, */
1245 printk (KERN_INFO
"SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1246 "fifo threshold=%d\n", cr23
*4,
1247 (cr27
&0x0f) ? 'A'-1+(cr27
&0x0f): '-',
1248 (cr26
&0x0f) ? 'A'-1+(cr26
&0x0f): '-', cra
& 0x0f);
1249 printk(KERN_INFO
"SMSC LPT Config: enabled=%s power=%s\n",
1250 (cr23
*4 >=0x100) ?"yes":"no", (cr1
& 4) ? "yes" : "no");
1251 printk(KERN_INFO
"SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1252 (cr1
& 0x08 ) ? "Standard mode only (SPP)" : modes
[cr4
& 0x03],
1253 (cr4
& 0x40) ? "1.7" : "1.9");
1256 /* Heuristics ! BIOS setup for this mainboard device limits
1257 the choices to standard settings, i.e. io-address and IRQ
1258 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1259 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1260 if(cr23
*4 >=0x100) { /* if active */
1261 while((superios
[i
].io
!= 0) && (i
<NR_SUPERIOS
))
1264 printk(KERN_INFO
"Super-IO: too many chips!\n");
1269 superios
[i
].io
= 0x3bc;
1270 superios
[i
].irq
= 7;
1273 superios
[i
].io
= 0x378;
1274 superios
[i
].irq
= 7;
1277 superios
[i
].io
= 0x278;
1278 superios
[i
].irq
= 5;
1281 if((d
==1) || (d
==3))
1284 superios
[i
].dma
= PARPORT_DMA_NONE
;
1290 static void __devinit
show_parconfig_winbond(int io
, int key
)
1292 int cr30
,cr60
,cr61
,cr70
,cr74
,crf0
,i
=0;
1293 static const char *const modes
[] = {
1294 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1299 "EPP-1.7 and SPP", /* 5 */
1301 "ECP and EPP-1.7" };
1302 static char *const irqtypes
[] = {
1303 "pulsed low, high-Z",
1306 /* The registers are called compatible-PnP because the
1307 register layout is modelled after ISA-PnP, the access
1308 method is just another ... */
1311 outb(0x07,io
); /* Register 7: Select Logical Device */
1312 outb(0x01,io
+1); /* LD1 is Parallel Port */
1327 if (verbose_probing
) {
1328 printk(KERN_INFO
"Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1329 "70=%02x 74=%02x, f0=%02x\n", cr30
,cr60
,cr61
,cr70
,cr74
,crf0
);
1330 printk(KERN_INFO
"Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1331 (cr30
& 0x01) ? "yes":"no", cr60
,cr61
,cr70
&0x0f );
1332 if ((cr74
& 0x07) > 3)
1333 printk("dma=none\n");
1335 printk("dma=%d\n",cr74
& 0x07);
1336 printk(KERN_INFO
"Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1337 irqtypes
[crf0
>>7], (crf0
>>3)&0x0f);
1338 printk(KERN_INFO
"Winbond LPT Config: Port mode=%s\n", modes
[crf0
& 0x07]);
1341 if(cr30
& 0x01) { /* the settings can be interrogated later ... */
1342 while((superios
[i
].io
!= 0) && (i
<NR_SUPERIOS
))
1345 printk(KERN_INFO
"Super-IO: too many chips!\n");
1347 superios
[i
].io
= (cr60
<<8)|cr61
;
1348 superios
[i
].irq
= cr70
&0x0f;
1349 superios
[i
].dma
= (((cr74
& 0x07) > 3) ?
1350 PARPORT_DMA_NONE
: (cr74
& 0x07));
1355 static void __devinit
decode_winbond(int efer
, int key
, int devid
, int devrev
, int oldid
)
1357 const char *type
= "unknown";
1360 if (devid
== devrev
)
1361 /* simple heuristics, we happened to read some
1362 non-winbond register */
1365 id
=(devid
<<8) | devrev
;
1367 /* Values are from public data sheets pdf files, I can just
1368 confirm 83977TF is correct :-) */
1369 if (id
== 0x9771) type
="83977F/AF";
1370 else if (id
== 0x9773) type
="83977TF / SMSC 97w33x/97w34x";
1371 else if (id
== 0x9774) type
="83977ATF";
1372 else if ((id
& ~0x0f) == 0x5270) type
="83977CTF / SMSC 97w36x";
1373 else if ((id
& ~0x0f) == 0x52f0) type
="83977EF / SMSC 97w35x";
1374 else if ((id
& ~0x0f) == 0x5210) type
="83627";
1375 else if ((id
& ~0x0f) == 0x6010) type
="83697HF";
1376 else if ((oldid
&0x0f ) == 0x0a) { type
="83877F"; progif
=1;}
1377 else if ((oldid
&0x0f ) == 0x0b) { type
="83877AF"; progif
=1;}
1378 else if ((oldid
&0x0f ) == 0x0c) { type
="83877TF"; progif
=1;}
1379 else if ((oldid
&0x0f ) == 0x0d) { type
="83877ATF"; progif
=1;}
1382 if (verbose_probing
)
1383 printk(KERN_INFO
"Winbond chip at EFER=0x%x key=0x%02x "
1384 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1385 efer
, key
, devid
, devrev
, oldid
, type
);
1388 show_parconfig_winbond(efer
,key
);
1391 static void __devinit
decode_smsc(int efer
, int key
, int devid
, int devrev
)
1393 const char *type
= "unknown";
1394 void (*func
)(int io
, int key
);
1397 if (devid
== devrev
)
1398 /* simple heuristics, we happened to read some
1399 non-smsc register */
1403 id
=(devid
<<8) | devrev
;
1405 if (id
==0x0302) {type
="37c669"; func
=show_parconfig_smsc37c669
;}
1406 else if (id
==0x6582) type
="37c665IR";
1407 else if (devid
==0x65) type
="37c665GT";
1408 else if (devid
==0x66) type
="37c666GT";
1410 if (verbose_probing
)
1411 printk(KERN_INFO
"SMSC chip at EFER=0x%x "
1412 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1413 efer
, key
, devid
, devrev
, type
);
1420 static void __devinit
winbond_check(int io
, int key
)
1422 int devid
,devrev
,oldid
,x_devid
,x_devrev
,x_oldid
;
1424 if (!request_region(io
, 3, __FUNCTION__
))
1427 /* First probe without key */
1436 outb(key
,io
); /* Write Magic Sequence to EFER, extended
1437 funtion enable register */
1438 outb(0x20,io
); /* Write EFIR, extended function index register */
1439 devid
=inb(io
+1); /* Read EFDR, extended function data register */
1444 outb(0xaa,io
); /* Magic Seal */
1446 if ((x_devid
== devid
) && (x_devrev
== devrev
) && (x_oldid
== oldid
))
1447 goto out
; /* protection against false positives */
1449 decode_winbond(io
,key
,devid
,devrev
,oldid
);
1451 release_region(io
, 3);
1454 static void __devinit
winbond_check2(int io
,int key
)
1456 int devid
,devrev
,oldid
,x_devid
,x_devrev
,x_oldid
;
1458 if (!request_region(io
, 3, __FUNCTION__
))
1461 /* First probe without the key */
1469 outb(key
,io
); /* Write Magic Byte to EFER, extended
1470 funtion enable register */
1471 outb(0x20,io
+2); /* Write EFIR, extended function index register */
1472 devid
=inb(io
+2); /* Read EFDR, extended function data register */
1477 outb(0xaa,io
); /* Magic Seal */
1479 if ((x_devid
== devid
) && (x_devrev
== devrev
) && (x_oldid
== oldid
))
1480 goto out
; /* protection against false positives */
1482 decode_winbond(io
,key
,devid
,devrev
,oldid
);
1484 release_region(io
, 3);
1487 static void __devinit
smsc_check(int io
, int key
)
1489 int id
,rev
,oldid
,oldrev
,x_id
,x_rev
,x_oldid
,x_oldrev
;
1491 if (!request_region(io
, 3, __FUNCTION__
))
1494 /* First probe without the key */
1505 outb(key
,io
); /* Write Magic Sequence to EFER, extended
1506 funtion enable register */
1507 outb(0x0d,io
); /* Write EFIR, extended function index register */
1508 oldid
=inb(io
+1); /* Read EFDR, extended function data register */
1515 outb(0xaa,io
); /* Magic Seal */
1517 if ((x_id
== id
) && (x_oldrev
== oldrev
) &&
1518 (x_oldid
== oldid
) && (x_rev
== rev
))
1519 goto out
; /* protection against false positives */
1521 decode_smsc(io
,key
,oldid
,oldrev
);
1523 release_region(io
, 3);
1527 static void __devinit
detect_and_report_winbond (void)
1529 if (verbose_probing
)
1530 printk(KERN_DEBUG
"Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1531 winbond_check(0x3f0,0x87);
1532 winbond_check(0x370,0x87);
1533 winbond_check(0x2e ,0x87);
1534 winbond_check(0x4e ,0x87);
1535 winbond_check(0x3f0,0x86);
1536 winbond_check2(0x250,0x88);
1537 winbond_check2(0x250,0x89);
1540 static void __devinit
detect_and_report_smsc (void)
1542 if (verbose_probing
)
1543 printk(KERN_DEBUG
"SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1544 smsc_check(0x3f0,0x55);
1545 smsc_check(0x370,0x55);
1546 smsc_check(0x3f0,0x44);
1547 smsc_check(0x370,0x44);
1549 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1551 static int get_superio_dma (struct parport
*p
)
1554 while( (superios
[i
].io
!= p
->base
) && (i
<NR_SUPERIOS
))
1557 return superios
[i
].dma
;
1558 return PARPORT_DMA_NONE
;
1561 static int get_superio_irq (struct parport
*p
)
1564 while( (superios
[i
].io
!= p
->base
) && (i
<NR_SUPERIOS
))
1567 return superios
[i
].irq
;
1568 return PARPORT_IRQ_NONE
;
1572 /* --- Mode detection ------------------------------------- */
1575 * Checks for port existence, all ports support SPP MODE
1577 * 0 : No parallel port at this address
1578 * PARPORT_MODE_PCSPP : SPP port detected
1579 * (if the user specified an ioport himself,
1580 * this shall always be the case!)
1583 static int parport_SPP_supported(struct parport
*pb
)
1588 * first clear an eventually pending EPP timeout
1589 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1590 * that does not even respond to SPP cycles if an EPP
1591 * timeout is pending
1593 clear_epp_timeout(pb
);
1595 /* Do a simple read-write test to make sure the port exists. */
1597 outb (w
, CONTROL (pb
));
1599 /* Is there a control register that we can read from? Some
1600 * ports don't allow reads, so read_control just returns a
1601 * software copy. Some ports _do_ allow reads, so bypass the
1602 * software copy here. In addition, some bits aren't
1604 r
= inb (CONTROL (pb
));
1605 if ((r
& 0xf) == w
) {
1607 outb (w
, CONTROL (pb
));
1608 r
= inb (CONTROL (pb
));
1609 outb (0xc, CONTROL (pb
));
1611 return PARPORT_MODE_PCSPP
;
1615 /* That didn't work, but the user thinks there's a
1617 printk (KERN_INFO
"parport 0x%lx (WARNING): CTR: "
1618 "wrote 0x%02x, read 0x%02x\n", pb
->base
, w
, r
);
1620 /* Try the data register. The data lines aren't tri-stated at
1621 * this stage, so we expect back what we wrote. */
1623 parport_pc_write_data (pb
, w
);
1624 r
= parport_pc_read_data (pb
);
1627 parport_pc_write_data (pb
, w
);
1628 r
= parport_pc_read_data (pb
);
1630 return PARPORT_MODE_PCSPP
;
1633 if (user_specified
) {
1634 /* Didn't work, but the user is convinced this is the
1636 printk (KERN_INFO
"parport 0x%lx (WARNING): DATA: "
1637 "wrote 0x%02x, read 0x%02x\n", pb
->base
, w
, r
);
1638 printk (KERN_INFO
"parport 0x%lx: You gave this address, "
1639 "but there is probably no parallel port there!\n",
1643 /* It's possible that we can't read the control register or
1644 * the data register. In that case just believe the user. */
1646 return PARPORT_MODE_PCSPP
;
1653 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1654 * on these cards actually accesses the CTR.
1656 * Modern cards don't do this but reading from ECR will return 0xff
1657 * regardless of what is written here if the card does NOT support
1660 * We first check to see if ECR is the same as CTR. If not, the low
1661 * two bits of ECR aren't writable, so we check by writing ECR and
1662 * reading it back to see if it's what we expect.
1664 static int parport_ECR_present(struct parport
*pb
)
1666 struct parport_pc_private
*priv
= pb
->private_data
;
1667 unsigned char r
= 0xc;
1669 outb (r
, CONTROL (pb
));
1670 if ((inb (ECONTROL (pb
)) & 0x3) == (r
& 0x3)) {
1671 outb (r
^ 0x2, CONTROL (pb
)); /* Toggle bit 1 */
1673 r
= inb (CONTROL (pb
));
1674 if ((inb (ECONTROL (pb
)) & 0x2) == (r
& 0x2))
1675 goto no_reg
; /* Sure that no ECR register exists */
1678 if ((inb (ECONTROL (pb
)) & 0x3 ) != 0x1)
1681 ECR_WRITE (pb
, 0x34);
1682 if (inb (ECONTROL (pb
)) != 0x35)
1686 outb (0xc, CONTROL (pb
));
1688 /* Go to mode 000 */
1689 frob_set_mode (pb
, ECR_SPP
);
1694 outb (0xc, CONTROL (pb
));
1698 #ifdef CONFIG_PARPORT_1284
1699 /* Detect PS/2 support.
1701 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1702 * allows us to read data from the data lines. In theory we would get back
1703 * 0xff but any peripheral attached to the port may drag some or all of the
1704 * lines down to zero. So if we get back anything that isn't the contents
1705 * of the data register we deem PS/2 support to be present.
1707 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1708 * drivers, but an external peripheral with sufficiently beefy drivers of
1709 * its own can overpower them and assert its own levels onto the bus, from
1710 * where they can then be read back as normal. Ports with this property
1711 * and the right type of device attached are likely to fail the SPP test,
1712 * (as they will appear to have stuck bits) and so the fact that they might
1713 * be misdetected here is rather academic.
1716 static int parport_PS2_supported(struct parport
*pb
)
1720 clear_epp_timeout(pb
);
1722 /* try to tri-state the buffer */
1723 parport_pc_data_reverse (pb
);
1725 parport_pc_write_data(pb
, 0x55);
1726 if (parport_pc_read_data(pb
) != 0x55) ok
++;
1728 parport_pc_write_data(pb
, 0xaa);
1729 if (parport_pc_read_data(pb
) != 0xaa) ok
++;
1731 /* cancel input mode */
1732 parport_pc_data_forward (pb
);
1735 pb
->modes
|= PARPORT_MODE_TRISTATE
;
1737 struct parport_pc_private
*priv
= pb
->private_data
;
1738 priv
->ctr_writable
&= ~0x20;
1744 #ifdef CONFIG_PARPORT_PC_FIFO
1745 static int __devinit
parport_ECP_supported(struct parport
*pb
)
1748 int config
, configb
;
1750 struct parport_pc_private
*priv
= pb
->private_data
;
1751 /* Translate ECP intrLine to ISA irq value */
1752 static const int intrline
[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1754 /* If there is no ECR, we have no hope of supporting ECP. */
1758 /* Find out FIFO depth */
1759 ECR_WRITE (pb
, ECR_SPP
<< 5); /* Reset FIFO */
1760 ECR_WRITE (pb
, ECR_TST
<< 5); /* TEST FIFO */
1761 for (i
=0; i
< 1024 && !(inb (ECONTROL (pb
)) & 0x02); i
++)
1762 outb (0xaa, FIFO (pb
));
1765 * Using LGS chipset it uses ECR register, but
1766 * it doesn't support ECP or FIFO MODE
1769 ECR_WRITE (pb
, ECR_SPP
<< 5);
1773 priv
->fifo_depth
= i
;
1774 if (verbose_probing
)
1775 printk (KERN_DEBUG
"0x%lx: FIFO is %d bytes\n", pb
->base
, i
);
1777 /* Find out writeIntrThreshold */
1778 frob_econtrol (pb
, 1<<2, 1<<2);
1779 frob_econtrol (pb
, 1<<2, 0);
1780 for (i
= 1; i
<= priv
->fifo_depth
; i
++) {
1783 if (inb (ECONTROL (pb
)) & (1<<2))
1787 if (i
<= priv
->fifo_depth
) {
1788 if (verbose_probing
)
1789 printk (KERN_DEBUG
"0x%lx: writeIntrThreshold is %d\n",
1792 /* Number of bytes we know we can write if we get an
1796 priv
->writeIntrThreshold
= i
;
1798 /* Find out readIntrThreshold */
1799 frob_set_mode (pb
, ECR_PS2
); /* Reset FIFO and enable PS2 */
1800 parport_pc_data_reverse (pb
); /* Must be in PS2 mode */
1801 frob_set_mode (pb
, ECR_TST
); /* Test FIFO */
1802 frob_econtrol (pb
, 1<<2, 1<<2);
1803 frob_econtrol (pb
, 1<<2, 0);
1804 for (i
= 1; i
<= priv
->fifo_depth
; i
++) {
1805 outb (0xaa, FIFO (pb
));
1806 if (inb (ECONTROL (pb
)) & (1<<2))
1810 if (i
<= priv
->fifo_depth
) {
1811 if (verbose_probing
)
1812 printk (KERN_INFO
"0x%lx: readIntrThreshold is %d\n",
1815 /* Number of bytes we can read if we get an interrupt. */
1818 priv
->readIntrThreshold
= i
;
1820 ECR_WRITE (pb
, ECR_SPP
<< 5); /* Reset FIFO */
1821 ECR_WRITE (pb
, 0xf4); /* Configuration mode */
1822 config
= inb (CONFIGA (pb
));
1823 pword
= (config
>> 4) & 0x7;
1827 printk (KERN_WARNING
"0x%lx: Unsupported pword size!\n",
1832 printk (KERN_WARNING
"0x%lx: Unsupported pword size!\n",
1836 printk (KERN_WARNING
"0x%lx: Unknown implementation ID\n",
1842 priv
->pword
= pword
;
1844 if (verbose_probing
) {
1845 printk (KERN_DEBUG
"0x%lx: PWord is %d bits\n", pb
->base
, 8 * pword
);
1847 printk (KERN_DEBUG
"0x%lx: Interrupts are ISA-%s\n", pb
->base
,
1848 config
& 0x80 ? "Level" : "Pulses");
1850 configb
= inb (CONFIGB (pb
));
1851 printk (KERN_DEBUG
"0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1852 pb
->base
, config
, configb
);
1853 printk (KERN_DEBUG
"0x%lx: ECP settings irq=", pb
->base
);
1854 if ((configb
>>3) & 0x07)
1855 printk("%d",intrline
[(configb
>>3) & 0x07]);
1857 printk("<none or set by other means>");
1859 if( (configb
& 0x03 ) == 0x00)
1860 printk("<none or set by other means>\n");
1862 printk("%d\n",configb
& 0x07);
1865 /* Go back to mode 000 */
1866 frob_set_mode (pb
, ECR_SPP
);
1872 static int parport_ECPPS2_supported(struct parport
*pb
)
1874 const struct parport_pc_private
*priv
= pb
->private_data
;
1881 oecr
= inb (ECONTROL (pb
));
1882 ECR_WRITE (pb
, ECR_PS2
<< 5);
1883 result
= parport_PS2_supported(pb
);
1884 ECR_WRITE (pb
, oecr
);
1888 /* EPP mode detection */
1890 static int parport_EPP_supported(struct parport
*pb
)
1892 const struct parport_pc_private
*priv
= pb
->private_data
;
1896 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1897 * when EPP is possible and is set high when an EPP timeout
1898 * occurs (EPP uses the HALT line to stop the CPU while it does
1899 * the byte transfer, an EPP timeout occurs if the attached
1900 * device fails to respond after 10 micro seconds).
1902 * This bit is cleared by either reading it (National Semi)
1903 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1904 * This bit is always high in non EPP modes.
1907 /* If EPP timeout bit clear then EPP available */
1908 if (!clear_epp_timeout(pb
)) {
1909 return 0; /* No way to clear timeout */
1912 /* Check for Intel bug. */
1915 for (i
= 0x00; i
< 0x80; i
+= 0x20) {
1917 if (clear_epp_timeout (pb
)) {
1918 /* Phony EPP in ECP. */
1924 pb
->modes
|= PARPORT_MODE_EPP
;
1926 /* Set up access functions to use EPP hardware. */
1927 pb
->ops
->epp_read_data
= parport_pc_epp_read_data
;
1928 pb
->ops
->epp_write_data
= parport_pc_epp_write_data
;
1929 pb
->ops
->epp_read_addr
= parport_pc_epp_read_addr
;
1930 pb
->ops
->epp_write_addr
= parport_pc_epp_write_addr
;
1935 static int parport_ECPEPP_supported(struct parport
*pb
)
1937 struct parport_pc_private
*priv
= pb
->private_data
;
1945 oecr
= inb (ECONTROL (pb
));
1946 /* Search for SMC style EPP+ECP mode */
1947 ECR_WRITE (pb
, 0x80);
1948 outb (0x04, CONTROL (pb
));
1949 result
= parport_EPP_supported(pb
);
1951 ECR_WRITE (pb
, oecr
);
1954 /* Set up access functions to use ECP+EPP hardware. */
1955 pb
->ops
->epp_read_data
= parport_pc_ecpepp_read_data
;
1956 pb
->ops
->epp_write_data
= parport_pc_ecpepp_write_data
;
1957 pb
->ops
->epp_read_addr
= parport_pc_ecpepp_read_addr
;
1958 pb
->ops
->epp_write_addr
= parport_pc_ecpepp_write_addr
;
1964 #else /* No IEEE 1284 support */
1966 /* Don't bother probing for modes we know we won't use. */
1967 static int __devinit
parport_PS2_supported(struct parport
*pb
) { return 0; }
1968 #ifdef CONFIG_PARPORT_PC_FIFO
1969 static int __devinit
parport_ECP_supported(struct parport
*pb
) { return 0; }
1971 static int __devinit
parport_EPP_supported(struct parport
*pb
) { return 0; }
1972 static int __devinit
parport_ECPEPP_supported(struct parport
*pb
){return 0;}
1973 static int __devinit
parport_ECPPS2_supported(struct parport
*pb
){return 0;}
1975 #endif /* No IEEE 1284 support */
1977 /* --- IRQ detection -------------------------------------- */
1979 /* Only if supports ECP mode */
1980 static int programmable_irq_support(struct parport
*pb
)
1983 unsigned char oecr
= inb (ECONTROL (pb
));
1984 static const int lookup
[8] = {
1985 PARPORT_IRQ_NONE
, 7, 9, 10, 11, 14, 15, 5
1988 ECR_WRITE (pb
, ECR_CNF
<< 5); /* Configuration MODE */
1990 intrLine
= (inb (CONFIGB (pb
)) >> 3) & 0x07;
1991 irq
= lookup
[intrLine
];
1993 ECR_WRITE (pb
, oecr
);
1997 static int irq_probe_ECP(struct parport
*pb
)
2002 irqs
= probe_irq_on();
2004 ECR_WRITE (pb
, ECR_SPP
<< 5); /* Reset FIFO */
2005 ECR_WRITE (pb
, (ECR_TST
<< 5) | 0x04);
2006 ECR_WRITE (pb
, ECR_TST
<< 5);
2008 /* If Full FIFO sure that writeIntrThreshold is generated */
2009 for (i
=0; i
< 1024 && !(inb (ECONTROL (pb
)) & 0x02) ; i
++)
2010 outb (0xaa, FIFO (pb
));
2012 pb
->irq
= probe_irq_off(irqs
);
2013 ECR_WRITE (pb
, ECR_SPP
<< 5);
2016 pb
->irq
= PARPORT_IRQ_NONE
;
2022 * This detection seems that only works in National Semiconductors
2023 * This doesn't work in SMC, LGS, and Winbond
2025 static int irq_probe_EPP(struct parport
*pb
)
2027 #ifndef ADVANCED_DETECT
2028 return PARPORT_IRQ_NONE
;
2033 if (pb
->modes
& PARPORT_MODE_PCECR
)
2034 oecr
= inb (ECONTROL (pb
));
2036 irqs
= probe_irq_on();
2038 if (pb
->modes
& PARPORT_MODE_PCECR
)
2039 frob_econtrol (pb
, 0x10, 0x10);
2041 clear_epp_timeout(pb
);
2042 parport_pc_frob_control (pb
, 0x20, 0x20);
2043 parport_pc_frob_control (pb
, 0x10, 0x10);
2044 clear_epp_timeout(pb
);
2046 /* Device isn't expecting an EPP read
2047 * and generates an IRQ.
2049 parport_pc_read_epp(pb
);
2052 pb
->irq
= probe_irq_off (irqs
);
2053 if (pb
->modes
& PARPORT_MODE_PCECR
)
2054 ECR_WRITE (pb
, oecr
);
2055 parport_pc_write_control(pb
, 0xc);
2058 pb
->irq
= PARPORT_IRQ_NONE
;
2061 #endif /* Advanced detection */
2064 static int irq_probe_SPP(struct parport
*pb
)
2066 /* Don't even try to do this. */
2067 return PARPORT_IRQ_NONE
;
2070 /* We will attempt to share interrupt requests since other devices
2071 * such as sound cards and network cards seem to like using the
2074 * When ECP is available we can autoprobe for IRQs.
2075 * NOTE: If we can autoprobe it, we can register the IRQ.
2077 static int parport_irq_probe(struct parport
*pb
)
2079 struct parport_pc_private
*priv
= pb
->private_data
;
2082 pb
->irq
= programmable_irq_support(pb
);
2084 if (pb
->irq
== PARPORT_IRQ_NONE
)
2085 pb
->irq
= irq_probe_ECP(pb
);
2088 if ((pb
->irq
== PARPORT_IRQ_NONE
) && priv
->ecr
&&
2089 (pb
->modes
& PARPORT_MODE_EPP
))
2090 pb
->irq
= irq_probe_EPP(pb
);
2092 clear_epp_timeout(pb
);
2094 if (pb
->irq
== PARPORT_IRQ_NONE
&& (pb
->modes
& PARPORT_MODE_EPP
))
2095 pb
->irq
= irq_probe_EPP(pb
);
2097 clear_epp_timeout(pb
);
2099 if (pb
->irq
== PARPORT_IRQ_NONE
)
2100 pb
->irq
= irq_probe_SPP(pb
);
2102 if (pb
->irq
== PARPORT_IRQ_NONE
)
2103 pb
->irq
= get_superio_irq(pb
);
2108 /* --- DMA detection -------------------------------------- */
2110 /* Only if chipset conforms to ECP ISA Interface Standard */
2111 static int programmable_dma_support (struct parport
*p
)
2113 unsigned char oecr
= inb (ECONTROL (p
));
2116 frob_set_mode (p
, ECR_CNF
);
2118 dma
= inb (CONFIGB(p
)) & 0x07;
2119 /* 000: Indicates jumpered 8-bit DMA if read-only.
2120 100: Indicates jumpered 16-bit DMA if read-only. */
2121 if ((dma
& 0x03) == 0)
2122 dma
= PARPORT_DMA_NONE
;
2124 ECR_WRITE (p
, oecr
);
2128 static int parport_dma_probe (struct parport
*p
)
2130 const struct parport_pc_private
*priv
= p
->private_data
;
2132 p
->dma
= programmable_dma_support(p
); /* ask ECP chipset first */
2133 if (p
->dma
== PARPORT_DMA_NONE
) {
2134 /* ask known Super-IO chips proper, although these
2135 claim ECP compatible, some don't report their DMA
2136 conforming to ECP standards */
2137 p
->dma
= get_superio_dma(p
);
2143 /* --- Initialisation code -------------------------------- */
2145 static LIST_HEAD(ports_list
);
2146 static DEFINE_SPINLOCK(ports_lock
);
2148 struct parport
*parport_pc_probe_port (unsigned long int base
,
2149 unsigned long int base_hi
,
2153 struct parport_pc_private
*priv
;
2154 struct parport_operations
*ops
;
2156 int probedirq
= PARPORT_IRQ_NONE
;
2157 struct resource
*base_res
;
2158 struct resource
*ECR_res
= NULL
;
2159 struct resource
*EPP_res
= NULL
;
2160 struct platform_device
*pdev
= NULL
;
2163 /* We need a physical device to attach to, but none was
2164 * provided. Create our own. */
2165 pdev
= platform_device_register_simple("parport_pc",
2172 ops
= kmalloc(sizeof (struct parport_operations
), GFP_KERNEL
);
2176 priv
= kmalloc (sizeof (struct parport_pc_private
), GFP_KERNEL
);
2180 /* a misnomer, actually - it's allocate and reserve parport number */
2181 p
= parport_register_port(base
, irq
, dma
, ops
);
2185 base_res
= request_region(base
, 3, p
->name
);
2189 memcpy(ops
, &parport_pc_ops
, sizeof (struct parport_operations
));
2191 priv
->ctr_writable
= ~0x10;
2193 priv
->fifo_depth
= 0;
2194 priv
->dma_buf
= NULL
;
2195 priv
->dma_handle
= 0;
2196 INIT_LIST_HEAD(&priv
->list
);
2200 p
->base_hi
= base_hi
;
2201 p
->modes
= PARPORT_MODE_PCSPP
| PARPORT_MODE_SAFEININT
;
2202 p
->private_data
= priv
;
2205 ECR_res
= request_region(base_hi
, 3, p
->name
);
2207 parport_ECR_present(p
);
2210 if (base
!= 0x3bc) {
2211 EPP_res
= request_region(base
+0x3, 5, p
->name
);
2213 if (!parport_EPP_supported(p
))
2214 parport_ECPEPP_supported(p
);
2216 if (!parport_SPP_supported (p
))
2220 parport_ECPPS2_supported(p
);
2222 parport_PS2_supported(p
);
2224 p
->size
= (p
->modes
& PARPORT_MODE_EPP
)?8:3;
2226 printk(KERN_INFO
"%s: PC-style at 0x%lx", p
->name
, p
->base
);
2227 if (p
->base_hi
&& priv
->ecr
)
2228 printk(" (0x%lx)", p
->base_hi
);
2229 if (p
->irq
== PARPORT_IRQ_AUTO
) {
2230 p
->irq
= PARPORT_IRQ_NONE
;
2231 parport_irq_probe(p
);
2232 } else if (p
->irq
== PARPORT_IRQ_PROBEONLY
) {
2233 p
->irq
= PARPORT_IRQ_NONE
;
2234 parport_irq_probe(p
);
2236 p
->irq
= PARPORT_IRQ_NONE
;
2238 if (p
->irq
!= PARPORT_IRQ_NONE
) {
2239 printk(", irq %d", p
->irq
);
2240 priv
->ctr_writable
|= 0x10;
2242 if (p
->dma
== PARPORT_DMA_AUTO
) {
2243 p
->dma
= PARPORT_DMA_NONE
;
2244 parport_dma_probe(p
);
2247 if (p
->dma
== PARPORT_DMA_AUTO
) /* To use DMA, giving the irq
2248 is mandatory (see above) */
2249 p
->dma
= PARPORT_DMA_NONE
;
2251 #ifdef CONFIG_PARPORT_PC_FIFO
2252 if (parport_ECP_supported(p
) &&
2253 p
->dma
!= PARPORT_DMA_NOFIFO
&&
2254 priv
->fifo_depth
> 0 && p
->irq
!= PARPORT_IRQ_NONE
) {
2255 p
->modes
|= PARPORT_MODE_ECP
| PARPORT_MODE_COMPAT
;
2256 p
->ops
->compat_write_data
= parport_pc_compat_write_block_pio
;
2257 #ifdef CONFIG_PARPORT_1284
2258 p
->ops
->ecp_write_data
= parport_pc_ecp_write_block_pio
;
2259 /* currently broken, but working on it.. (FB) */
2260 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2261 #endif /* IEEE 1284 support */
2262 if (p
->dma
!= PARPORT_DMA_NONE
) {
2263 printk(", dma %d", p
->dma
);
2264 p
->modes
|= PARPORT_MODE_DMA
;
2266 else printk(", using FIFO");
2269 /* We can't use the DMA channel after all. */
2270 p
->dma
= PARPORT_DMA_NONE
;
2271 #endif /* Allowed to use FIFO/DMA */
2274 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2278 printmode(TRISTATE
);
2285 #ifndef CONFIG_PARPORT_1284
2287 #endif /* CONFIG_PARPORT_1284 */
2289 if (probedirq
!= PARPORT_IRQ_NONE
)
2290 printk(KERN_INFO
"%s: irq %d detected\n", p
->name
, probedirq
);
2292 /* If No ECP release the ports grabbed above. */
2293 if (ECR_res
&& (p
->modes
& PARPORT_MODE_ECP
) == 0) {
2294 release_region(base_hi
, 3);
2297 /* Likewise for EEP ports */
2298 if (EPP_res
&& (p
->modes
& PARPORT_MODE_EPP
) == 0) {
2299 release_region(base
+3, 5);
2302 if (p
->irq
!= PARPORT_IRQ_NONE
) {
2303 if (request_irq (p
->irq
, parport_pc_interrupt
,
2305 printk (KERN_WARNING
"%s: irq %d in use, "
2306 "resorting to polled operation\n",
2308 p
->irq
= PARPORT_IRQ_NONE
;
2309 p
->dma
= PARPORT_DMA_NONE
;
2312 #ifdef CONFIG_PARPORT_PC_FIFO
2314 if (p
->dma
!= PARPORT_DMA_NONE
) {
2315 if (request_dma (p
->dma
, p
->name
)) {
2316 printk (KERN_WARNING
"%s: dma %d in use, "
2317 "resorting to PIO operation\n",
2319 p
->dma
= PARPORT_DMA_NONE
;
2322 dma_alloc_coherent(dev
,
2326 if (! priv
->dma_buf
) {
2327 printk (KERN_WARNING
"%s: "
2328 "cannot get buffer for DMA, "
2329 "resorting to PIO operation\n",
2332 p
->dma
= PARPORT_DMA_NONE
;
2340 /* Done probing. Now put the port into a sensible start-up state. */
2343 * Put the ECP detected port in PS2 mode.
2344 * Do this also for ports that have ECR but don't do ECP.
2346 ECR_WRITE (p
, 0x34);
2348 parport_pc_write_data(p
, 0);
2349 parport_pc_data_forward (p
);
2351 /* Now that we've told the sharing engine about the port, and
2352 found out its characteristics, let the high-level drivers
2354 spin_lock(&ports_lock
);
2355 list_add(&priv
->list
, &ports_list
);
2356 spin_unlock(&ports_lock
);
2357 parport_announce_port (p
);
2363 release_region(base_hi
, 3);
2365 release_region(base
+0x3, 5);
2366 release_region(base
, 3);
2368 parport_put_port(p
);
2375 platform_device_unregister(pdev
);
2379 EXPORT_SYMBOL (parport_pc_probe_port
);
2381 void parport_pc_unregister_port (struct parport
*p
)
2383 struct parport_pc_private
*priv
= p
->private_data
;
2384 struct parport_operations
*ops
= p
->ops
;
2386 parport_remove_port(p
);
2387 spin_lock(&ports_lock
);
2388 list_del_init(&priv
->list
);
2389 spin_unlock(&ports_lock
);
2390 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2391 if (p
->dma
!= PARPORT_DMA_NONE
)
2394 if (p
->irq
!= PARPORT_IRQ_NONE
)
2395 free_irq(p
->irq
, p
);
2396 release_region(p
->base
, 3);
2398 release_region(p
->base
+ 3, p
->size
- 3);
2399 if (p
->modes
& PARPORT_MODE_ECP
)
2400 release_region(p
->base_hi
, 3);
2401 #if defined(CONFIG_PARPORT_PC_FIFO) && defined(HAS_DMA)
2403 dma_free_coherent(p
->physport
->dev
, PAGE_SIZE
,
2407 kfree (p
->private_data
);
2408 parport_put_port(p
);
2409 kfree (ops
); /* hope no-one cached it */
2412 EXPORT_SYMBOL (parport_pc_unregister_port
);
2416 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2417 static int __devinit
sio_ite_8872_probe (struct pci_dev
*pdev
, int autoirq
,
2419 const struct parport_pc_via_data
*via
)
2421 short inta_addr
[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2422 struct resource
*base_res
;
2424 u32 ite8872_lpt
, ite8872_lpthi
;
2425 u8 ite8872_irq
, type
;
2426 char *fake_name
= "parport probe";
2430 DPRINTK (KERN_DEBUG
"sio_ite_8872_probe()\n");
2432 // make sure which one chip
2433 for(i
= 0; i
< 5; i
++) {
2434 base_res
= request_region(inta_addr
[i
], 0x8, fake_name
);
2437 pci_write_config_dword (pdev
, 0x60,
2438 0xe7000000 | inta_addr
[i
]);
2439 pci_write_config_dword (pdev
, 0x78,
2440 0x00000000 | inta_addr
[i
]);
2441 test
= inb (inta_addr
[i
]);
2442 if (test
!= 0xff) break;
2443 release_region(inta_addr
[i
], 0x8);
2447 printk (KERN_INFO
"parport_pc: cannot find ITE8872 INTA\n");
2451 type
= inb (inta_addr
[i
] + 0x18);
2456 printk (KERN_INFO
"parport_pc: ITE8871 found (1P)\n");
2457 ite8872set
= 0x64200000;
2460 printk (KERN_INFO
"parport_pc: ITE8875 found (1P)\n");
2461 ite8872set
= 0x64200000;
2464 printk (KERN_INFO
"parport_pc: ITE8872 found (2S1P)\n");
2465 ite8872set
= 0x64e00000;
2468 printk (KERN_INFO
"parport_pc: ITE8873 found (1S)\n");
2471 DPRINTK (KERN_DEBUG
"parport_pc: ITE8874 found (2S)\n");
2474 printk (KERN_INFO
"parport_pc: unknown ITE887x\n");
2475 printk (KERN_INFO
"parport_pc: please mail 'lspci -nvv' "
2476 "output to Rich.Liu@ite.com.tw\n");
2480 pci_read_config_byte (pdev
, 0x3c, &ite8872_irq
);
2481 pci_read_config_dword (pdev
, 0x1c, &ite8872_lpt
);
2482 ite8872_lpt
&= 0x0000ff00;
2483 pci_read_config_dword (pdev
, 0x20, &ite8872_lpthi
);
2484 ite8872_lpthi
&= 0x0000ff00;
2485 pci_write_config_dword (pdev
, 0x6c, 0xe3000000 | ite8872_lpt
);
2486 pci_write_config_dword (pdev
, 0x70, 0xe3000000 | ite8872_lpthi
);
2487 pci_write_config_dword (pdev
, 0x80, (ite8872_lpthi
<<16) | ite8872_lpt
);
2488 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2490 pci_write_config_dword (pdev
, 0x9c,
2491 ite8872set
| (ite8872_irq
* 0x11111));
2493 DPRINTK (KERN_DEBUG
"ITE887x: The IRQ is %d.\n", ite8872_irq
);
2494 DPRINTK (KERN_DEBUG
"ITE887x: The PARALLEL I/O port is 0x%x.\n",
2496 DPRINTK (KERN_DEBUG
"ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2499 /* Let the user (or defaults) steer us away from interrupts */
2501 if (autoirq
!= PARPORT_IRQ_AUTO
)
2502 irq
= PARPORT_IRQ_NONE
;
2505 * Release the resource so that parport_pc_probe_port can get it.
2507 release_resource(base_res
);
2508 if (parport_pc_probe_port (ite8872_lpt
, ite8872_lpthi
,
2509 irq
, PARPORT_DMA_NONE
, &pdev
->dev
)) {
2511 "parport_pc: ITE 8872 parallel port: io=0x%X",
2513 if (irq
!= PARPORT_IRQ_NONE
)
2514 printk (", irq=%d", irq
);
2522 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2523 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2524 static int __devinitdata parport_init_mode
= 0;
2526 /* Data for two known VIA chips */
2527 static struct parport_pc_via_data via_686a_data __devinitdata
= {
2536 static struct parport_pc_via_data via_8231_data __devinitdata
= {
2546 static int __devinit
sio_via_probe (struct pci_dev
*pdev
, int autoirq
,
2548 const struct parport_pc_via_data
*via
)
2550 u8 tmp
, tmp2
, siofunc
;
2553 unsigned port1
, port2
;
2554 unsigned have_epp
= 0;
2556 printk(KERN_DEBUG
"parport_pc: VIA 686A/8231 detected\n");
2558 switch(parport_init_mode
)
2561 printk(KERN_DEBUG
"parport_pc: setting SPP mode\n");
2562 siofunc
= VIA_FUNCTION_PARPORT_SPP
;
2565 printk(KERN_DEBUG
"parport_pc: setting PS/2 mode\n");
2566 siofunc
= VIA_FUNCTION_PARPORT_SPP
;
2567 ppcontrol
= VIA_PARPORT_BIDIR
;
2570 printk(KERN_DEBUG
"parport_pc: setting EPP mode\n");
2571 siofunc
= VIA_FUNCTION_PARPORT_EPP
;
2572 ppcontrol
= VIA_PARPORT_BIDIR
;
2576 printk(KERN_DEBUG
"parport_pc: setting ECP mode\n");
2577 siofunc
= VIA_FUNCTION_PARPORT_ECP
;
2578 ppcontrol
= VIA_PARPORT_BIDIR
;
2581 printk(KERN_DEBUG
"parport_pc: setting EPP+ECP mode\n");
2582 siofunc
= VIA_FUNCTION_PARPORT_ECP
;
2583 ppcontrol
= VIA_PARPORT_BIDIR
|VIA_PARPORT_ECPEPP
;
2587 printk(KERN_DEBUG
"parport_pc: probing current configuration\n");
2588 siofunc
= VIA_FUNCTION_PROBE
;
2592 * unlock super i/o configuration
2594 pci_read_config_byte(pdev
, via
->via_pci_superio_config_reg
, &tmp
);
2595 tmp
|= via
->via_pci_superio_config_data
;
2596 pci_write_config_byte(pdev
, via
->via_pci_superio_config_reg
, tmp
);
2598 /* Bits 1-0: Parallel Port Mode / Enable */
2599 outb(via
->viacfg_function
, VIA_CONFIG_INDEX
);
2600 tmp
= inb (VIA_CONFIG_DATA
);
2601 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2602 outb(via
->viacfg_parport_control
, VIA_CONFIG_INDEX
);
2603 tmp2
= inb (VIA_CONFIG_DATA
);
2604 if (siofunc
== VIA_FUNCTION_PROBE
)
2606 siofunc
= tmp
& VIA_FUNCTION_PARPORT_DISABLE
;
2611 tmp
&= ~VIA_FUNCTION_PARPORT_DISABLE
;
2613 outb(via
->viacfg_function
, VIA_CONFIG_INDEX
);
2614 outb(tmp
, VIA_CONFIG_DATA
);
2615 tmp2
&= ~(VIA_PARPORT_BIDIR
|VIA_PARPORT_ECPEPP
);
2617 outb(via
->viacfg_parport_control
, VIA_CONFIG_INDEX
);
2618 outb(tmp2
, VIA_CONFIG_DATA
);
2621 /* Parallel Port I/O Base Address, bits 9-2 */
2622 outb(via
->viacfg_parport_base
, VIA_CONFIG_INDEX
);
2623 port1
= inb(VIA_CONFIG_DATA
) << 2;
2625 printk (KERN_DEBUG
"parport_pc: Current parallel port base: 0x%X\n",port1
);
2626 if ((port1
== 0x3BC) && have_epp
)
2628 outb(via
->viacfg_parport_base
, VIA_CONFIG_INDEX
);
2629 outb((0x378 >> 2), VIA_CONFIG_DATA
);
2630 printk(KERN_DEBUG
"parport_pc: Parallel port base changed to 0x378\n");
2635 * lock super i/o configuration
2637 pci_read_config_byte(pdev
, via
->via_pci_superio_config_reg
, &tmp
);
2638 tmp
&= ~via
->via_pci_superio_config_data
;
2639 pci_write_config_byte(pdev
, via
->via_pci_superio_config_reg
, tmp
);
2641 if (siofunc
== VIA_FUNCTION_PARPORT_DISABLE
) {
2642 printk(KERN_INFO
"parport_pc: VIA parallel port disabled in BIOS\n");
2646 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2647 pci_read_config_byte(pdev
, via
->via_pci_parport_irq_reg
, &tmp
);
2648 irq
= ((tmp
& VIA_IRQCONTROL_PARALLEL
) >> 4);
2650 if (siofunc
== VIA_FUNCTION_PARPORT_ECP
)
2652 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2653 pci_read_config_byte(pdev
, via
->via_pci_parport_dma_reg
, &tmp
);
2654 dma
= ((tmp
& VIA_DMACONTROL_PARALLEL
) >> 2);
2657 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2658 dma
= PARPORT_DMA_NONE
;
2660 /* Let the user (or defaults) steer us away from interrupts and DMA */
2661 if (autoirq
== PARPORT_IRQ_NONE
) {
2662 irq
= PARPORT_IRQ_NONE
;
2663 dma
= PARPORT_DMA_NONE
;
2665 if (autodma
== PARPORT_DMA_NONE
)
2666 dma
= PARPORT_DMA_NONE
;
2669 case 0x3bc: port2
= 0x7bc; break;
2670 case 0x378: port2
= 0x778; break;
2671 case 0x278: port2
= 0x678; break;
2673 printk(KERN_INFO
"parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2678 /* filter bogus IRQs */
2684 irq
= PARPORT_IRQ_NONE
;
2687 default: /* do nothing */
2691 /* finally, do the probe with values obtained */
2692 if (parport_pc_probe_port (port1
, port2
, irq
, dma
, &pdev
->dev
)) {
2694 "parport_pc: VIA parallel port: io=0x%X", port1
);
2695 if (irq
!= PARPORT_IRQ_NONE
)
2696 printk (", irq=%d", irq
);
2697 if (dma
!= PARPORT_DMA_NONE
)
2698 printk (", dma=%d", dma
);
2703 printk(KERN_WARNING
"parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2709 enum parport_pc_sio_types
{
2710 sio_via_686a
= 0, /* Via VT82C686A motherboard Super I/O */
2711 sio_via_8231
, /* Via VT8231 south bridge integrated Super IO */
2716 /* each element directly indexed from enum list, above */
2717 static struct parport_pc_superio
{
2718 int (*probe
) (struct pci_dev
*pdev
, int autoirq
, int autodma
,
2719 const struct parport_pc_via_data
*via
);
2720 const struct parport_pc_via_data
*via
;
2721 } parport_pc_superio_info
[] __devinitdata
= {
2722 { sio_via_probe
, &via_686a_data
, },
2723 { sio_via_probe
, &via_8231_data
, },
2724 { sio_ite_8872_probe
, NULL
, },
2727 enum parport_pc_pci_cards
{
2728 siig_1p_10x
= last_sio
,
2733 lava_parallel_dual_a
,
2734 lava_parallel_dual_b
,
2780 /* each element directly indexed from enum list, above
2781 * (but offset by last_sio) */
2782 static struct parport_pc_pci
{
2784 struct { /* BAR (base address registers) numbers in the config
2787 int hi
; /* -1 if not there, >6 for offset-method (max
2791 /* If set, this is called immediately after pci_enable_device.
2792 * If it returns non-zero, no probing will take place and the
2793 * ports will not be used. */
2794 int (*preinit_hook
) (struct pci_dev
*pdev
, int autoirq
, int autodma
);
2796 /* If set, this is called after probing for ports. If 'failed'
2797 * is non-zero we couldn't use any of the ports. */
2798 void (*postinit_hook
) (struct pci_dev
*pdev
, int failed
);
2800 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2801 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2802 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2803 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2804 /* lava_parallel */ { 1, { { 0, -1 }, } },
2805 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2806 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2807 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2808 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2809 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2810 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2811 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2812 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2813 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2814 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2815 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2816 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2817 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2818 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2819 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2820 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2821 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2822 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2823 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2824 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2825 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2826 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2827 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2828 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2829 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2830 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2831 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2832 /* SYBA uses fixed offsets in
2834 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2835 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2836 /* titan_010l */ { 1, { { 3, -1 }, } },
2837 /* titan_1284p1 */ { 1, { { 0, 1 }, } },
2838 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2839 /* avlab_1p */ { 1, { { 0, 1}, } },
2840 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2841 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2842 * and 840 locks up if you write 1 to bit 2! */
2843 /* oxsemi_952 */ { 1, { { 0, 1 }, } },
2844 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2845 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2846 /* aks_0100 */ { 1, { { 0, -1 }, } },
2847 /* mobility_pp */ { 1, { { 0, 1 }, } },
2848 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2849 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2850 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2851 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2852 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2855 static const struct pci_device_id parport_pc_pci_tbl
[] = {
2856 /* Super-IO onboard chips */
2857 { 0x1106, 0x0686, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sio_via_686a
},
2858 { 0x1106, 0x8231, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sio_via_8231
},
2859 { PCI_VENDOR_ID_ITE
, PCI_DEVICE_ID_ITE_8872
,
2860 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sio_ite_8872
},
2863 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1P_10x
,
2864 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, siig_1p_10x
},
2865 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2P_10x
,
2866 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, siig_2p_10x
},
2867 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1P_20x
,
2868 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, siig_1p_20x
},
2869 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2P_20x
,
2870 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, siig_2p_20x
},
2871 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PARALLEL
,
2872 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, lava_parallel
},
2873 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DUAL_PAR_A
,
2874 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, lava_parallel_dual_a
},
2875 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DUAL_PAR_B
,
2876 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, lava_parallel_dual_b
},
2877 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR
,
2878 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, boca_ioppar
},
2879 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2880 PCI_SUBVENDOR_ID_EXSYS
, PCI_SUBDEVICE_ID_EXSYS_4014
, 0,0, plx_9050
},
2881 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2882 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a
},
2883 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h
},
2884 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h
},
2885 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a
},
2886 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a
},
2887 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a
},
2888 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a
},
2889 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u
},
2890 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a
},
2891 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u
},
2892 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r
},
2893 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s
},
2894 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d
},
2895 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e
},
2896 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f
},
2897 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a
},
2898 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b
},
2899 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c
},
2900 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a
},
2901 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014
},
2902 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a
},
2903 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018
},
2904 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a
},
2905 { 0x14f2, 0x0121, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, mobility_pp
},
2906 { PCI_VENDOR_ID_SYBA
, PCI_DEVICE_ID_SYBA_2P_EPP
,
2907 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, syba_2p_epp
},
2908 { PCI_VENDOR_ID_SYBA
, PCI_DEVICE_ID_SYBA_1P_ECP
,
2909 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, syba_1p_ecp
},
2910 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_010L
,
2911 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, titan_010l
},
2912 { 0x9710, 0x9805, 0x1000, 0x0010, 0, 0, titan_1284p1
},
2913 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2
},
2914 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2915 { 0x14db, 0x2120, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, avlab_1p
}, /* AFAVLAB_TK9902 */
2916 { 0x14db, 0x2121, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, avlab_2p
},
2917 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI952PP
,
2918 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, oxsemi_952
},
2919 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954PP
,
2920 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, oxsemi_954
},
2921 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_12PCI840
,
2922 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, oxsemi_840
},
2923 { PCI_VENDOR_ID_AKS
, PCI_DEVICE_ID_AKS_ALADDINCARD
,
2924 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, aks_0100
},
2925 /* NetMos communication controllers */
2926 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9705
,
2927 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, netmos_9705
},
2928 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9715
,
2929 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, netmos_9715
},
2930 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9755
,
2931 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, netmos_9755
},
2932 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9805
,
2933 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, netmos_9805
},
2934 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9815
,
2935 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, netmos_9815
},
2936 { 0, } /* terminate list */
2938 MODULE_DEVICE_TABLE(pci
,parport_pc_pci_tbl
);
2940 struct pci_parport_data
{
2942 struct parport
*ports
[2];
2945 static int parport_pc_pci_probe (struct pci_dev
*dev
,
2946 const struct pci_device_id
*id
)
2948 int err
, count
, n
, i
= id
->driver_data
;
2949 struct pci_parport_data
*data
;
2952 /* This is an onboard Super-IO and has already been probed */
2955 /* This is a PCI card */
2958 if ((err
= pci_enable_device (dev
)) != 0)
2961 data
= kmalloc(sizeof(struct pci_parport_data
), GFP_KERNEL
);
2965 if (cards
[i
].preinit_hook
&&
2966 cards
[i
].preinit_hook (dev
, PARPORT_IRQ_NONE
, PARPORT_DMA_NONE
)) {
2971 for (n
= 0; n
< cards
[i
].numports
; n
++) {
2972 int lo
= cards
[i
].addr
[n
].lo
;
2973 int hi
= cards
[i
].addr
[n
].hi
;
2974 unsigned long io_lo
, io_hi
;
2975 io_lo
= pci_resource_start (dev
, lo
);
2977 if ((hi
>= 0) && (hi
<= 6))
2978 io_hi
= pci_resource_start (dev
, hi
);
2980 io_lo
+= hi
; /* Reinterpret the meaning of
2981 "hi" as an offset (see SYBA
2983 /* TODO: test if sharing interrupts works */
2984 printk (KERN_DEBUG
"PCI parallel port detected: %04x:%04x, "
2985 "I/O at %#lx(%#lx)\n",
2986 parport_pc_pci_tbl
[i
+ last_sio
].vendor
,
2987 parport_pc_pci_tbl
[i
+ last_sio
].device
, io_lo
, io_hi
);
2988 data
->ports
[count
] =
2989 parport_pc_probe_port (io_lo
, io_hi
, PARPORT_IRQ_NONE
,
2990 PARPORT_DMA_NONE
, &dev
->dev
);
2991 if (data
->ports
[count
])
2997 if (cards
[i
].postinit_hook
)
2998 cards
[i
].postinit_hook (dev
, count
== 0);
3001 pci_set_drvdata(dev
, data
);
3010 static void __devexit
parport_pc_pci_remove(struct pci_dev
*dev
)
3012 struct pci_parport_data
*data
= pci_get_drvdata(dev
);
3015 pci_set_drvdata(dev
, NULL
);
3018 for (i
= data
->num
- 1; i
>= 0; i
--)
3019 parport_pc_unregister_port(data
->ports
[i
]);
3025 static struct pci_driver parport_pc_pci_driver
= {
3026 .name
= "parport_pc",
3027 .id_table
= parport_pc_pci_tbl
,
3028 .probe
= parport_pc_pci_probe
,
3029 .remove
= __devexit_p(parport_pc_pci_remove
),
3032 static int __init
parport_pc_init_superio (int autoirq
, int autodma
)
3034 const struct pci_device_id
*id
;
3035 struct pci_dev
*pdev
= NULL
;
3038 for_each_pci_dev(pdev
) {
3039 id
= pci_match_id(parport_pc_pci_tbl
, pdev
);
3040 if (id
== NULL
|| id
->driver_data
>= last_sio
)
3043 if (parport_pc_superio_info
[id
->driver_data
].probe
3044 (pdev
, autoirq
, autodma
,parport_pc_superio_info
[id
->driver_data
].via
)) {
3049 return ret
; /* number of devices found */
3052 static struct pci_driver parport_pc_pci_driver
;
3053 static int __init
parport_pc_init_superio(int autoirq
, int autodma
) {return 0;}
3054 #endif /* CONFIG_PCI */
3057 static const struct pnp_device_id parport_pc_pnp_tbl
[] = {
3058 /* Standard LPT Printer Port */
3059 {.id
= "PNP0400", .driver_data
= 0},
3060 /* ECP Printer Port */
3061 {.id
= "PNP0401", .driver_data
= 0},
3065 MODULE_DEVICE_TABLE(pnp
,parport_pc_pnp_tbl
);
3067 static int parport_pc_pnp_probe(struct pnp_dev
*dev
, const struct pnp_device_id
*id
)
3069 struct parport
*pdata
;
3070 unsigned long io_lo
, io_hi
;
3073 if (pnp_port_valid(dev
,0) &&
3074 !(pnp_port_flags(dev
,0) & IORESOURCE_DISABLED
)) {
3075 io_lo
= pnp_port_start(dev
,0);
3079 if (pnp_port_valid(dev
,1) &&
3080 !(pnp_port_flags(dev
,1) & IORESOURCE_DISABLED
)) {
3081 io_hi
= pnp_port_start(dev
,1);
3085 if (pnp_irq_valid(dev
,0) &&
3086 !(pnp_irq_flags(dev
,0) & IORESOURCE_DISABLED
)) {
3087 irq
= pnp_irq(dev
,0);
3089 irq
= PARPORT_IRQ_NONE
;
3091 if (pnp_dma_valid(dev
,0) &&
3092 !(pnp_dma_flags(dev
,0) & IORESOURCE_DISABLED
)) {
3093 dma
= pnp_dma(dev
,0);
3095 dma
= PARPORT_DMA_NONE
;
3097 dev_info(&dev
->dev
, "reported by %s\n", dev
->protocol
->name
);
3098 if (!(pdata
= parport_pc_probe_port (io_lo
, io_hi
, irq
, dma
, &dev
->dev
)))
3101 pnp_set_drvdata(dev
,pdata
);
3105 static void parport_pc_pnp_remove(struct pnp_dev
*dev
)
3107 struct parport
*pdata
= (struct parport
*)pnp_get_drvdata(dev
);
3111 parport_pc_unregister_port(pdata
);
3114 /* we only need the pnp layer to activate the device, at least for now */
3115 static struct pnp_driver parport_pc_pnp_driver
= {
3116 .name
= "parport_pc",
3117 .id_table
= parport_pc_pnp_tbl
,
3118 .probe
= parport_pc_pnp_probe
,
3119 .remove
= parport_pc_pnp_remove
,
3123 static int __devinit
parport_pc_platform_probe(struct platform_device
*pdev
)
3125 /* Always succeed, the actual probing is done in
3126 * parport_pc_probe_port(). */
3130 static struct platform_driver parport_pc_platform_driver
= {
3132 .owner
= THIS_MODULE
,
3133 .name
= "parport_pc",
3135 .probe
= parport_pc_platform_probe
,
3138 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3139 static int __devinit
__attribute__((unused
))
3140 parport_pc_find_isa_ports (int autoirq
, int autodma
)
3144 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq
, autodma
, NULL
))
3146 if (parport_pc_probe_port(0x378, 0x778, autoirq
, autodma
, NULL
))
3148 if (parport_pc_probe_port(0x278, 0x678, autoirq
, autodma
, NULL
))
3154 /* This function is called by parport_pc_init if the user didn't
3155 * specify any ports to probe. Its job is to find some ports. Order
3156 * is important here -- we want ISA ports to be registered first,
3157 * followed by PCI cards (for least surprise), but before that we want
3158 * to do chipset-specific tests for some onboard ports that we know
3161 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3162 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3164 static void __init
parport_pc_find_ports (int autoirq
, int autodma
)
3168 #ifdef CONFIG_PARPORT_PC_SUPERIO
3169 detect_and_report_winbond ();
3170 detect_and_report_smsc ();
3173 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3174 count
+= parport_pc_init_superio (autoirq
, autodma
);
3176 /* PnP ports, skip detection if SuperIO already found them */
3178 err
= pnp_register_driver (&parport_pc_pnp_driver
);
3180 pnp_registered_parport
= 1;
3183 /* ISA ports and whatever (see asm/parport.h). */
3184 parport_pc_find_nonpci_ports (autoirq
, autodma
);
3186 err
= pci_register_driver (&parport_pc_pci_driver
);
3188 pci_registered_parport
= 1;
3192 * Piles of crap below pretend to be a parser for module and kernel
3193 * parameters. Say "thank you" to whoever had come up with that
3194 * syntax and keep in mind that code below is a cleaned up version.
3197 static int __initdata io
[PARPORT_PC_MAX_PORTS
+1] = { [0 ... PARPORT_PC_MAX_PORTS
] = 0 };
3198 static int __initdata io_hi
[PARPORT_PC_MAX_PORTS
+1] =
3199 { [0 ... PARPORT_PC_MAX_PORTS
] = PARPORT_IOHI_AUTO
};
3200 static int __initdata dmaval
[PARPORT_PC_MAX_PORTS
] = { [0 ... PARPORT_PC_MAX_PORTS
-1] = PARPORT_DMA_NONE
};
3201 static int __initdata irqval
[PARPORT_PC_MAX_PORTS
] = { [0 ... PARPORT_PC_MAX_PORTS
-1] = PARPORT_IRQ_PROBEONLY
};
3203 static int __init
parport_parse_param(const char *s
, int *val
,
3204 int automatic
, int none
, int nofifo
)
3208 if (!strncmp(s
, "auto", 4))
3210 else if (!strncmp(s
, "none", 4))
3212 else if (nofifo
&& !strncmp(s
, "nofifo", 4))
3216 unsigned long r
= simple_strtoul(s
, &ep
, 0);
3220 printk(KERN_ERR
"parport: bad specifier `%s'\n", s
);
3227 static int __init
parport_parse_irq(const char *irqstr
, int *val
)
3229 return parport_parse_param(irqstr
, val
, PARPORT_IRQ_AUTO
,
3230 PARPORT_IRQ_NONE
, 0);
3233 static int __init
parport_parse_dma(const char *dmastr
, int *val
)
3235 return parport_parse_param(dmastr
, val
, PARPORT_DMA_AUTO
,
3236 PARPORT_DMA_NONE
, PARPORT_DMA_NOFIFO
);
3240 static int __init
parport_init_mode_setup(char *str
)
3242 printk(KERN_DEBUG
"parport_pc.c: Specified parameter parport_init_mode=%s\n", str
);
3244 if (!strcmp (str
, "spp"))
3245 parport_init_mode
=1;
3246 if (!strcmp (str
, "ps2"))
3247 parport_init_mode
=2;
3248 if (!strcmp (str
, "epp"))
3249 parport_init_mode
=3;
3250 if (!strcmp (str
, "ecp"))
3251 parport_init_mode
=4;
3252 if (!strcmp (str
, "ecpepp"))
3253 parport_init_mode
=5;
3259 static const char *irq
[PARPORT_PC_MAX_PORTS
];
3260 static const char *dma
[PARPORT_PC_MAX_PORTS
];
3262 MODULE_PARM_DESC(io
, "Base I/O address (SPP regs)");
3263 module_param_array(io
, int, NULL
, 0);
3264 MODULE_PARM_DESC(io_hi
, "Base I/O address (ECR)");
3265 module_param_array(io_hi
, int, NULL
, 0);
3266 MODULE_PARM_DESC(irq
, "IRQ line");
3267 module_param_array(irq
, charp
, NULL
, 0);
3268 MODULE_PARM_DESC(dma
, "DMA channel");
3269 module_param_array(dma
, charp
, NULL
, 0);
3270 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3271 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3272 MODULE_PARM_DESC(verbose_probing
, "Log chit-chat during initialisation");
3273 module_param(verbose_probing
, int, 0644);
3276 static char *init_mode
;
3277 MODULE_PARM_DESC(init_mode
, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3278 module_param(init_mode
, charp
, 0);
3281 static int __init
parse_parport_params(void)
3288 parport_init_mode_setup(init_mode
);
3291 for (i
= 0; i
< PARPORT_PC_MAX_PORTS
&& io
[i
]; i
++) {
3292 if (parport_parse_irq(irq
[i
], &val
))
3295 if (parport_parse_dma(dma
[i
], &val
))
3300 /* The user can make us use any IRQs or DMAs we find. */
3301 if (irq
[0] && !parport_parse_irq(irq
[0], &val
))
3303 case PARPORT_IRQ_NONE
:
3304 case PARPORT_IRQ_AUTO
:
3308 printk (KERN_WARNING
3309 "parport_pc: irq specified "
3310 "without base address. Use 'io=' "
3311 "to specify one\n");
3314 if (dma
[0] && !parport_parse_dma(dma
[0], &val
))
3316 case PARPORT_DMA_NONE
:
3317 case PARPORT_DMA_AUTO
:
3321 printk (KERN_WARNING
3322 "parport_pc: dma specified "
3323 "without base address. Use 'io=' "
3324 "to specify one\n");
3332 static int parport_setup_ptr __initdata
= 0;
3335 * Acceptable parameters:
3339 * parport=0xBASE[,IRQ[,DMA]]
3341 * IRQ/DMA may be numeric or 'auto' or 'none'
3343 static int __init
parport_setup (char *str
)
3349 if (!str
|| !*str
|| (*str
== '0' && !*(str
+1))) {
3350 /* Disable parport if "parport=0" in cmdline */
3351 io
[0] = PARPORT_DISABLE
;
3355 if (!strncmp (str
, "auto", 4)) {
3356 irqval
[0] = PARPORT_IRQ_AUTO
;
3357 dmaval
[0] = PARPORT_DMA_AUTO
;
3361 val
= simple_strtoul (str
, &endptr
, 0);
3362 if (endptr
== str
) {
3363 printk (KERN_WARNING
"parport=%s not understood\n", str
);
3367 if (parport_setup_ptr
== PARPORT_PC_MAX_PORTS
) {
3368 printk(KERN_ERR
"parport=%s ignored, too many ports\n", str
);
3372 io
[parport_setup_ptr
] = val
;
3373 irqval
[parport_setup_ptr
] = PARPORT_IRQ_NONE
;
3374 dmaval
[parport_setup_ptr
] = PARPORT_DMA_NONE
;
3376 sep
= strchr(str
, ',');
3378 if (parport_parse_irq(sep
, &val
))
3380 irqval
[parport_setup_ptr
] = val
;
3381 sep
= strchr(sep
, ',');
3383 if (parport_parse_dma(sep
, &val
))
3385 dmaval
[parport_setup_ptr
] = val
;
3388 parport_setup_ptr
++;
3392 static int __init
parse_parport_params(void)
3394 return io
[0] == PARPORT_DISABLE
;
3397 __setup ("parport=", parport_setup
);
3400 * Acceptable parameters:
3402 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3405 __setup("parport_init_mode=",parport_init_mode_setup
);
3409 /* "Parser" ends here */
3411 static int __init
parport_pc_init(void)
3415 if (parse_parport_params())
3418 err
= platform_driver_register(&parport_pc_platform_driver
);
3424 /* Only probe the ports we were given. */
3426 for (i
= 0; i
< PARPORT_PC_MAX_PORTS
; i
++) {
3429 if ((io_hi
[i
]) == PARPORT_IOHI_AUTO
)
3430 io_hi
[i
] = 0x400 + io
[i
];
3431 parport_pc_probe_port(io
[i
], io_hi
[i
],
3432 irqval
[i
], dmaval
[i
], NULL
);
3435 parport_pc_find_ports (irqval
[0], dmaval
[0]);
3440 static void __exit
parport_pc_exit(void)
3442 if (pci_registered_parport
)
3443 pci_unregister_driver (&parport_pc_pci_driver
);
3444 if (pnp_registered_parport
)
3445 pnp_unregister_driver (&parport_pc_pnp_driver
);
3446 platform_driver_unregister(&parport_pc_platform_driver
);
3448 spin_lock(&ports_lock
);
3449 while (!list_empty(&ports_list
)) {
3450 struct parport_pc_private
*priv
;
3451 struct parport
*port
;
3452 priv
= list_entry(ports_list
.next
,
3453 struct parport_pc_private
, list
);
3455 if (port
->dev
&& port
->dev
->bus
== &platform_bus_type
)
3456 platform_device_unregister(
3457 to_platform_device(port
->dev
));
3458 spin_unlock(&ports_lock
);
3459 parport_pc_unregister_port(port
);
3460 spin_lock(&ports_lock
);
3462 spin_unlock(&ports_lock
);
3465 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3466 MODULE_DESCRIPTION("PC-style parallel port driver");
3467 MODULE_LICENSE("GPL");
3468 module_init(parport_pc_init
)
3469 module_exit(parport_pc_exit
)