2 * pata-cs5530.c - CS5530 PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
6 * based upon cs5530.c by Mark Lord.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Loosely based on the piix & svwks drivers.
24 * Available from AMD web site.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
35 #include <linux/dmi.h>
37 #define DRV_NAME "pata_cs5530"
38 #define DRV_VERSION "0.7.2"
40 static void __iomem
*cs5530_port_base(struct ata_port
*ap
)
42 unsigned long bmdma
= (unsigned long)ap
->ioaddr
.bmdma_addr
;
44 return (void __iomem
*)((bmdma
& ~0x0F) + 0x20 + 0x10 * ap
->port_no
);
48 * cs5530_set_piomode - PIO setup
50 * @adev: device on the interface
52 * Set our PIO requirements. This is fairly simple on the CS5530
56 static void cs5530_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
58 static const unsigned int cs5530_pio_timings
[2][5] = {
59 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
60 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
62 void __iomem
*base
= cs5530_port_base(ap
);
66 /* Find out which table to use */
67 tuning
= ioread32(base
+ 0x04);
68 format
= (tuning
& 0x80000000UL
) ? 1 : 0;
70 /* Now load the right timing register */
74 iowrite32(cs5530_pio_timings
[format
][adev
->pio_mode
- XFER_PIO_0
], base
);
78 * cs5530_set_dmamode - DMA timing setup
80 * @adev: Device being configured
82 * We cannot mix MWDMA and UDMA without reloading timings each switch
83 * master to slave. We track the last DMA setup in order to minimise
87 static void cs5530_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
89 void __iomem
*base
= cs5530_port_base(ap
);
90 u32 tuning
, timing
= 0;
93 /* Find out which table to use */
94 tuning
= ioread32(base
+ 0x04);
96 switch(adev
->dma_mode
) {
98 timing
= 0x00921250;break;
100 timing
= 0x00911140;break;
102 timing
= 0x00911030;break;
104 timing
= 0x00077771;break;
106 timing
= 0x00012121;break;
108 timing
= 0x00002020;break;
112 /* Merge in the PIO format bit */
113 timing
|= (tuning
& 0x80000000UL
);
114 if (adev
->devno
== 0) /* Master */
115 iowrite32(timing
, base
+ 0x04);
117 if (timing
& 0x00100000)
118 tuning
|= 0x00100000; /* UDMA for both */
120 tuning
&= ~0x00100000; /* MWDMA for both */
121 iowrite32(tuning
, base
+ 0x04);
122 iowrite32(timing
, base
+ 0x0C);
125 /* Set the DMA capable bit in the BMDMA area */
126 reg
= ioread8(ap
->ioaddr
.bmdma_addr
+ ATA_DMA_STATUS
);
127 reg
|= (1 << (5 + adev
->devno
));
128 iowrite8(reg
, ap
->ioaddr
.bmdma_addr
+ ATA_DMA_STATUS
);
130 /* Remember the last DMA setup we did */
132 ap
->private_data
= adev
;
136 * cs5530_qc_issue_prot - command issue
137 * @qc: command pending
139 * Called when the libata layer is about to issue a command. We wrap
140 * this interface so that we can load the correct ATA timings if
141 * neccessary. Specifically we have a problem that there is only
142 * one MWDMA/UDMA bit.
145 static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd
*qc
)
147 struct ata_port
*ap
= qc
->ap
;
148 struct ata_device
*adev
= qc
->dev
;
149 struct ata_device
*prev
= ap
->private_data
;
151 /* See if the DMA settings could be wrong */
152 if (adev
->dma_mode
!= 0 && adev
!= prev
&& prev
!= NULL
) {
153 /* Maybe, but do the channels match MWDMA/UDMA ? */
154 if ((adev
->dma_mode
>= XFER_UDMA_0
&& prev
->dma_mode
< XFER_UDMA_0
) ||
155 (adev
->dma_mode
< XFER_UDMA_0
&& prev
->dma_mode
>= XFER_UDMA_0
))
156 /* Switch the mode bits */
157 cs5530_set_dmamode(ap
, adev
);
160 return ata_qc_issue_prot(qc
);
163 static struct scsi_host_template cs5530_sht
= {
164 .module
= THIS_MODULE
,
166 .ioctl
= ata_scsi_ioctl
,
167 .queuecommand
= ata_scsi_queuecmd
,
168 .can_queue
= ATA_DEF_QUEUE
,
169 .this_id
= ATA_SHT_THIS_ID
,
170 .sg_tablesize
= LIBATA_MAX_PRD
,
171 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
172 .emulated
= ATA_SHT_EMULATED
,
173 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
174 .proc_name
= DRV_NAME
,
175 .dma_boundary
= ATA_DMA_BOUNDARY
,
176 .slave_configure
= ata_scsi_slave_config
,
177 .slave_destroy
= ata_scsi_slave_destroy
,
178 .bios_param
= ata_std_bios_param
,
181 static struct ata_port_operations cs5530_port_ops
= {
182 .port_disable
= ata_port_disable
,
183 .set_piomode
= cs5530_set_piomode
,
184 .set_dmamode
= cs5530_set_dmamode
,
185 .mode_filter
= ata_pci_default_filter
,
187 .tf_load
= ata_tf_load
,
188 .tf_read
= ata_tf_read
,
189 .check_status
= ata_check_status
,
190 .exec_command
= ata_exec_command
,
191 .dev_select
= ata_std_dev_select
,
193 .bmdma_setup
= ata_bmdma_setup
,
194 .bmdma_start
= ata_bmdma_start
,
195 .bmdma_stop
= ata_bmdma_stop
,
196 .bmdma_status
= ata_bmdma_status
,
198 .freeze
= ata_bmdma_freeze
,
199 .thaw
= ata_bmdma_thaw
,
200 .error_handler
= ata_bmdma_error_handler
,
201 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
202 .cable_detect
= ata_cable_40wire
,
204 .qc_prep
= ata_qc_prep
,
205 .qc_issue
= cs5530_qc_issue_prot
,
207 .data_xfer
= ata_data_xfer
,
209 .irq_handler
= ata_interrupt
,
210 .irq_clear
= ata_bmdma_irq_clear
,
211 .irq_on
= ata_irq_on
,
212 .irq_ack
= ata_irq_ack
,
214 .port_start
= ata_port_start
,
217 static struct dmi_system_id palmax_dmi_table
[] = {
219 .ident
= "Palmax PD1100",
221 DMI_MATCH(DMI_SYS_VENDOR
, "Cyrix"),
222 DMI_MATCH(DMI_PRODUCT_NAME
, "Caddis"),
228 static int cs5530_is_palmax(void)
230 if (dmi_check_system(palmax_dmi_table
)) {
231 printk(KERN_INFO
"Palmax PD1100: Disabling DMA on docking port.\n");
239 * cs5530_init_chip - Chipset init
241 * Perform the chip initialisation work that is shared between both
242 * setup and resume paths
245 static int cs5530_init_chip(void)
247 struct pci_dev
*master_0
= NULL
, *cs5530_0
= NULL
, *dev
= NULL
;
249 while ((dev
= pci_get_device(PCI_VENDOR_ID_CYRIX
, PCI_ANY_ID
, dev
)) != NULL
) {
250 switch (dev
->device
) {
251 case PCI_DEVICE_ID_CYRIX_PCI_MASTER
:
252 master_0
= pci_dev_get(dev
);
254 case PCI_DEVICE_ID_CYRIX_5530_LEGACY
:
255 cs5530_0
= pci_dev_get(dev
);
260 printk(KERN_ERR DRV_NAME
": unable to locate PCI MASTER function\n");
264 printk(KERN_ERR DRV_NAME
": unable to locate CS5530 LEGACY function\n");
268 pci_set_master(cs5530_0
);
269 pci_set_mwi(cs5530_0
);
272 * Set PCI CacheLineSize to 16-bytes:
273 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
275 * Note: This value is constant because the 5530 is only a Geode companion
278 pci_write_config_byte(cs5530_0
, PCI_CACHE_LINE_SIZE
, 0x04);
281 * Disable trapping of UDMA register accesses (Win98 hack):
282 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
285 pci_write_config_word(cs5530_0
, 0xd0, 0x5006);
288 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
289 * The other settings are what is necessary to get the register
290 * into a sane state for IDE DMA operation.
293 pci_write_config_byte(master_0
, 0x40, 0x1e);
296 * Set max PCI burst size (16-bytes seems to work best):
297 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
298 * all others: clear bit-1 at 0x41, and do:
299 * 128bytes: OR 0x00 at 0x41
300 * 256bytes: OR 0x04 at 0x41
301 * 512bytes: OR 0x08 at 0x41
302 * 1024bytes: OR 0x0c at 0x41
305 pci_write_config_byte(master_0
, 0x41, 0x14);
308 * These settings are necessary to get the chip
309 * into a sane state for IDE DMA operation.
312 pci_write_config_byte(master_0
, 0x42, 0x00);
313 pci_write_config_byte(master_0
, 0x43, 0xc1);
315 pci_dev_put(master_0
);
316 pci_dev_put(cs5530_0
);
320 pci_dev_put(master_0
);
322 pci_dev_put(cs5530_0
);
327 * cs5530_init_one - Initialise a CS5530
329 * @id: Entry in match table
331 * Install a driver for the newly found CS5530 companion chip. Most of
332 * this is just housekeeping. We have to set the chip up correctly and
333 * turn off various bits of emulation magic.
336 static int cs5530_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
338 static const struct ata_port_info info
= {
340 .flags
= ATA_FLAG_SLAVE_POSS
|ATA_FLAG_SRST
,
344 .port_ops
= &cs5530_port_ops
346 /* The docking connector doesn't do UDMA, and it seems not MWDMA */
347 static const struct ata_port_info info_palmax_secondary
= {
349 .flags
= ATA_FLAG_SLAVE_POSS
|ATA_FLAG_SRST
,
351 .port_ops
= &cs5530_port_ops
353 const struct ata_port_info
*ppi
[] = { &info
, NULL
};
355 /* Chip initialisation */
356 if (cs5530_init_chip())
359 if (cs5530_is_palmax())
360 ppi
[1] = &info_palmax_secondary
;
362 /* Now kick off ATA set up */
363 return ata_pci_init_one(pdev
, ppi
);
367 static int cs5530_reinit_one(struct pci_dev
*pdev
)
369 /* If we fail on resume we are doomed */
370 if (cs5530_init_chip())
372 return ata_pci_device_resume(pdev
);
374 #endif /* CONFIG_PM */
376 static const struct pci_device_id cs5530
[] = {
377 { PCI_VDEVICE(CYRIX
, PCI_DEVICE_ID_CYRIX_5530_IDE
), },
382 static struct pci_driver cs5530_pci_driver
= {
385 .probe
= cs5530_init_one
,
386 .remove
= ata_pci_remove_one
,
388 .suspend
= ata_pci_device_suspend
,
389 .resume
= cs5530_reinit_one
,
393 static int __init
cs5530_init(void)
395 return pci_register_driver(&cs5530_pci_driver
);
398 static void __exit
cs5530_exit(void)
400 pci_unregister_driver(&cs5530_pci_driver
);
403 MODULE_AUTHOR("Alan Cox");
404 MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530");
405 MODULE_LICENSE("GPL");
406 MODULE_DEVICE_TABLE(pci
, cs5530
);
407 MODULE_VERSION(DRV_VERSION
);
409 module_init(cs5530_init
);
410 module_exit(cs5530_exit
);