include/asm-frv/mb-regs.h

   1 /* mb-regs.h: motherboard registers
   2  *
   3  * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef _ASM_MB_REGS_H
  13 #define _ASM_MB_REGS_H
  14
  15 #include <asm/cpu-irqs.h>
  16 #include <asm/sections.h>
  17 #include <asm/mem-layout.h>
  18
  19 #define __region_IO     KERNEL_IO_START /* the region from 0xe0000000 to 0xffffffff has suitable
  20                                          * protection laid over the top for use in memory-mapped
  21                                          * I/O
  22                                          */
  23
  24 #define __region_CS0    0xff000000      /* Boot ROMs area */
  25
  26 #ifdef CONFIG_MB93091_VDK
  27 /*
  28  * VDK motherboard and CPU card specific stuff
  29  */
  30
  31 #include <asm/mb93091-fpga-irqs.h>
  32
  33 #define IRQ_CPU_MB93493_0       IRQ_CPU_EXTERNAL0
  34 #define IRQ_CPU_MB93493_1       IRQ_CPU_EXTERNAL1
  35
  36 #define __region_CS2    0xe0000000      /* SLBUS/PCI I/O space */
  37 #define __region_CS2_M          0x0fffffff /* mask */
  38 #define __region_CS2_C          0x00000000 /* control */
  39 #define __region_CS5    0xf0000000      /* MB93493 CSC area (DAV daughter board) */
  40 #define __region_CS5_M          0x00ffffff
  41 #define __region_CS5_C          0x00010000
  42 #define __region_CS7    0xf1000000      /* CB70 CPU-card PCMCIA port I/O space */
  43 #define __region_CS7_M          0x00ffffff
  44 #define __region_CS7_C          0x00410701
  45 #define __region_CS1    0xfc000000      /* SLBUS/PCI bridge control registers */
  46 #define __region_CS1_M          0x000fffff
  47 #define __region_CS1_C          0x00000000
  48 #define __region_CS6    0xfc100000      /* CB70 CPU-card DM9000 LAN I/O space */
  49 #define __region_CS6_M          0x000fffff
  50 #define __region_CS6_C          0x00400707
  51 #define __region_CS3    0xfc200000      /* MB93493 CSR area (DAV daughter board) */
  52 #define __region_CS3_M          0x000fffff
  53 #define __region_CS3_C          0xc8100000
  54 #define __region_CS4    0xfd000000      /* CB70 CPU-card extra flash space */
  55 #define __region_CS4_M          0x00ffffff
  56 #define __region_CS4_C          0x00000f07
  57
  58 #define __region_PCI_IO         (__region_CS2 + 0x04000000UL)
  59 #define __region_PCI_MEM        (__region_CS2 + 0x08000000UL)
  60 #define __flush_PCI_writes()                                            \
  61 do {                                                                    \
  62         __builtin_write8((volatile void *) __region_PCI_MEM, 0);        \
  63 } while(0)
  64
  65 #define __is_PCI_IO(addr) \
  66         (((unsigned long)(addr) >> 24) - (__region_PCI_IO >> 24)  < (0x04000000UL >> 24))
  67
  68 #define __is_PCI_MEM(addr) \
  69         ((unsigned long)(addr) - __region_PCI_MEM < 0x08000000UL)
  70
  71 #define __is_PCI_addr(addr) \
  72         ((unsigned long)(addr) - __region_PCI_IO < 0x0c000000UL)
  73
  74 #define __get_CLKSW()   ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; })
  75 #define __get_CLKIN()   (__get_CLKSW() * 125U * 100000U / 24U)
  76
  77 #ifndef __ASSEMBLY__
  78 extern int __nongprelbss mb93090_mb00_detected;
  79 #endif
  80
  81 #define __addr_LEDS()           (__region_CS2 + 0x01200004UL)
  82 #ifdef CONFIG_MB93090_MB00
  83 #define __set_LEDS(X)                                                   \
  84 do {                                                                    \
  85         if (mb93090_mb00_detected)                                      \
  86                 __builtin_write32((void *) __addr_LEDS(), ~(X));        \
  87 } while (0)
  88 #else
  89 #define __set_LEDS(X)
  90 #endif
  91
  92 #define __addr_LCD()            (__region_CS2 + 0x01200008UL)
  93 #define __get_LCD(B)            __builtin_read32((volatile void *) (B))
  94 #define __set_LCD(B,X)          __builtin_write32((volatile void *) (B), (X))
  95
  96 #define LCD_D                   0x000000ff              /* LCD data bus */
  97 #define LCD_RW                  0x00000100              /* LCD R/W signal */
  98 #define LCD_RS                  0x00000200              /* LCD Register Select */
  99 #define LCD_E                   0x00000400              /* LCD Start Enable Signal */
 100
 101 #define LCD_CMD_CLEAR           (LCD_E|0x001)
 102 #define LCD_CMD_HOME            (LCD_E|0x002)
 103 #define LCD_CMD_CURSOR_INC      (LCD_E|0x004)
 104 #define LCD_CMD_SCROLL_INC      (LCD_E|0x005)
 105 #define LCD_CMD_CURSOR_DEC      (LCD_E|0x006)
 106 #define LCD_CMD_SCROLL_DEC      (LCD_E|0x007)
 107 #define LCD_CMD_OFF             (LCD_E|0x008)
 108 #define LCD_CMD_ON(CRSR,BLINK)  (LCD_E|0x00c|(CRSR<<1)|BLINK)
 109 #define LCD_CMD_CURSOR_MOVE_L   (LCD_E|0x010)
 110 #define LCD_CMD_CURSOR_MOVE_R   (LCD_E|0x014)
 111 #define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018)
 112 #define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c)
 113 #define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2))
 114 #define LCD_CMD_SET_CG_ADDR(X)  (LCD_E|0x040|X)
 115 #define LCD_CMD_SET_DD_ADDR(X)  (LCD_E|0x080|X)
 116 #define LCD_CMD_READ_BUSY       (LCD_E|LCD_RW)
 117 #define LCD_DATA_WRITE(X)       (LCD_E|LCD_RS|(X))
 118 #define LCD_DATA_READ           (LCD_E|LCD_RS|LCD_RW)
 119
 120 #else
 121 /*
 122  * PDK unit specific stuff
 123  */
 124
 125 #include <asm/mb93093-fpga-irqs.h>
 126
 127 #define IRQ_CPU_MB93493_0       IRQ_CPU_EXTERNAL0
 128 #define IRQ_CPU_MB93493_1       IRQ_CPU_EXTERNAL1
 129
 130 #define __region_CS5    0xf0000000      /* MB93493 CSC area (DAV daughter board) */
 131 #define __region_CS5_M          0x00ffffff /* mask */
 132 #define __region_CS5_C          0x00010000 /* control */
 133 #define __region_CS2    0x20000000      /* FPGA registers */
 134 #define __region_CS2_M          0x000fffff
 135 #define __region_CS2_C          0x00000000
 136 #define __region_CS1    0xfc100000      /* LAN registers */
 137 #define __region_CS1_M          0x000fffff
 138 #define __region_CS1_C          0x00010404
 139 #define __region_CS3    0xfc200000      /* MB93493 CSR area (DAV daughter board) */
 140 #define __region_CS3_M          0x000fffff
 141 #define __region_CS3_C          0xc8000000
 142 #define __region_CS4    0xfd000000      /* extra ROMs area */
 143 #define __region_CS4_M          0x00ffffff
 144 #define __region_CS4_C          0x00000f07
 145
 146 #define __region_CS6    0xfe000000      /* not used - hide behind CPU resource I/O regs */
 147 #define __region_CS6_M          0x000fffff
 148 #define __region_CS6_C          0x00000f07
 149 #define __region_CS7    0xfe000000      /* not used - hide behind CPU resource I/O regs */
 150 #define __region_CS7_M          0x000fffff
 151 #define __region_CS7_C          0x00000f07
 152
 153 #define __is_PCI_IO(addr)       0       /* no PCI */
 154 #define __is_PCI_MEM(addr)      0
 155 #define __is_PCI_addr(addr)     0
 156 #define __region_PCI_IO         0
 157 #define __region_PCI_MEM        0
 158 #define __flush_PCI_writes()    do { } while(0)
 159
 160 #define __get_CLKSW()           0UL
 161 #define __get_CLKIN()           66000000UL
 162
 163 #define __addr_LEDS()           (__region_CS2 + 0x00000023UL)
 164 #define __set_LEDS(X)           __builtin_write8((volatile void *) __addr_LEDS(), (X))
 165
 166 #define __addr_FPGATR()         (__region_CS2 + 0x00000030UL)
 167 #define __set_FPGATR(X)         __builtin_write32((volatile void *) __addr_FPGATR(), (X))
 168 #define __get_FPGATR()          __builtin_read32((volatile void *) __addr_FPGATR())
 169
 170 #define MB93093_FPGA_FPGATR_AUDIO_CLK   0x00000003
 171
 172 #define __set_FPGATR_AUDIO_CLK(V) \
 173         __set_FPGATR((__get_FPGATR() & ~MB93093_FPGA_FPGATR_AUDIO_CLK) | (V))
 174
 175 #define MB93093_FPGA_FPGATR_AUDIO_CLK_OFF       0x0
 176 #define MB93093_FPGA_FPGATR_AUDIO_CLK_11MHz     0x1
 177 #define MB93093_FPGA_FPGATR_AUDIO_CLK_12MHz     0x2
 178 #define MB93093_FPGA_FPGATR_AUDIO_CLK_02MHz     0x3
 179
 180 #define MB93093_FPGA_SWR_PUSHSWMASK     (0x1F<<26)
 181 #define MB93093_FPGA_SWR_PUSHSW4        (1<<29)
 182
 183 #define __addr_FPGA_SWR         ((volatile void *)(__region_CS2 + 0x28UL))
 184 #define __get_FPGA_PUSHSW1_5()  (__builtin_read32(__addr_FPGA_SWR) & MB93093_FPGA_SWR_PUSHSWMASK)
 185
 186
 187 #endif
 188
 189 #endif /* _ASM_MB_REGS_H */