arch/arm/mm/flush.c

   1 /*
   2  *  linux/arch/arm/mm/flush.c
   3  *
   4  *  Copyright (C) 1995-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/mm.h>
  12 #include <linux/pagemap.h>
  13
  14 #include <asm/cacheflush.h>
  15 #include <asm/system.h>
  16 #include <asm/tlbflush.h>
  17
  18 #ifdef CONFIG_CPU_CACHE_VIPT
  19
  20 #define ALIAS_FLUSH_START       0xffff4000
  21
  22 #define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
  23
  24 static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
  25 {
  26         unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
  27         const int zero = 0;
  28
  29         set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
  30         flush_tlb_kernel_page(to);
  31
  32         asm(    "mcrr   p15, 0, %1, %0, c14\n"
  33         "       mcr     p15, 0, %2, c7, c10, 4\n"
  34         "       mcr     p15, 0, %2, c7, c5, 0\n"
  35             :
  36             : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
  37             : "cc");
  38 }
  39
  40 void flush_cache_mm(struct mm_struct *mm)
  41 {
  42         if (cache_is_vivt()) {
  43                 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
  44                         __cpuc_flush_user_all();
  45                 return;
  46         }
  47
  48         if (cache_is_vipt_aliasing()) {
  49                 asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
  50                 "       mcr     p15, 0, %0, c7, c5, 0\n"
  51                 "       mcr     p15, 0, %0, c7, c10, 4"
  52                     :
  53                     : "r" (0)
  54                     : "cc");
  55         }
  56 }
  57
  58 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
  59 {
  60         if (cache_is_vivt()) {
  61                 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
  62                         __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
  63                                                 vma->vm_flags);
  64                 return;
  65         }
  66
  67         if (cache_is_vipt_aliasing()) {
  68                 asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
  69                 "       mcr     p15, 0, %0, c7, c5, 0\n"
  70                 "       mcr     p15, 0, %0, c7, c10, 4"
  71                     :
  72                     : "r" (0)
  73                     : "cc");
  74         }
  75 }
  76
  77 void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
  78 {
  79         if (cache_is_vivt()) {
  80                 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
  81                         unsigned long addr = user_addr & PAGE_MASK;
  82                         __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
  83                 }
  84                 return;
  85         }
  86
  87         if (cache_is_vipt_aliasing())
  88                 flush_pfn_alias(pfn, user_addr);
  89 }
  90 #else
  91 #define flush_pfn_alias(pfn,vaddr)      do { } while (0)
  92 #endif
  93
  94 void __flush_dcache_page(struct address_space *mapping, struct page *page)
  95 {
  96         /*
  97          * Writeback any data associated with the kernel mapping of this
  98          * page.  This ensures that data in the physical page is mutually
  99          * coherent with the kernels mapping.
 100          */
 101         __cpuc_flush_dcache_page(page_address(page));
 102
 103         /*
 104          * If this is a page cache page, and we have an aliasing VIPT cache,
 105          * we only need to do one flush - which would be at the relevant
 106          * userspace colour, which is congruent with page->index.
 107          */
 108         if (mapping && cache_is_vipt_aliasing())
 109                 flush_pfn_alias(page_to_pfn(page),
 110                                 page->index << PAGE_CACHE_SHIFT);
 111 }
 112
 113 static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
 114 {
 115         struct mm_struct *mm = current->active_mm;
 116         struct vm_area_struct *mpnt;
 117         struct prio_tree_iter iter;
 118         pgoff_t pgoff;
 119
 120         /*
 121          * There are possible user space mappings of this page:
 122          * - VIVT cache: we need to also write back and invalidate all user
 123          *   data in the current VM view associated with this page.
 124          * - aliasing VIPT: we only need to find one mapping of this page.
 125          */
 126         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 127
 128         flush_dcache_mmap_lock(mapping);
 129         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 130                 unsigned long offset;
 131
 132                 /*
 133                  * If this VMA is not in our MM, we can ignore it.
 134                  */
 135                 if (mpnt->vm_mm != mm)
 136                         continue;
 137                 if (!(mpnt->vm_flags & VM_MAYSHARE))
 138                         continue;
 139                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 140                 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
 141         }
 142         flush_dcache_mmap_unlock(mapping);
 143 }
 144
 145 /*
 146  * Ensure cache coherency between kernel mapping and userspace mapping
 147  * of this page.
 148  *
 149  * We have three cases to consider:
 150  *  - VIPT non-aliasing cache: fully coherent so nothing required.
 151  *  - VIVT: fully aliasing, so we need to handle every alias in our
 152  *          current VM view.
 153  *  - VIPT aliasing: need to handle one alias in our current VM view.
 154  *
 155  * If we need to handle aliasing:
 156  *  If the page only exists in the page cache and there are no user
 157  *  space mappings, we can be lazy and remember that we may have dirty
 158  *  kernel cache lines for later.  Otherwise, we assume we have
 159  *  aliasing mappings.
 160  *
 161  * Note that we disable the lazy flush for SMP.
 162  */
 163 void flush_dcache_page(struct page *page)
 164 {
 165         struct address_space *mapping = page_mapping(page);
 166
 167 #ifndef CONFIG_SMP
 168         if (mapping && !mapping_mapped(mapping))
 169                 set_bit(PG_dcache_dirty, &page->flags);
 170         else
 171 #endif
 172         {
 173                 __flush_dcache_page(mapping, page);
 174                 if (mapping && cache_is_vivt())
 175                         __flush_dcache_aliases(mapping, page);
 176         }
 177 }
 178 EXPORT_SYMBOL(flush_dcache_page);