include/asm-ppc/io.h

   1 #ifdef __KERNEL__
   2 #ifndef _PPC_IO_H
   3 #define _PPC_IO_H
   4
   5 #include <linux/config.h>
   6 #include <linux/string.h>
   7 #include <linux/types.h>
   8
   9 #include <asm/page.h>
  10 #include <asm/byteorder.h>
  11 #include <asm/synch.h>
  12 #include <asm/mmu.h>
  13
  14 #define SIO_CONFIG_RA   0x398
  15 #define SIO_CONFIG_RD   0x399
  16
  17 #define SLOW_DOWN_IO
  18
  19 #define PMAC_ISA_MEM_BASE       0
  20 #define PMAC_PCI_DRAM_OFFSET    0
  21 #define CHRP_ISA_IO_BASE        0xf8000000
  22 #define CHRP_ISA_MEM_BASE       0xf7000000
  23 #define CHRP_PCI_DRAM_OFFSET    0
  24 #define PREP_ISA_IO_BASE        0x80000000
  25 #define PREP_ISA_MEM_BASE       0xc0000000
  26 #define PREP_PCI_DRAM_OFFSET    0x80000000
  27
  28 #if defined(CONFIG_4xx)
  29 #include <asm/ibm4xx.h>
  30 #elif defined(CONFIG_8xx)
  31 #include <asm/mpc8xx.h>
  32 #elif defined(CONFIG_8260)
  33 #include <asm/mpc8260.h>
  34 #elif defined(CONFIG_83xx)
  35 #include <asm/mpc83xx.h>
  36 #elif defined(CONFIG_85xx)
  37 #include <asm/mpc85xx.h>
  38 #elif defined(CONFIG_APUS)
  39 #define _IO_BASE        0
  40 #define _ISA_MEM_BASE   0
  41 #define PCI_DRAM_OFFSET 0
  42 #else /* Everyone else */
  43 #define _IO_BASE        isa_io_base
  44 #define _ISA_MEM_BASE   isa_mem_base
  45 #define PCI_DRAM_OFFSET pci_dram_offset
  46 #endif /* Platform-dependent I/O */
  47
  48 #define ___IO_BASE ((void __iomem *)_IO_BASE)
  49 extern unsigned long isa_io_base;
  50 extern unsigned long isa_mem_base;
  51 extern unsigned long pci_dram_offset;
  52
  53 /*
  54  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
  55  *
  56  * Read operations have additional twi & isync to make sure the read
  57  * is actually performed (i.e. the data has come back) before we start
  58  * executing any following instructions.
  59  */
  60 extern inline int in_8(const volatile unsigned char __iomem *addr)
  61 {
  62         int ret;
  63
  64         __asm__ __volatile__(
  65                 "lbz%U1%X1 %0,%1;\n"
  66                 "twi 0,%0,0;\n"
  67                 "isync" : "=r" (ret) : "m" (*addr));
  68         return ret;
  69 }
  70
  71 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
  72 {
  73         __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
  74 }
  75
  76 extern inline int in_le16(const volatile unsigned short __iomem *addr)
  77 {
  78         int ret;
  79
  80         __asm__ __volatile__("lhbrx %0,0,%1;\n"
  81                              "twi 0,%0,0;\n"
  82                              "isync" : "=r" (ret) :
  83                               "r" (addr), "m" (*addr));
  84         return ret;
  85 }
  86
  87 extern inline int in_be16(const volatile unsigned short __iomem *addr)
  88 {
  89         int ret;
  90
  91         __asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
  92                              "twi 0,%0,0;\n"
  93                              "isync" : "=r" (ret) : "m" (*addr));
  94         return ret;
  95 }
  96
  97 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
  98 {
  99         __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
 100                               "r" (val), "r" (addr));
 101 }
 102
 103 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
 104 {
 105         __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 106 }
 107
 108 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
 109 {
 110         unsigned ret;
 111
 112         __asm__ __volatile__("lwbrx %0,0,%1;\n"
 113                              "twi 0,%0,0;\n"
 114                              "isync" : "=r" (ret) :
 115                              "r" (addr), "m" (*addr));
 116         return ret;
 117 }
 118
 119 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
 120 {
 121         unsigned ret;
 122
 123         __asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
 124                              "twi 0,%0,0;\n"
 125                              "isync" : "=r" (ret) : "m" (*addr));
 126         return ret;
 127 }
 128
 129 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
 130 {
 131         __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
 132                              "r" (val), "r" (addr));
 133 }
 134
 135 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 136 {
 137         __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 138 }
 139 #if defined (CONFIG_8260_PCI9)
 140 #define readb(addr) in_8((volatile u8 *)(addr))
 141 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
 142 #else
 143 static inline __u8 readb(const volatile void __iomem *addr)
 144 {
 145         return in_8(addr);
 146 }
 147 static inline void writeb(__u8 b, volatile void __iomem *addr)
 148 {
 149         out_8(addr, b);
 150 }
 151 #endif
 152
 153 #if defined(CONFIG_APUS)
 154 static inline __u16 readw(const volatile void __iomem *addr)
 155 {
 156         return *(__force volatile __u16 *)(addr);
 157 }
 158 static inline __u32 readl(const volatile void __iomem *addr)
 159 {
 160         return *(__force volatile __u32 *)(addr);
 161 }
 162 static inline void writew(__u16 b, volatile void __iomem *addr)
 163 {
 164         *(__force volatile __u16 *)(addr) = b;
 165 }
 166 static inline void writel(__u32 b, volatile void __iomem *addr)
 167 {
 168         *(__force volatile __u32 *)(addr) = b;
 169 }
 170 #elif defined (CONFIG_8260_PCI9)
 171 /* Use macros if PCI9 workaround enabled */
 172 #define readw(addr) in_le16((volatile u16 *)(addr))
 173 #define readl(addr) in_le32((volatile u32 *)(addr))
 174 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
 175 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
 176 #else
 177 static inline __u16 readw(const volatile void __iomem *addr)
 178 {
 179         return in_le16(addr);
 180 }
 181 static inline __u32 readl(const volatile void __iomem *addr)
 182 {
 183         return in_le32(addr);
 184 }
 185 static inline void writew(__u16 b, volatile void __iomem *addr)
 186 {
 187         out_le16(addr, b);
 188 }
 189 static inline void writel(__u32 b, volatile void __iomem *addr)
 190 {
 191         out_le32(addr, b);
 192 }
 193 #endif /* CONFIG_APUS */
 194
 195 #define readb_relaxed(addr) readb(addr)
 196 #define readw_relaxed(addr) readw(addr)
 197 #define readl_relaxed(addr) readl(addr)
 198
 199 static inline __u8 __raw_readb(const volatile void __iomem *addr)
 200 {
 201         return *(__force volatile __u8 *)(addr);
 202 }
 203 static inline __u16 __raw_readw(const volatile void __iomem *addr)
 204 {
 205         return *(__force volatile __u16 *)(addr);
 206 }
 207 static inline __u32 __raw_readl(const volatile void __iomem *addr)
 208 {
 209         return *(__force volatile __u32 *)(addr);
 210 }
 211 static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
 212 {
 213         *(__force volatile __u8 *)(addr) = b;
 214 }
 215 static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
 216 {
 217         *(__force volatile __u16 *)(addr) = b;
 218 }
 219 static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
 220 {
 221         *(__force volatile __u32 *)(addr) = b;
 222 }
 223
 224 #define mmiowb()
 225
 226 /*
 227  * The insw/outsw/insl/outsl macros don't do byte-swapping.
 228  * They are only used in practice for transferring buffers which
 229  * are arrays of bytes, and byte-swapping is not appropriate in
 230  * that case.  - paulus
 231  */
 232 #define insb(port, buf, ns)     _insb((port)+___IO_BASE, (buf), (ns))
 233 #define outsb(port, buf, ns)    _outsb((port)+___IO_BASE, (buf), (ns))
 234 #define insw(port, buf, ns)     _insw_ns((port)+___IO_BASE, (buf), (ns))
 235 #define outsw(port, buf, ns)    _outsw_ns((port)+___IO_BASE, (buf), (ns))
 236 #define insl(port, buf, nl)     _insl_ns((port)+___IO_BASE, (buf), (nl))
 237 #define outsl(port, buf, nl)    _outsl_ns((port)+___IO_BASE, (buf), (nl))
 238
 239 /*
 240  * On powermacs, we will get a machine check exception if we
 241  * try to read data from a non-existent I/O port.  Because the
 242  * machine check is an asynchronous exception, it isn't
 243  * well-defined which instruction SRR0 will point to when the
 244  * exception occurs.
 245  * With the sequence below (twi; isync; nop), we have found that
 246  * the machine check occurs on one of the three instructions on
 247  * all PPC implementations tested so far.  The twi and isync are
 248  * needed on the 601 (in fact twi; sync works too), the isync and
 249  * nop are needed on 604[e|r], and any of twi, sync or isync will
 250  * work on 603[e], 750, 74xx.
 251  * The twi creates an explicit data dependency on the returned
 252  * value which seems to be needed to make the 601 wait for the
 253  * load to finish.
 254  */
 255
 256 #define __do_in_asm(name, op)                           \
 257 extern __inline__ unsigned int name(unsigned int port)  \
 258 {                                                       \
 259         unsigned int x;                                 \
 260         __asm__ __volatile__(                           \
 261                         op "    %0,0,%1\n"              \
 262                 "1:     twi     0,%0,0\n"               \
 263                 "2:     isync\n"                        \
 264                 "3:     nop\n"                          \
 265                 "4:\n"                                  \
 266                 ".section .fixup,\"ax\"\n"              \
 267                 "5:     li      %0,-1\n"                \
 268                 "       b       4b\n"                   \
 269                 ".previous\n"                           \
 270                 ".section __ex_table,\"a\"\n"           \
 271                 "       .align  2\n"                    \
 272                 "       .long   1b,5b\n"                \
 273                 "       .long   2b,5b\n"                \
 274                 "       .long   3b,5b\n"                \
 275                 ".previous"                             \
 276                 : "=&r" (x)                             \
 277                 : "r" (port + ___IO_BASE));             \
 278         return x;                                       \
 279 }
 280
 281 #define __do_out_asm(name, op)                          \
 282 extern __inline__ void name(unsigned int val, unsigned int port) \
 283 {                                                       \
 284         __asm__ __volatile__(                           \
 285                 op " %0,0,%1\n"                         \
 286                 "1:     sync\n"                         \
 287                 "2:\n"                                  \
 288                 ".section __ex_table,\"a\"\n"           \
 289                 "       .align  2\n"                    \
 290                 "       .long   1b,2b\n"                \
 291                 ".previous"                             \
 292                 : : "r" (val), "r" (port + ___IO_BASE));        \
 293 }
 294
 295 __do_out_asm(outb, "stbx")
 296 #ifdef CONFIG_APUS
 297 __do_in_asm(inb, "lbzx")
 298 __do_in_asm(inw, "lhz%U1%X1")
 299 __do_in_asm(inl, "lwz%U1%X1")
 300 __do_out_asm(outl,"stw%U0%X0")
 301 __do_out_asm(outw, "sth%U0%X0")
 302 #elif defined (CONFIG_8260_PCI9)
 303 /* in asm cannot be defined if PCI9 workaround is used */
 304 #define inb(port)               in_8((port)+___IO_BASE)
 305 #define inw(port)               in_le16((port)+___IO_BASE)
 306 #define inl(port)               in_le32((port)+___IO_BASE)
 307 __do_out_asm(outw, "sthbrx")
 308 __do_out_asm(outl, "stwbrx")
 309 #else
 310 __do_in_asm(inb, "lbzx")
 311 __do_in_asm(inw, "lhbrx")
 312 __do_in_asm(inl, "lwbrx")
 313 __do_out_asm(outw, "sthbrx")
 314 __do_out_asm(outl, "stwbrx")
 315
 316 #endif
 317
 318 #define inb_p(port)             inb((port))
 319 #define outb_p(val, port)       outb((val), (port))
 320 #define inw_p(port)             inw((port))
 321 #define outw_p(val, port)       outw((val), (port))
 322 #define inl_p(port)             inl((port))
 323 #define outl_p(val, port)       outl((val), (port))
 324
 325 extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
 326 extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
 327 extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
 328 extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
 329 extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
 330 extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
 331 extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
 332 extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
 333 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
 334 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
 335
 336 /*
 337  * The *_ns versions below don't do byte-swapping.
 338  * Neither do the standard versions now, these are just here
 339  * for older code.
 340  */
 341 #define insw_ns(port, buf, ns)  _insw_ns((port)+___IO_BASE, (buf), (ns))
 342 #define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
 343 #define insl_ns(port, buf, nl)  _insl_ns((port)+___IO_BASE, (buf), (nl))
 344 #define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
 345
 346
 347 #define IO_SPACE_LIMIT ~0
 348
 349 #if defined (CONFIG_8260_PCI9)
 350 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
 351 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
 352 #define memcpy_toio(a,b,c)     memcpy((void *)(a),(b),(c))
 353 #else
 354 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 355 {
 356         memset((void __force *)addr, val, count);
 357 }
 358 static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
 359 {
 360         memcpy(dst, (void __force *) src, count);
 361 }
 362 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 363 {
 364         memcpy((void __force *) dst, src, count);
 365 }
 366 #endif
 367
 368 #define eth_io_copy_and_sum(a,b,c,d)            eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
 369
 370 /*
 371  * Map in an area of physical address space, for accessing
 372  * I/O devices etc.
 373  */
 374 extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
 375                        unsigned long flags);
 376 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 377 #ifdef CONFIG_44x
 378 extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
 379 #endif
 380 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 381 extern void iounmap(volatile void __iomem *addr);
 382 extern unsigned long iopa(unsigned long addr);
 383 extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
 384 extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
 385                              unsigned int size, int flags);
 386
 387 /*
 388  * The PCI bus is inherently Little-Endian.  The PowerPC is being
 389  * run Big-Endian.  Thus all values which cross the [PCI] barrier
 390  * must be endian-adjusted.  Also, the local DRAM has a different
 391  * address from the PCI point of view, thus buffer addresses also
 392  * have to be modified [mapped] appropriately.
 393  */
 394 extern inline unsigned long virt_to_bus(volatile void * address)
 395 {
 396 #ifndef CONFIG_APUS
 397         if (address == (void *)0)
 398                 return 0;
 399         return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
 400 #else
 401         return iopa ((unsigned long) address);
 402 #endif
 403 }
 404
 405 extern inline void * bus_to_virt(unsigned long address)
 406 {
 407 #ifndef CONFIG_APUS
 408         if (address == 0)
 409                 return NULL;
 410         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 411 #else
 412         return (void*) mm_ptov (address);
 413 #endif
 414 }
 415
 416 /*
 417  * Change virtual addresses to physical addresses and vv, for
 418  * addresses in the area where the kernel has the RAM mapped.
 419  */
 420 extern inline unsigned long virt_to_phys(volatile void * address)
 421 {
 422 #ifndef CONFIG_APUS
 423         return (unsigned long) address - KERNELBASE;
 424 #else
 425         return iopa ((unsigned long) address);
 426 #endif
 427 }
 428
 429 extern inline void * phys_to_virt(unsigned long address)
 430 {
 431 #ifndef CONFIG_APUS
 432         return (void *) (address + KERNELBASE);
 433 #else
 434         return (void*) mm_ptov (address);
 435 #endif
 436 }
 437
 438 /*
 439  * Change "struct page" to physical address.
 440  */
 441 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 442 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 443
 444 /* Enforce in-order execution of data I/O.
 445  * No distinction between read/write on PPC; use eieio for all three.
 446  */
 447 #define iobarrier_rw() eieio()
 448 #define iobarrier_r()  eieio()
 449 #define iobarrier_w()  eieio()
 450
 451 static inline int check_signature(volatile void __iomem * io_addr,
 452         const unsigned char *signature, int length)
 453 {
 454         int retval = 0;
 455         do {
 456                 if (readb(io_addr) != *signature)
 457                         goto out;
 458                 io_addr++;
 459                 signature++;
 460                 length--;
 461         } while (length);
 462         retval = 1;
 463 out:
 464         return retval;
 465 }
 466
 467 /*
 468  * Here comes the ppc implementation of the IOMAP
 469  * interfaces.
 470  */
 471 static inline unsigned int ioread8(void __iomem *addr)
 472 {
 473         return readb(addr);
 474 }
 475
 476 static inline unsigned int ioread16(void __iomem *addr)
 477 {
 478         return readw(addr);
 479 }
 480
 481 static inline unsigned int ioread32(void __iomem *addr)
 482 {
 483         return readl(addr);
 484 }
 485
 486 static inline void iowrite8(u8 val, void __iomem *addr)
 487 {
 488         writeb(val, addr);
 489 }
 490
 491 static inline void iowrite16(u16 val, void __iomem *addr)
 492 {
 493         writew(val, addr);
 494 }
 495
 496 static inline void iowrite32(u32 val, void __iomem *addr)
 497 {
 498         writel(val, addr);
 499 }
 500
 501 static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
 502 {
 503         _insb(addr, dst, count);
 504 }
 505
 506 static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
 507 {
 508         _insw_ns(addr, dst, count);
 509 }
 510
 511 static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
 512 {
 513         _insl_ns(addr, dst, count);
 514 }
 515
 516 static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
 517 {
 518         _outsb(addr, src, count);
 519 }
 520
 521 static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
 522 {
 523         _outsw_ns(addr, src, count);
 524 }
 525
 526 static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
 527 {
 528         _outsl_ns(addr, src, count);
 529 }
 530
 531 /* Create a virtual mapping cookie for an IO port range */
 532 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 533 extern void ioport_unmap(void __iomem *);
 534
 535 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 536 struct pci_dev;
 537 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 538 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 539
 540 #endif /* _PPC_IO_H */
 541
 542 #ifdef CONFIG_8260_PCI9
 543 #include <asm/mpc8260_pci9.h>
 544 #endif
 545
 546 /*
 547  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 548  * access
 549  */
 550 #define xlate_dev_mem_ptr(p)    __va(p)
 551
 552 /*
 553  * Convert a virtual cached pointer to an uncached pointer
 554  */
 555 #define xlate_dev_kmem_ptr(p)   p
 556
 557 #endif /* __KERNEL__ */