v2.6.22.24-op1
[linux-2.6.22.y-op.git] / sound / oss / vwsnd.c
blobd25249a932bfa48abe544bfa7dac49ba0a3e17e7
1 /*
2 * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
3 * onboard audio. See notes in Documentation/sound/oss/vwsnd .
5 * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #undef VWSND_DEBUG /* define for debugging */
25 * XXX to do -
27 * External sync.
28 * Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
29 * Bug - if select() called before read(), pcm_setup() not called.
30 * Bug - output doesn't stop soon enough if process killed.
34 * Things to test -
36 * Will readv/writev work? Write a test.
38 * insmod/rmmod 100 million times.
40 * Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
41 * rate).
43 * Concurrent threads banging on mixer simultaneously, both UP
44 * and SMP kernels. Especially, watch for thread A changing
45 * OUTSRC while thread B changes gain -- both write to the same
46 * ad1843 register.
48 * What happens if a client opens /dev/audio then forks?
49 * Do two procs have /dev/audio open? Test.
51 * Pump audio through the CD, MIC and line inputs and verify that
52 * they mix/mute into the output.
54 * Apps:
55 * amp
56 * mpg123
57 * x11amp
58 * mxv
59 * kmedia
60 * esound
61 * need more input apps
63 * Run tests while bombarding with signals. setitimer(2) will do it... */
66 * This driver is organized in nine sections.
67 * The nine sections are:
69 * debug stuff
70 * low level lithium access
71 * high level lithium access
72 * AD1843 access
73 * PCM I/O
74 * audio driver
75 * mixer driver
76 * probe/attach/unload
77 * initialization and loadable kernel module interface
79 * That is roughly the order of increasing abstraction, so forward
80 * dependencies are minimal.
84 * Locking Notes
86 * INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
87 * open descriptors to this driver. They store it in vwsnd_use_count.
88 * The global device list, vwsnd_dev_list, is immutable when the IN_USE
89 * is true.
91 * devc->open_lock is a semaphore that is used to enforce the
92 * single reader/single writer rule for /dev/audio. The rule is
93 * that each device may have at most one reader and one writer.
94 * Open will block until the previous client has closed the
95 * device, unless O_NONBLOCK is specified.
97 * The semaphore devc->io_mutex serializes PCM I/O syscalls. This
98 * is unnecessary in Linux 2.2, because the kernel lock
99 * serializes read, write, and ioctl globally, but it's there,
100 * ready for the brave, new post-kernel-lock world.
102 * Locking between interrupt and baselevel is handled by the
103 * "lock" spinlock in vwsnd_port (one lock each for read and
104 * write). Each half holds the lock just long enough to see what
105 * area it owns and update its pointers. See pcm_output() and
106 * pcm_input() for most of the gory stuff.
108 * devc->mix_mutex serializes all mixer ioctls. This is also
109 * redundant because of the kernel lock.
111 * The lowest level lock is lith->lithium_lock. It is a
112 * spinlock which is held during the two-register tango of
113 * reading/writing an AD1843 register. See
114 * li_{read,write}_ad1843_reg().
118 * Sample Format Notes
120 * Lithium's DMA engine has two formats: 16-bit 2's complement
121 * and 8-bit unsigned . 16-bit transfers the data unmodified, 2
122 * bytes per sample. 8-bit unsigned transfers 1 byte per sample
123 * and XORs each byte with 0x80. Lithium can input or output
124 * either mono or stereo in either format.
126 * The AD1843 has four formats: 16-bit 2's complement, 8-bit
127 * unsigned, 8-bit mu-Law and 8-bit A-Law.
129 * This driver supports five formats: AFMT_S8, AFMT_U8,
130 * AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
132 * For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
133 * rely on Lithium's XOR to translate between U8 and S8.
135 * For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
136 * the 0x80 bit in software to compensate for Lithium's XOR.
137 * This happens in pcm_copy_{in,out}().
139 * Changes:
140 * 11-10-2000 Bartlomiej Zolnierkiewicz <bkz@linux-ide.org>
141 * Added some __init/__exit
144 #include <linux/module.h>
145 #include <linux/init.h>
147 #include <linux/spinlock.h>
148 #include <linux/smp_lock.h>
149 #include <linux/wait.h>
150 #include <linux/interrupt.h>
151 #include <linux/mutex.h>
153 #include <asm/mach-visws/cobalt.h>
155 #include "sound_config.h"
157 /*****************************************************************************/
158 /* debug stuff */
160 #ifdef VWSND_DEBUG
162 static int shut_up = 1;
165 * dbgassert - called when an assertion fails.
168 static void dbgassert(const char *fcn, int line, const char *expr)
170 if (in_interrupt())
171 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
172 __FILE__, fcn, line, expr);
173 else {
174 int x;
175 printk(KERN_ERR "ASSERTION FAILED, %s:%s:%d %s\n",
176 __FILE__, fcn, line, expr);
177 x = * (volatile int *) 0; /* force proc to exit */
182 * Bunch of useful debug macros:
184 * ASSERT - print unless e nonzero (panic if in interrupt)
185 * DBGDO - include arbitrary code if debugging
186 * DBGX - debug print raw (w/o function name)
187 * DBGP - debug print w/ function name
188 * DBGE - debug print function entry
189 * DBGC - debug print function call
190 * DBGR - debug print function return
191 * DBGXV - debug print raw when verbose
192 * DBGPV - debug print when verbose
193 * DBGEV - debug print function entry when verbose
194 * DBGRV - debug print function return when verbose
197 #define ASSERT(e) ((e) ? (void) 0 : dbgassert(__FUNCTION__, __LINE__, #e))
198 #define DBGDO(x) x
199 #define DBGX(fmt, args...) (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
200 #define DBGP(fmt, args...) (DBGX("%s: " fmt, __FUNCTION__ , ##args))
201 #define DBGE(fmt, args...) (DBGX("%s" fmt, __FUNCTION__ , ##args))
202 #define DBGC(rtn) (DBGP("calling %s\n", rtn))
203 #define DBGR() (DBGP("returning\n"))
204 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
205 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
206 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
207 #define DBGCV(rtn) (shut_up ? 0 : DBGC(rtn))
208 #define DBGRV() (shut_up ? 0 : DBGR())
210 #else /* !VWSND_DEBUG */
212 #define ASSERT(e) ((void) 0)
213 #define DBGDO(x) /* don't */
214 #define DBGX(fmt, args...) ((void) 0)
215 #define DBGP(fmt, args...) ((void) 0)
216 #define DBGE(fmt, args...) ((void) 0)
217 #define DBGC(rtn) ((void) 0)
218 #define DBGR() ((void) 0)
219 #define DBGPV(fmt, args...) ((void) 0)
220 #define DBGXV(fmt, args...) ((void) 0)
221 #define DBGEV(fmt, args...) ((void) 0)
222 #define DBGCV(rtn) ((void) 0)
223 #define DBGRV() ((void) 0)
225 #endif /* !VWSND_DEBUG */
227 /*****************************************************************************/
228 /* low level lithium access */
231 * We need to talk to Lithium registers on three pages. Here are
232 * the pages' offsets from the base address (0xFF001000).
235 enum {
236 LI_PAGE0_OFFSET = 0x01000 - 0x1000, /* FF001000 */
237 LI_PAGE1_OFFSET = 0x0F000 - 0x1000, /* FF00F000 */
238 LI_PAGE2_OFFSET = 0x10000 - 0x1000, /* FF010000 */
241 /* low-level lithium data */
243 typedef struct lithium {
244 void * page0; /* virtual addresses */
245 void * page1;
246 void * page2;
247 spinlock_t lock; /* protects codec and UST/MSC access */
248 } lithium_t;
251 * li_destroy destroys the lithium_t structure and vm mappings.
254 static void li_destroy(lithium_t *lith)
256 if (lith->page0) {
257 iounmap(lith->page0);
258 lith->page0 = NULL;
260 if (lith->page1) {
261 iounmap(lith->page1);
262 lith->page1 = NULL;
264 if (lith->page2) {
265 iounmap(lith->page2);
266 lith->page2 = NULL;
271 * li_create initializes the lithium_t structure and sets up vm mappings
272 * to access the registers.
273 * Returns 0 on success, -errno on failure.
276 static int __init li_create(lithium_t *lith, unsigned long baseaddr)
278 spin_lock_init(&lith->lock);
279 lith->page0 = ioremap_nocache(baseaddr + LI_PAGE0_OFFSET, PAGE_SIZE);
280 lith->page1 = ioremap_nocache(baseaddr + LI_PAGE1_OFFSET, PAGE_SIZE);
281 lith->page2 = ioremap_nocache(baseaddr + LI_PAGE2_OFFSET, PAGE_SIZE);
282 if (!lith->page0 || !lith->page1 || !lith->page2) {
283 li_destroy(lith);
284 return -ENOMEM;
286 return 0;
290 * basic register accessors - read/write long/byte
293 static __inline__ unsigned long li_readl(lithium_t *lith, int off)
295 return * (volatile unsigned long *) (lith->page0 + off);
298 static __inline__ unsigned char li_readb(lithium_t *lith, int off)
300 return * (volatile unsigned char *) (lith->page0 + off);
303 static __inline__ void li_writel(lithium_t *lith, int off, unsigned long val)
305 * (volatile unsigned long *) (lith->page0 + off) = val;
308 static __inline__ void li_writeb(lithium_t *lith, int off, unsigned char val)
310 * (volatile unsigned char *) (lith->page0 + off) = val;
313 /*****************************************************************************/
314 /* High Level Lithium Access */
317 * Lithium DMA Notes
319 * Lithium has two dedicated DMA channels for audio. They are known
320 * as comm1 and comm2 (communication areas 1 and 2). Comm1 is for
321 * input, and comm2 is for output. Each is controlled by three
322 * registers: BASE (base address), CFG (config) and CCTL
323 * (config/control).
325 * Each DMA channel points to a physically contiguous ring buffer in
326 * main memory of up to 8 Kbytes. (This driver always uses 8 Kb.)
327 * There are three pointers into the ring buffer: read, write, and
328 * trigger. The pointers are 8 bits each. Each pointer points to
329 * 32-byte "chunks" of data. The DMA engine moves 32 bytes at a time,
330 * so there is no finer-granularity control.
332 * In comm1, the hardware updates the write ptr, and software updates
333 * the read ptr. In comm2, it's the opposite: hardware updates the
334 * read ptr, and software updates the write ptr. I designate the
335 * hardware-updated ptr as the hwptr, and the software-updated ptr as
336 * the swptr.
338 * The trigger ptr and trigger mask are used to trigger interrupts.
339 * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
341 * Trigger Mask Value
343 * A three bit wide field that represents a power of two mask
344 * that is used whenever the trigger pointer is compared to its
345 * respective read or write pointer. A value of zero here
346 * implies a mask of 0xFF and a value of seven implies a mask
347 * 0x01. This value can be used to sub-divide the ring buffer
348 * into pie sections so that interrupts monitor the progress of
349 * hardware from section to section.
351 * My interpretation of that is, whenever the hw ptr is updated, it is
352 * compared with the trigger ptr, and the result is masked by the
353 * trigger mask. (Actually, by the complement of the trigger mask.)
354 * If the result is zero, an interrupt is triggered. I.e., interrupt
355 * if ((hwptr & ~mask) == (trptr & ~mask)). The mask is formed from
356 * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
358 * In yet different words, setting tmreg to 0 causes an interrupt after
359 * every 256 DMA chunks (8192 bytes) or once per traversal of the
360 * ring buffer. Setting it to 7 caues an interrupt every 2 DMA chunks
361 * (64 bytes) or 128 times per traversal of the ring buffer.
364 /* Lithium register offsets and bit definitions */
366 #define LI_HOST_CONTROLLER 0x000
367 # define LI_HC_RESET 0x00008000
368 # define LI_HC_LINK_ENABLE 0x00004000
369 # define LI_HC_LINK_FAILURE 0x00000004
370 # define LI_HC_LINK_CODEC 0x00000002
371 # define LI_HC_LINK_READY 0x00000001
373 #define LI_INTR_STATUS 0x010
374 #define LI_INTR_MASK 0x014
375 # define LI_INTR_LINK_ERR 0x00008000
376 # define LI_INTR_COMM2_TRIG 0x00000008
377 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
378 # define LI_INTR_COMM1_TRIG 0x00000002
379 # define LI_INTR_COMM1_OVERFLOW 0x00000001
381 #define LI_CODEC_COMMAND 0x018
382 # define LI_CC_BUSY 0x00008000
383 # define LI_CC_DIR 0x00000080
384 # define LI_CC_DIR_RD LI_CC_DIR
385 # define LI_CC_DIR_WR (!LI_CC_DIR)
386 # define LI_CC_ADDR_MASK 0x0000007F
388 #define LI_CODEC_DATA 0x01C
390 #define LI_COMM1_BASE 0x100
391 #define LI_COMM1_CTL 0x104
392 # define LI_CCTL_RESET 0x80000000
393 # define LI_CCTL_SIZE 0x70000000
394 # define LI_CCTL_DMA_ENABLE 0x08000000
395 # define LI_CCTL_TMASK 0x07000000 /* trigger mask */
396 # define LI_CCTL_TPTR 0x00FF0000 /* trigger pointer */
397 # define LI_CCTL_RPTR 0x0000FF00
398 # define LI_CCTL_WPTR 0x000000FF
399 #define LI_COMM1_CFG 0x108
400 # define LI_CCFG_LOCK 0x00008000
401 # define LI_CCFG_SLOT 0x00000070
402 # define LI_CCFG_DIRECTION 0x00000008
403 # define LI_CCFG_DIR_IN (!LI_CCFG_DIRECTION)
404 # define LI_CCFG_DIR_OUT LI_CCFG_DIRECTION
405 # define LI_CCFG_MODE 0x00000004
406 # define LI_CCFG_MODE_MONO (!LI_CCFG_MODE)
407 # define LI_CCFG_MODE_STEREO LI_CCFG_MODE
408 # define LI_CCFG_FORMAT 0x00000003
409 # define LI_CCFG_FMT_8BIT 0x00000000
410 # define LI_CCFG_FMT_16BIT 0x00000001
411 #define LI_COMM2_BASE 0x10C
412 #define LI_COMM2_CTL 0x110
413 /* bit definitions are the same as LI_COMM1_CTL */
414 #define LI_COMM2_CFG 0x114
415 /* bit definitions are the same as LI_COMM1_CFG */
417 #define LI_UST_LOW 0x200 /* 64-bit Unadjusted System Time is */
418 #define LI_UST_HIGH 0x204 /* microseconds since boot */
420 #define LI_AUDIO1_UST 0x300 /* UST-MSC pairs */
421 #define LI_AUDIO1_MSC 0x304 /* MSC (Media Stream Counter) */
422 #define LI_AUDIO2_UST 0x308 /* counts samples actually */
423 #define LI_AUDIO2_MSC 0x30C /* processed as of time UST */
426 * Lithium's DMA engine operates on chunks of 32 bytes. We call that
427 * a DMACHUNK.
430 #define DMACHUNK_SHIFT 5
431 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
432 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
433 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
436 * Two convenient macros to shift bitfields into/out of position.
438 * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
439 * As long as mask is constant, we trust the compiler will change the
440 * multipy and divide into shifts.
443 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
444 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
447 * dma_chan_desc is invariant information about a Lithium
448 * DMA channel. There are two instances, li_comm1 and li_comm2.
450 * Note that the CCTL register fields are write ptr and read ptr, but what
451 * we care about are which pointer is updated by software and which by
452 * hardware.
455 typedef struct dma_chan_desc {
456 int basereg;
457 int cfgreg;
458 int ctlreg;
459 int hwptrreg;
460 int swptrreg;
461 int ustreg;
462 int mscreg;
463 unsigned long swptrmask;
464 int ad1843_slot;
465 int direction; /* LI_CCTL_DIR_IN/OUT */
466 } dma_chan_desc_t;
468 static const dma_chan_desc_t li_comm1 = {
469 LI_COMM1_BASE, /* base register offset */
470 LI_COMM1_CFG, /* config register offset */
471 LI_COMM1_CTL, /* control register offset */
472 LI_COMM1_CTL + 0, /* hw ptr reg offset (write ptr) */
473 LI_COMM1_CTL + 1, /* sw ptr reg offset (read ptr) */
474 LI_AUDIO1_UST, /* ust reg offset */
475 LI_AUDIO1_MSC, /* msc reg offset */
476 LI_CCTL_RPTR, /* sw ptr bitmask in ctlval */
477 2, /* ad1843 serial slot */
478 LI_CCFG_DIR_IN /* direction */
481 static const dma_chan_desc_t li_comm2 = {
482 LI_COMM2_BASE, /* base register offset */
483 LI_COMM2_CFG, /* config register offset */
484 LI_COMM2_CTL, /* control register offset */
485 LI_COMM2_CTL + 1, /* hw ptr reg offset (read ptr) */
486 LI_COMM2_CTL + 0, /* sw ptr reg offset (writr ptr) */
487 LI_AUDIO2_UST, /* ust reg offset */
488 LI_AUDIO2_MSC, /* msc reg offset */
489 LI_CCTL_WPTR, /* sw ptr bitmask in ctlval */
490 2, /* ad1843 serial slot */
491 LI_CCFG_DIR_OUT /* direction */
495 * dma_chan is variable information about a Lithium DMA channel.
497 * The desc field points to invariant information.
498 * The lith field points to a lithium_t which is passed
499 * to li_read* and li_write* to access the registers.
500 * The *val fields shadow the lithium registers' contents.
503 typedef struct dma_chan {
504 const dma_chan_desc_t *desc;
505 lithium_t *lith;
506 unsigned long baseval;
507 unsigned long cfgval;
508 unsigned long ctlval;
509 } dma_chan_t;
512 * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
513 * UST is time in microseconds since the system booted, and MSC is a
514 * counter that increments with every audio sample.
517 typedef struct ustmsc {
518 unsigned long long ust;
519 unsigned long msc;
520 } ustmsc_t;
523 * li_ad1843_wait waits until lithium says the AD1843 register
524 * exchange is not busy. Returns 0 on success, -EBUSY on timeout.
526 * Locking: must be called with lithium_lock held.
529 static int li_ad1843_wait(lithium_t *lith)
531 unsigned long later = jiffies + 2;
532 while (li_readl(lith, LI_CODEC_COMMAND) & LI_CC_BUSY)
533 if (time_after_eq(jiffies, later))
534 return -EBUSY;
535 return 0;
539 * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
541 * Returns unsigned register value on success, -errno on failure.
544 static int li_read_ad1843_reg(lithium_t *lith, int reg)
546 int val;
548 ASSERT(!in_interrupt());
549 spin_lock(&lith->lock);
551 val = li_ad1843_wait(lith);
552 if (val == 0) {
553 li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_RD | reg);
554 val = li_ad1843_wait(lith);
556 if (val == 0)
557 val = li_readl(lith, LI_CODEC_DATA);
559 spin_unlock(&lith->lock);
561 DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
562 lith, reg, val);
564 return val;
568 * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
571 static void li_write_ad1843_reg(lithium_t *lith, int reg, int newval)
573 spin_lock(&lith->lock);
575 if (li_ad1843_wait(lith) == 0) {
576 li_writel(lith, LI_CODEC_DATA, newval);
577 li_writel(lith, LI_CODEC_COMMAND, LI_CC_DIR_WR | reg);
580 spin_unlock(&lith->lock);
584 * li_setup_dma calculates all the register settings for DMA in a particular
585 * mode. It takes too many arguments.
588 static void li_setup_dma(dma_chan_t *chan,
589 const dma_chan_desc_t *desc,
590 lithium_t *lith,
591 unsigned long buffer_paddr,
592 int bufshift,
593 int fragshift,
594 int channels,
595 int sampsize)
597 unsigned long mode, format;
598 unsigned long size, tmask;
600 DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
601 "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
602 chan, desc, lith, buffer_paddr,
603 bufshift, fragshift, channels, sampsize);
605 /* Reset the channel first. */
607 li_writel(lith, desc->ctlreg, LI_CCTL_RESET);
609 ASSERT(channels == 1 || channels == 2);
610 if (channels == 2)
611 mode = LI_CCFG_MODE_STEREO;
612 else
613 mode = LI_CCFG_MODE_MONO;
614 ASSERT(sampsize == 1 || sampsize == 2);
615 if (sampsize == 2)
616 format = LI_CCFG_FMT_16BIT;
617 else
618 format = LI_CCFG_FMT_8BIT;
619 chan->desc = desc;
620 chan->lith = lith;
623 * Lithium DMA address register takes a 40-bit physical
624 * address, right-shifted by 8 so it fits in 32 bits. Bit 37
625 * must be set -- it enables cache coherence.
628 ASSERT(!(buffer_paddr & 0xFF));
629 chan->baseval = (buffer_paddr >> 8) | 1 << (37 - 8);
631 chan->cfgval = (!LI_CCFG_LOCK |
632 SHIFT_FIELD(desc->ad1843_slot, LI_CCFG_SLOT) |
633 desc->direction |
634 mode |
635 format);
637 size = bufshift - 6;
638 tmask = 13 - fragshift; /* See Lithium DMA Notes above. */
639 ASSERT(size >= 2 && size <= 7);
640 ASSERT(tmask >= 1 && tmask <= 7);
641 chan->ctlval = (!LI_CCTL_RESET |
642 SHIFT_FIELD(size, LI_CCTL_SIZE) |
643 !LI_CCTL_DMA_ENABLE |
644 SHIFT_FIELD(tmask, LI_CCTL_TMASK) |
645 SHIFT_FIELD(0, LI_CCTL_TPTR));
647 DBGPV("basereg 0x%x = 0x%lx\n", desc->basereg, chan->baseval);
648 DBGPV("cfgreg 0x%x = 0x%lx\n", desc->cfgreg, chan->cfgval);
649 DBGPV("ctlreg 0x%x = 0x%lx\n", desc->ctlreg, chan->ctlval);
651 li_writel(lith, desc->basereg, chan->baseval);
652 li_writel(lith, desc->cfgreg, chan->cfgval);
653 li_writel(lith, desc->ctlreg, chan->ctlval);
655 DBGRV();
658 static void li_shutdown_dma(dma_chan_t *chan)
660 lithium_t *lith = chan->lith;
661 void * lith1 = lith->page1;
663 DBGEV("(chan=0x%p)\n", chan);
665 chan->ctlval &= ~LI_CCTL_DMA_ENABLE;
666 DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
667 li_writel(lith, chan->desc->ctlreg, chan->ctlval);
670 * Offset 0x500 on Lithium page 1 is an undocumented,
671 * unsupported register that holds the zero sample value.
672 * Lithium is supposed to output zero samples when DMA is
673 * inactive, and repeat the last sample when DMA underflows.
674 * But it has a bug, where, after underflow occurs, the zero
675 * sample is not reset.
677 * I expect this to break in a future rev of Lithium.
680 if (lith1 && chan->desc->direction == LI_CCFG_DIR_OUT)
681 * (volatile unsigned long *) (lith1 + 0x500) = 0;
685 * li_activate_dma always starts dma at the beginning of the buffer.
687 * N.B., these may be called from interrupt.
690 static __inline__ void li_activate_dma(dma_chan_t *chan)
692 chan->ctlval |= LI_CCTL_DMA_ENABLE;
693 DBGPV("ctlval = 0x%lx\n", chan->ctlval);
694 li_writel(chan->lith, chan->desc->ctlreg, chan->ctlval);
697 static void li_deactivate_dma(dma_chan_t *chan)
699 lithium_t *lith = chan->lith;
700 void * lith2 = lith->page2;
702 chan->ctlval &= ~(LI_CCTL_DMA_ENABLE | LI_CCTL_RPTR | LI_CCTL_WPTR);
703 DBGPV("ctlval = 0x%lx\n", chan->ctlval);
704 DBGPV("ctlreg 0x%x = 0x%lx\n", chan->desc->ctlreg, chan->ctlval);
705 li_writel(lith, chan->desc->ctlreg, chan->ctlval);
708 * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
709 * unsupported registers that are internal copies of the DMA
710 * read and write pointers. Because of a Lithium bug, these
711 * registers aren't zeroed correctly when DMA is shut off. So
712 * we whack them directly.
714 * I expect this to break in a future rev of Lithium.
717 if (lith2 && chan->desc->direction == LI_CCFG_DIR_OUT) {
718 * (volatile unsigned long *) (lith2 + 0x98) = 0;
719 * (volatile unsigned long *) (lith2 + 0x9C) = 0;
724 * read/write the ring buffer pointers. These routines' arguments and results
725 * are byte offsets from the beginning of the ring buffer.
728 static __inline__ int li_read_swptr(dma_chan_t *chan)
730 const unsigned long mask = chan->desc->swptrmask;
732 return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan->ctlval, mask));
735 static __inline__ int li_read_hwptr(dma_chan_t *chan)
737 return CHUNKS_TO_BYTES(li_readb(chan->lith, chan->desc->hwptrreg));
740 static __inline__ void li_write_swptr(dma_chan_t *chan, int val)
742 const unsigned long mask = chan->desc->swptrmask;
744 ASSERT(!(val & ~CHUNKS_TO_BYTES(0xFF)));
745 val = BYTES_TO_CHUNKS(val);
746 chan->ctlval = (chan->ctlval & ~mask) | SHIFT_FIELD(val, mask);
747 li_writeb(chan->lith, chan->desc->swptrreg, val);
750 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
752 static void li_read_USTMSC(dma_chan_t *chan, ustmsc_t *ustmsc)
754 lithium_t *lith = chan->lith;
755 const dma_chan_desc_t *desc = chan->desc;
756 unsigned long now_low, now_high0, now_high1, chan_ust;
758 spin_lock(&lith->lock);
761 * retry until we do all five reads without the
762 * high word changing. (High word increments
763 * every 2^32 microseconds, i.e., not often)
765 do {
766 now_high0 = li_readl(lith, LI_UST_HIGH);
767 now_low = li_readl(lith, LI_UST_LOW);
770 * Lithium guarantees these two reads will be
771 * atomic -- ust will not increment after msc
772 * is read.
775 ustmsc->msc = li_readl(lith, desc->mscreg);
776 chan_ust = li_readl(lith, desc->ustreg);
778 now_high1 = li_readl(lith, LI_UST_HIGH);
779 } while (now_high0 != now_high1);
781 spin_unlock(&lith->lock);
782 ustmsc->ust = ((unsigned long long) now_high0 << 32 | chan_ust);
785 static void li_enable_interrupts(lithium_t *lith, unsigned int mask)
787 DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
789 /* clear any already-pending interrupts. */
791 li_writel(lith, LI_INTR_STATUS, mask);
793 /* enable the interrupts. */
795 mask |= li_readl(lith, LI_INTR_MASK);
796 li_writel(lith, LI_INTR_MASK, mask);
799 static void li_disable_interrupts(lithium_t *lith, unsigned int mask)
801 unsigned int keepmask;
803 DBGEV("(lith=0x%p, mask=0x%x)\n", lith, mask);
805 /* disable the interrupts */
807 keepmask = li_readl(lith, LI_INTR_MASK) & ~mask;
808 li_writel(lith, LI_INTR_MASK, keepmask);
810 /* clear any pending interrupts. */
812 li_writel(lith, LI_INTR_STATUS, mask);
815 /* Get the interrupt status and clear all pending interrupts. */
817 static unsigned int li_get_clear_intr_status(lithium_t *lith)
819 unsigned int status;
821 status = li_readl(lith, LI_INTR_STATUS);
822 li_writel(lith, LI_INTR_STATUS, ~0);
823 return status & li_readl(lith, LI_INTR_MASK);
826 static int li_init(lithium_t *lith)
828 /* 1. System power supplies stabilize. */
830 /* 2. Assert the ~RESET signal. */
832 li_writel(lith, LI_HOST_CONTROLLER, LI_HC_RESET);
833 udelay(1);
835 /* 3. Deassert the ~RESET signal and enter a wait period to allow
836 the AD1843 internal clocks and the external crystal oscillator
837 to stabilize. */
839 li_writel(lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
840 udelay(1);
842 return 0;
845 /*****************************************************************************/
846 /* AD1843 access */
849 * AD1843 bitfield definitions. All are named as in the AD1843 data
850 * sheet, with ad1843_ prepended and individual bit numbers removed.
852 * E.g., bits LSS0 through LSS2 become ad1843_LSS.
854 * Only the bitfields we need are defined.
857 typedef struct ad1843_bitfield {
858 char reg;
859 char lo_bit;
860 char nbits;
861 } ad1843_bitfield_t;
863 static const ad1843_bitfield_t
864 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
865 ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */
866 ad1843_RIG = { 2, 0, 4 }, /* Right ADC Input Gain */
867 ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
868 ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */
869 ad1843_LIG = { 2, 8, 4 }, /* Left ADC Input Gain */
870 ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
871 ad1843_LSS = { 2, 13, 3 }, /* Left ADC Source Select */
872 ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
873 ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
874 ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
875 ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
876 ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
877 ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
878 ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
879 ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
880 ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
881 ad1843_RMCMM = { 7, 7, 1 }, /* Right Mic Mix Mute */
882 ad1843_LMCM = { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
883 ad1843_LMCMM = { 7, 15, 1 }, /* Left Mic Mix Mute */
884 ad1843_HPOS = { 8, 4, 1 }, /* Headphone Output Voltage Swing */
885 ad1843_HPOM = { 8, 5, 1 }, /* Headphone Output Mute */
886 ad1843_RDA1G = { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
887 ad1843_RDA1GM = { 9, 7, 1 }, /* Right DAC1 Analog Mute */
888 ad1843_LDA1G = { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
889 ad1843_LDA1GM = { 9, 15, 1 }, /* Left DAC1 Analog Mute */
890 ad1843_RDA1AM = { 11, 7, 1 }, /* Right DAC1 Digital Mute */
891 ad1843_LDA1AM = { 11, 15, 1 }, /* Left DAC1 Digital Mute */
892 ad1843_ADLC = { 15, 0, 2 }, /* ADC Left Sample Rate Source */
893 ad1843_ADRC = { 15, 2, 2 }, /* ADC Right Sample Rate Source */
894 ad1843_DA1C = { 15, 8, 2 }, /* DAC1 Sample Rate Source */
895 ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
896 ad1843_C2C = { 20, 0, 16 }, /* Clock 1 Sample Rate Select */
897 ad1843_DAADL = { 25, 4, 2 }, /* Digital ADC Left Source Select */
898 ad1843_DAADR = { 25, 6, 2 }, /* Digital ADC Right Source Select */
899 ad1843_DRSFLT = { 25, 15, 1 }, /* Digital Reampler Filter Mode */
900 ad1843_ADLF = { 26, 0, 2 }, /* ADC Left Channel Data Format */
901 ad1843_ADRF = { 26, 2, 2 }, /* ADC Right Channel Data Format */
902 ad1843_ADTLK = { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
903 ad1843_SCF = { 26, 7, 1 }, /* SCLK Frequency Select */
904 ad1843_DA1F = { 26, 8, 2 }, /* DAC1 Data Format Select */
905 ad1843_DA1SM = { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
906 ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */
907 ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */
908 ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */
909 ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */
910 ad1843_DA1EN = { 27, 8, 1 }, /* DAC1 Enable */
911 ad1843_DA2EN = { 27, 9, 1 }, /* DAC2 Enable */
912 ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */
913 ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */
914 ad1843_PDNI = { 28, 15, 1 }; /* Converter Power Down */
917 * The various registers of the AD1843 use three different formats for
918 * specifying gain. The ad1843_gain structure parameterizes the
919 * formats.
922 typedef struct ad1843_gain {
924 int negative; /* nonzero if gain is negative. */
925 const ad1843_bitfield_t *lfield;
926 const ad1843_bitfield_t *rfield;
928 } ad1843_gain_t;
930 static const ad1843_gain_t ad1843_gain_RECLEV
931 = { 0, &ad1843_LIG, &ad1843_RIG };
932 static const ad1843_gain_t ad1843_gain_LINE
933 = { 1, &ad1843_LX1M, &ad1843_RX1M };
934 static const ad1843_gain_t ad1843_gain_CD
935 = { 1, &ad1843_LX2M, &ad1843_RX2M };
936 static const ad1843_gain_t ad1843_gain_MIC
937 = { 1, &ad1843_LMCM, &ad1843_RMCM };
938 static const ad1843_gain_t ad1843_gain_PCM
939 = { 1, &ad1843_LDA1G, &ad1843_RDA1G };
941 /* read the current value of an AD1843 bitfield. */
943 static int ad1843_read_bits(lithium_t *lith, const ad1843_bitfield_t *field)
945 int w = li_read_ad1843_reg(lith, field->reg);
946 int val = w >> field->lo_bit & ((1 << field->nbits) - 1);
948 DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
949 lith, field->reg, field->lo_bit, field->nbits, val);
951 return val;
955 * write a new value to an AD1843 bitfield and return the old value.
958 static int ad1843_write_bits(lithium_t *lith,
959 const ad1843_bitfield_t *field,
960 int newval)
962 int w = li_read_ad1843_reg(lith, field->reg);
963 int mask = ((1 << field->nbits) - 1) << field->lo_bit;
964 int oldval = (w & mask) >> field->lo_bit;
965 int newbits = (newval << field->lo_bit) & mask;
966 w = (w & ~mask) | newbits;
967 (void) li_write_ad1843_reg(lith, field->reg, w);
969 DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
970 "returns 0x%x\n",
971 lith, field->reg, field->lo_bit, field->nbits, newval,
972 oldval);
974 return oldval;
978 * ad1843_read_multi reads multiple bitfields from the same AD1843
979 * register. It uses a single read cycle to do it. (Reading the
980 * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
981 * microseconds.)
983 * Called ike this.
985 * ad1843_read_multi(lith, nfields,
986 * &ad1843_FIELD1, &val1,
987 * &ad1843_FIELD2, &val2, ...);
990 static void ad1843_read_multi(lithium_t *lith, int argcount, ...)
992 va_list ap;
993 const ad1843_bitfield_t *fp;
994 int w = 0, mask, *value, reg = -1;
996 va_start(ap, argcount);
997 while (--argcount >= 0) {
998 fp = va_arg(ap, const ad1843_bitfield_t *);
999 value = va_arg(ap, int *);
1000 if (reg == -1) {
1001 reg = fp->reg;
1002 w = li_read_ad1843_reg(lith, reg);
1004 ASSERT(reg == fp->reg);
1005 mask = (1 << fp->nbits) - 1;
1006 *value = w >> fp->lo_bit & mask;
1008 va_end(ap);
1012 * ad1843_write_multi stores multiple bitfields into the same AD1843
1013 * register. It uses one read and one write cycle to do it.
1015 * Called like this.
1017 * ad1843_write_multi(lith, nfields,
1018 * &ad1843_FIELD1, val1,
1019 * &ad1843_FIELF2, val2, ...);
1022 static void ad1843_write_multi(lithium_t *lith, int argcount, ...)
1024 va_list ap;
1025 int reg;
1026 const ad1843_bitfield_t *fp;
1027 int value;
1028 int w, m, mask, bits;
1030 mask = 0;
1031 bits = 0;
1032 reg = -1;
1034 va_start(ap, argcount);
1035 while (--argcount >= 0) {
1036 fp = va_arg(ap, const ad1843_bitfield_t *);
1037 value = va_arg(ap, int);
1038 if (reg == -1)
1039 reg = fp->reg;
1040 ASSERT(fp->reg == reg);
1041 m = ((1 << fp->nbits) - 1) << fp->lo_bit;
1042 mask |= m;
1043 bits |= (value << fp->lo_bit) & m;
1045 va_end(ap);
1046 ASSERT(!(bits & ~mask));
1047 if (~mask & 0xFFFF)
1048 w = li_read_ad1843_reg(lith, reg);
1049 else
1050 w = 0;
1051 w = (w & ~mask) | bits;
1052 (void) li_write_ad1843_reg(lith, reg, w);
1056 * ad1843_get_gain reads the specified register and extracts the gain value
1057 * using the supplied gain type. It returns the gain in OSS format.
1060 static int ad1843_get_gain(lithium_t *lith, const ad1843_gain_t *gp)
1062 int lg, rg;
1063 unsigned short mask = (1 << gp->lfield->nbits) - 1;
1065 ad1843_read_multi(lith, 2, gp->lfield, &lg, gp->rfield, &rg);
1066 if (gp->negative) {
1067 lg = mask - lg;
1068 rg = mask - rg;
1070 lg = (lg * 100 + (mask >> 1)) / mask;
1071 rg = (rg * 100 + (mask >> 1)) / mask;
1072 return lg << 0 | rg << 8;
1076 * Set an audio channel's gain. Converts from OSS format to AD1843's
1077 * format.
1079 * Returns the new gain, which may be lower than the old gain.
1082 static int ad1843_set_gain(lithium_t *lith,
1083 const ad1843_gain_t *gp,
1084 int newval)
1086 unsigned short mask = (1 << gp->lfield->nbits) - 1;
1088 int lg = newval >> 0 & 0xFF;
1089 int rg = newval >> 8;
1090 if (lg < 0 || lg > 100 || rg < 0 || rg > 100)
1091 return -EINVAL;
1092 lg = (lg * mask + (mask >> 1)) / 100;
1093 rg = (rg * mask + (mask >> 1)) / 100;
1094 if (gp->negative) {
1095 lg = mask - lg;
1096 rg = mask - rg;
1098 ad1843_write_multi(lith, 2, gp->lfield, lg, gp->rfield, rg);
1099 return ad1843_get_gain(lith, gp);
1102 /* Returns the current recording source, in OSS format. */
1104 static int ad1843_get_recsrc(lithium_t *lith)
1106 int ls = ad1843_read_bits(lith, &ad1843_LSS);
1108 switch (ls) {
1109 case 1:
1110 return SOUND_MASK_MIC;
1111 case 2:
1112 return SOUND_MASK_LINE;
1113 case 3:
1114 return SOUND_MASK_CD;
1115 case 6:
1116 return SOUND_MASK_PCM;
1117 default:
1118 ASSERT(0);
1119 return -1;
1124 * Enable/disable digital resample mode in the AD1843.
1126 * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1127 * while switching modes. So we save DA1's state (DA2's state is not
1128 * interesting), power them down, switch into/out of resample mode,
1129 * power them up, and restore state.
1131 * This will cause audible glitches if D/A or A/D is going on, so the
1132 * driver disallows that (in mixer_write_ioctl()).
1134 * The open question is, is this worth doing? I'm leaving it in,
1135 * because it's written, but...
1138 static void ad1843_set_resample_mode(lithium_t *lith, int onoff)
1140 /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1141 int save_da1 = li_read_ad1843_reg(lith, 9);
1143 /* Power down A/D and D/A. */
1144 ad1843_write_multi(lith, 4,
1145 &ad1843_DA1EN, 0,
1146 &ad1843_DA2EN, 0,
1147 &ad1843_ADLEN, 0,
1148 &ad1843_ADREN, 0);
1150 /* Switch mode */
1151 ASSERT(onoff == 0 || onoff == 1);
1152 ad1843_write_bits(lith, &ad1843_DRSFLT, onoff);
1154 /* Power up A/D and D/A. */
1155 ad1843_write_multi(lith, 3,
1156 &ad1843_DA1EN, 1,
1157 &ad1843_ADLEN, 1,
1158 &ad1843_ADREN, 1);
1160 /* Restore DA1 mute and gain. */
1161 li_write_ad1843_reg(lith, 9, save_da1);
1165 * Set recording source. Arg newsrc specifies an OSS channel mask.
1167 * The complication is that when we switch into/out of loopback mode
1168 * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1169 * digital resampling mode.
1171 * Returns newsrc on success, -errno on failure.
1174 static int ad1843_set_recsrc(lithium_t *lith, int newsrc)
1176 int bits;
1177 int oldbits;
1179 switch (newsrc) {
1180 case SOUND_MASK_PCM:
1181 bits = 6;
1182 break;
1184 case SOUND_MASK_MIC:
1185 bits = 1;
1186 break;
1188 case SOUND_MASK_LINE:
1189 bits = 2;
1190 break;
1192 case SOUND_MASK_CD:
1193 bits = 3;
1194 break;
1196 default:
1197 return -EINVAL;
1199 oldbits = ad1843_read_bits(lith, &ad1843_LSS);
1200 if (newsrc == SOUND_MASK_PCM && oldbits != 6) {
1201 DBGP("enabling digital resample mode\n");
1202 ad1843_set_resample_mode(lith, 1);
1203 ad1843_write_multi(lith, 2,
1204 &ad1843_DAADL, 2,
1205 &ad1843_DAADR, 2);
1206 } else if (newsrc != SOUND_MASK_PCM && oldbits == 6) {
1207 DBGP("disabling digital resample mode\n");
1208 ad1843_set_resample_mode(lith, 0);
1209 ad1843_write_multi(lith, 2,
1210 &ad1843_DAADL, 0,
1211 &ad1843_DAADR, 0);
1213 ad1843_write_multi(lith, 2, &ad1843_LSS, bits, &ad1843_RSS, bits);
1214 return newsrc;
1218 * Return current output sources, in OSS format.
1221 static int ad1843_get_outsrc(lithium_t *lith)
1223 int pcm, line, mic, cd;
1225 pcm = ad1843_read_bits(lith, &ad1843_LDA1GM) ? 0 : SOUND_MASK_PCM;
1226 line = ad1843_read_bits(lith, &ad1843_LX1MM) ? 0 : SOUND_MASK_LINE;
1227 cd = ad1843_read_bits(lith, &ad1843_LX2MM) ? 0 : SOUND_MASK_CD;
1228 mic = ad1843_read_bits(lith, &ad1843_LMCMM) ? 0 : SOUND_MASK_MIC;
1230 return pcm | line | cd | mic;
1234 * Set output sources. Arg is a mask of active sources in OSS format.
1236 * Returns source mask on success, -errno on failure.
1239 static int ad1843_set_outsrc(lithium_t *lith, int mask)
1241 int pcm, line, mic, cd;
1243 if (mask & ~(SOUND_MASK_PCM | SOUND_MASK_LINE |
1244 SOUND_MASK_CD | SOUND_MASK_MIC))
1245 return -EINVAL;
1246 pcm = (mask & SOUND_MASK_PCM) ? 0 : 1;
1247 line = (mask & SOUND_MASK_LINE) ? 0 : 1;
1248 mic = (mask & SOUND_MASK_MIC) ? 0 : 1;
1249 cd = (mask & SOUND_MASK_CD) ? 0 : 1;
1251 ad1843_write_multi(lith, 2, &ad1843_LDA1GM, pcm, &ad1843_RDA1GM, pcm);
1252 ad1843_write_multi(lith, 2, &ad1843_LX1MM, line, &ad1843_RX1MM, line);
1253 ad1843_write_multi(lith, 2, &ad1843_LX2MM, cd, &ad1843_RX2MM, cd);
1254 ad1843_write_multi(lith, 2, &ad1843_LMCMM, mic, &ad1843_RMCMM, mic);
1256 return mask;
1259 /* Setup ad1843 for D/A conversion. */
1261 static void ad1843_setup_dac(lithium_t *lith,
1262 int framerate,
1263 int fmt,
1264 int channels)
1266 int ad_fmt = 0, ad_mode = 0;
1268 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1269 lith, framerate, fmt, channels);
1271 switch (fmt) {
1272 case AFMT_S8: ad_fmt = 1; break;
1273 case AFMT_U8: ad_fmt = 1; break;
1274 case AFMT_S16_LE: ad_fmt = 1; break;
1275 case AFMT_MU_LAW: ad_fmt = 2; break;
1276 case AFMT_A_LAW: ad_fmt = 3; break;
1277 default: ASSERT(0);
1280 switch (channels) {
1281 case 2: ad_mode = 0; break;
1282 case 1: ad_mode = 1; break;
1283 default: ASSERT(0);
1286 DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode, ad_fmt);
1287 ASSERT(framerate >= 4000 && framerate <= 49000);
1288 ad1843_write_bits(lith, &ad1843_C1C, framerate);
1289 ad1843_write_multi(lith, 2,
1290 &ad1843_DA1SM, ad_mode, &ad1843_DA1F, ad_fmt);
1293 static void ad1843_shutdown_dac(lithium_t *lith)
1295 ad1843_write_bits(lith, &ad1843_DA1F, 1);
1298 static void ad1843_setup_adc(lithium_t *lith, int framerate, int fmt, int channels)
1300 int da_fmt = 0;
1302 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1303 lith, framerate, fmt, channels);
1305 switch (fmt) {
1306 case AFMT_S8: da_fmt = 1; break;
1307 case AFMT_U8: da_fmt = 1; break;
1308 case AFMT_S16_LE: da_fmt = 1; break;
1309 case AFMT_MU_LAW: da_fmt = 2; break;
1310 case AFMT_A_LAW: da_fmt = 3; break;
1311 default: ASSERT(0);
1314 DBGPV("da_fmt = %d\n", da_fmt);
1315 ASSERT(framerate >= 4000 && framerate <= 49000);
1316 ad1843_write_bits(lith, &ad1843_C2C, framerate);
1317 ad1843_write_multi(lith, 2,
1318 &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt);
1321 static void ad1843_shutdown_adc(lithium_t *lith)
1323 /* nothing to do */
1327 * Fully initialize the ad1843. As described in the AD1843 data
1328 * sheet, section "START-UP SEQUENCE". The numbered comments are
1329 * subsection headings from the data sheet. See the data sheet, pages
1330 * 52-54, for more info.
1332 * return 0 on success, -errno on failure. */
1334 static int __init ad1843_init(lithium_t *lith)
1336 unsigned long later;
1337 int err;
1339 err = li_init(lith);
1340 if (err)
1341 return err;
1343 if (ad1843_read_bits(lith, &ad1843_INIT) != 0) {
1344 printk(KERN_ERR "vwsnd sound: AD1843 won't initialize\n");
1345 return -EIO;
1348 ad1843_write_bits(lith, &ad1843_SCF, 1);
1350 /* 4. Put the conversion resources into standby. */
1352 ad1843_write_bits(lith, &ad1843_PDNI, 0);
1353 later = jiffies + HZ / 2; /* roughly half a second */
1354 DBGDO(shut_up++);
1355 while (ad1843_read_bits(lith, &ad1843_PDNO)) {
1356 if (time_after(jiffies, later)) {
1357 printk(KERN_ERR
1358 "vwsnd audio: AD1843 won't power up\n");
1359 return -EIO;
1361 schedule();
1363 DBGDO(shut_up--);
1365 /* 5. Power up the clock generators and enable clock output pins. */
1367 ad1843_write_multi(lith, 2, &ad1843_C1EN, 1, &ad1843_C2EN, 1);
1369 /* 6. Configure conversion resources while they are in standby. */
1371 /* DAC1 uses clock 1 as source, ADC uses clock 2. Always. */
1373 ad1843_write_multi(lith, 3,
1374 &ad1843_DA1C, 1,
1375 &ad1843_ADLC, 2,
1376 &ad1843_ADRC, 2);
1378 /* 7. Enable conversion resources. */
1380 ad1843_write_bits(lith, &ad1843_ADTLK, 1);
1381 ad1843_write_multi(lith, 5,
1382 &ad1843_ANAEN, 1,
1383 &ad1843_AAMEN, 1,
1384 &ad1843_DA1EN, 1,
1385 &ad1843_ADLEN, 1,
1386 &ad1843_ADREN, 1);
1388 /* 8. Configure conversion resources while they are enabled. */
1390 ad1843_write_bits(lith, &ad1843_DA1C, 1);
1392 /* Unmute all channels. */
1394 ad1843_set_outsrc(lith,
1395 (SOUND_MASK_PCM | SOUND_MASK_LINE |
1396 SOUND_MASK_MIC | SOUND_MASK_CD));
1397 ad1843_write_multi(lith, 2, &ad1843_LDA1AM, 0, &ad1843_RDA1AM, 0);
1399 /* Set default recording source to Line In and set
1400 * mic gain to +20 dB.
1403 ad1843_set_recsrc(lith, SOUND_MASK_LINE);
1404 ad1843_write_multi(lith, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1);
1406 /* Set Speaker Out level to +/- 4V and unmute it. */
1408 ad1843_write_multi(lith, 2, &ad1843_HPOS, 1, &ad1843_HPOM, 0);
1410 return 0;
1413 /*****************************************************************************/
1414 /* PCM I/O */
1416 #define READ_INTR_MASK (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1417 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1419 typedef enum vwsnd_port_swstate { /* software state */
1420 SW_OFF,
1421 SW_INITIAL,
1422 SW_RUN,
1423 SW_DRAIN,
1424 } vwsnd_port_swstate_t;
1426 typedef enum vwsnd_port_hwstate { /* hardware state */
1427 HW_STOPPED,
1428 HW_RUNNING,
1429 } vwsnd_port_hwstate_t;
1432 * These flags are read by ISR, but only written at baseline.
1435 typedef enum vwsnd_port_flags {
1436 DISABLED = 1 << 0,
1437 ERFLOWN = 1 << 1, /* overflown or underflown */
1438 HW_BUSY = 1 << 2,
1439 } vwsnd_port_flags_t;
1442 * vwsnd_port is the per-port data structure. Each device has two
1443 * ports, one for input and one for output.
1445 * Locking:
1447 * port->lock protects: hwstate, flags, swb_[iu]_avail.
1449 * devc->io_mutex protects: swstate, sw_*, swb_[iu]_idx.
1451 * everything else is only written by open/release or
1452 * pcm_{setup,shutdown}(), which are serialized by a
1453 * combination of devc->open_mutex and devc->io_mutex.
1456 typedef struct vwsnd_port {
1458 spinlock_t lock;
1459 wait_queue_head_t queue;
1460 vwsnd_port_swstate_t swstate;
1461 vwsnd_port_hwstate_t hwstate;
1462 vwsnd_port_flags_t flags;
1464 int sw_channels;
1465 int sw_samplefmt;
1466 int sw_framerate;
1467 int sample_size;
1468 int frame_size;
1469 unsigned int zero_word; /* zero for the sample format */
1471 int sw_fragshift;
1472 int sw_fragcount;
1473 int sw_subdivshift;
1475 unsigned int hw_fragshift;
1476 unsigned int hw_fragsize;
1477 unsigned int hw_fragcount;
1479 int hwbuf_size;
1480 unsigned long hwbuf_paddr;
1481 unsigned long hwbuf_vaddr;
1482 void * hwbuf; /* hwbuf == hwbuf_vaddr */
1483 int hwbuf_max; /* max bytes to preload */
1485 void * swbuf;
1486 unsigned int swbuf_size; /* size in bytes */
1487 unsigned int swb_u_idx; /* index of next user byte */
1488 unsigned int swb_i_idx; /* index of next intr byte */
1489 unsigned int swb_u_avail; /* # bytes avail to user */
1490 unsigned int swb_i_avail; /* # bytes avail to intr */
1492 dma_chan_t chan;
1494 /* Accounting */
1496 int byte_count;
1497 int frag_count;
1498 int MSC_offset;
1500 } vwsnd_port_t;
1502 /* vwsnd_dev is the per-device data structure. */
1504 typedef struct vwsnd_dev {
1505 struct vwsnd_dev *next_dev;
1506 int audio_minor; /* minor number of audio device */
1507 int mixer_minor; /* minor number of mixer device */
1509 struct mutex open_mutex;
1510 struct mutex io_mutex;
1511 struct mutex mix_mutex;
1512 mode_t open_mode;
1513 wait_queue_head_t open_wait;
1515 lithium_t lith;
1517 vwsnd_port_t rport;
1518 vwsnd_port_t wport;
1519 } vwsnd_dev_t;
1521 static vwsnd_dev_t *vwsnd_dev_list; /* linked list of all devices */
1523 static atomic_t vwsnd_use_count = ATOMIC_INIT(0);
1525 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1526 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1527 # define IN_USE (atomic_read(&vwsnd_use_count) != 0)
1530 * Lithium can only DMA multiples of 32 bytes. Its DMA buffer may
1531 * be up to 8 Kb. This driver always uses 8 Kb.
1533 * Memory bug workaround -- I'm not sure what's going on here, but
1534 * somehow pcm_copy_out() was triggering segv's going on to the next
1535 * page of the hw buffer. So, I make the hw buffer one size bigger
1536 * than we actually use. That way, the following page is allocated
1537 * and mapped, and no error. I suspect that something is broken
1538 * in Cobalt, but haven't really investigated. HBO is the actual
1539 * size of the buffer, and HWBUF_ORDER is what we allocate.
1542 #define HWBUF_SHIFT 13
1543 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1544 # define HBO (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1545 # define HWBUF_ORDER (HBO + 1) /* next size bigger */
1546 #define MIN_SPEED 4000
1547 #define MAX_SPEED 49000
1549 #define MIN_FRAGSHIFT (DMACHUNK_SHIFT + 1)
1550 #define MAX_FRAGSHIFT (PAGE_SHIFT)
1551 #define MIN_FRAGSIZE (1 << MIN_FRAGSHIFT)
1552 #define MAX_FRAGSIZE (1 << MAX_FRAGSHIFT)
1553 #define MIN_FRAGCOUNT(fragsize) 3
1554 #define MAX_FRAGCOUNT(fragsize) (32 * PAGE_SIZE / (fragsize))
1555 #define DEFAULT_FRAGSHIFT 12
1556 #define DEFAULT_FRAGCOUNT 16
1557 #define DEFAULT_SUBDIVSHIFT 0
1560 * The software buffer (swbuf) is a ring buffer shared between user
1561 * level and interrupt level. Each level owns some of the bytes in
1562 * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1563 * User level calls _u for user, and interrupt level calls _i for
1564 * interrupt.
1566 * port->swb_{u,i}_avail is the number of bytes available to that level.
1568 * port->swb_{u,i}_idx is the index of the first available byte in the
1569 * buffer.
1571 * Each level calls swb_inc_{u,i}() to atomically increment its index,
1572 * recalculate the number of bytes available for both sides, and
1573 * return the number of bytes available. Since each side can only
1574 * give away bytes, the other side can only increase the number of
1575 * bytes available to this side. Each side updates its own index
1576 * variable, swb_{u,i}_idx, so no lock is needed to read it.
1578 * To query the number of bytes available, call swb_inc_{u,i} with an
1579 * increment of zero.
1582 static __inline__ unsigned int __swb_inc_u(vwsnd_port_t *port, int inc)
1584 if (inc) {
1585 port->swb_u_idx += inc;
1586 port->swb_u_idx %= port->swbuf_size;
1587 port->swb_u_avail -= inc;
1588 port->swb_i_avail += inc;
1590 return port->swb_u_avail;
1593 static __inline__ unsigned int swb_inc_u(vwsnd_port_t *port, int inc)
1595 unsigned long flags;
1596 unsigned int ret;
1598 spin_lock_irqsave(&port->lock, flags);
1600 ret = __swb_inc_u(port, inc);
1602 spin_unlock_irqrestore(&port->lock, flags);
1603 return ret;
1606 static __inline__ unsigned int __swb_inc_i(vwsnd_port_t *port, int inc)
1608 if (inc) {
1609 port->swb_i_idx += inc;
1610 port->swb_i_idx %= port->swbuf_size;
1611 port->swb_i_avail -= inc;
1612 port->swb_u_avail += inc;
1614 return port->swb_i_avail;
1617 static __inline__ unsigned int swb_inc_i(vwsnd_port_t *port, int inc)
1619 unsigned long flags;
1620 unsigned int ret;
1622 spin_lock_irqsave(&port->lock, flags);
1624 ret = __swb_inc_i(port, inc);
1626 spin_unlock_irqrestore(&port->lock, flags);
1627 return ret;
1631 * pcm_setup - this routine initializes all port state after
1632 * mode-setting ioctls have been done, but before the first I/O is
1633 * done.
1635 * Locking: called with devc->io_mutex held.
1637 * Returns 0 on success, -errno on failure.
1640 static int pcm_setup(vwsnd_dev_t *devc,
1641 vwsnd_port_t *rport,
1642 vwsnd_port_t *wport)
1644 vwsnd_port_t *aport = rport ? rport : wport;
1645 int sample_size;
1646 unsigned int zero_word;
1648 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1650 ASSERT(aport != NULL);
1651 if (aport->swbuf != NULL)
1652 return 0;
1653 switch (aport->sw_samplefmt) {
1654 case AFMT_MU_LAW:
1655 sample_size = 1;
1656 zero_word = 0xFFFFFFFF ^ 0x80808080;
1657 break;
1659 case AFMT_A_LAW:
1660 sample_size = 1;
1661 zero_word = 0xD5D5D5D5 ^ 0x80808080;
1662 break;
1664 case AFMT_U8:
1665 sample_size = 1;
1666 zero_word = 0x80808080;
1667 break;
1669 case AFMT_S8:
1670 sample_size = 1;
1671 zero_word = 0x00000000;
1672 break;
1674 case AFMT_S16_LE:
1675 sample_size = 2;
1676 zero_word = 0x00000000;
1677 break;
1679 default:
1680 sample_size = 0; /* prevent compiler warning */
1681 zero_word = 0;
1682 ASSERT(0);
1684 aport->sample_size = sample_size;
1685 aport->zero_word = zero_word;
1686 aport->frame_size = aport->sw_channels * aport->sample_size;
1687 aport->hw_fragshift = aport->sw_fragshift - aport->sw_subdivshift;
1688 aport->hw_fragsize = 1 << aport->hw_fragshift;
1689 aport->hw_fragcount = aport->sw_fragcount << aport->sw_subdivshift;
1690 ASSERT(aport->hw_fragsize >= MIN_FRAGSIZE);
1691 ASSERT(aport->hw_fragsize <= MAX_FRAGSIZE);
1692 ASSERT(aport->hw_fragcount >= MIN_FRAGCOUNT(aport->hw_fragsize));
1693 ASSERT(aport->hw_fragcount <= MAX_FRAGCOUNT(aport->hw_fragsize));
1694 if (rport) {
1695 int hwfrags, swfrags;
1696 rport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1697 hwfrags = rport->hwbuf_max >> aport->hw_fragshift;
1698 swfrags = aport->hw_fragcount - hwfrags;
1699 if (swfrags < 2)
1700 swfrags = 2;
1701 rport->swbuf_size = swfrags * aport->hw_fragsize;
1702 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1703 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1704 rport->hwbuf_max, rport->swbuf_size);
1706 if (wport) {
1707 int hwfrags, swfrags;
1708 int total_bytes = aport->hw_fragcount * aport->hw_fragsize;
1709 wport->hwbuf_max = aport->hwbuf_size - DMACHUNK_SIZE;
1710 if (wport->hwbuf_max > total_bytes)
1711 wport->hwbuf_max = total_bytes;
1712 hwfrags = wport->hwbuf_max >> aport->hw_fragshift;
1713 DBGPV("hwfrags = %d\n", hwfrags);
1714 swfrags = aport->hw_fragcount - hwfrags;
1715 if (swfrags < 2)
1716 swfrags = 2;
1717 wport->swbuf_size = swfrags * aport->hw_fragsize;
1718 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags, swfrags);
1719 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1720 wport->hwbuf_max, wport->swbuf_size);
1723 aport->swb_u_idx = 0;
1724 aport->swb_i_idx = 0;
1725 aport->byte_count = 0;
1728 * Is this a Cobalt bug? We need to make this buffer extend
1729 * one page further than we actually use -- somehow memcpy
1730 * causes an exceptoin otherwise. I suspect there's a bug in
1731 * Cobalt (or somewhere) where it's generating a fault on a
1732 * speculative load or something. Obviously, I haven't taken
1733 * the time to track it down.
1736 aport->swbuf = vmalloc(aport->swbuf_size + PAGE_SIZE);
1737 if (!aport->swbuf)
1738 return -ENOMEM;
1739 if (rport && wport) {
1740 ASSERT(aport == rport);
1741 ASSERT(wport->swbuf == NULL);
1742 /* One extra page - see comment above. */
1743 wport->swbuf = vmalloc(aport->swbuf_size + PAGE_SIZE);
1744 if (!wport->swbuf) {
1745 vfree(aport->swbuf);
1746 aport->swbuf = NULL;
1747 return -ENOMEM;
1749 wport->sample_size = rport->sample_size;
1750 wport->zero_word = rport->zero_word;
1751 wport->frame_size = rport->frame_size;
1752 wport->hw_fragshift = rport->hw_fragshift;
1753 wport->hw_fragsize = rport->hw_fragsize;
1754 wport->hw_fragcount = rport->hw_fragcount;
1755 wport->swbuf_size = rport->swbuf_size;
1756 wport->hwbuf_max = rport->hwbuf_max;
1757 wport->swb_u_idx = rport->swb_u_idx;
1758 wport->swb_i_idx = rport->swb_i_idx;
1759 wport->byte_count = rport->byte_count;
1761 if (rport) {
1762 rport->swb_u_avail = 0;
1763 rport->swb_i_avail = rport->swbuf_size;
1764 rport->swstate = SW_RUN;
1765 li_setup_dma(&rport->chan,
1766 &li_comm1,
1767 &devc->lith,
1768 rport->hwbuf_paddr,
1769 HWBUF_SHIFT,
1770 rport->hw_fragshift,
1771 rport->sw_channels,
1772 rport->sample_size);
1773 ad1843_setup_adc(&devc->lith,
1774 rport->sw_framerate,
1775 rport->sw_samplefmt,
1776 rport->sw_channels);
1777 li_enable_interrupts(&devc->lith, READ_INTR_MASK);
1778 if (!(rport->flags & DISABLED)) {
1779 ustmsc_t ustmsc;
1780 rport->hwstate = HW_RUNNING;
1781 li_activate_dma(&rport->chan);
1782 li_read_USTMSC(&rport->chan, &ustmsc);
1783 rport->MSC_offset = ustmsc.msc;
1786 if (wport) {
1787 if (wport->hwbuf_max > wport->swbuf_size)
1788 wport->hwbuf_max = wport->swbuf_size;
1789 wport->flags &= ~ERFLOWN;
1790 wport->swb_u_avail = wport->swbuf_size;
1791 wport->swb_i_avail = 0;
1792 wport->swstate = SW_RUN;
1793 li_setup_dma(&wport->chan,
1794 &li_comm2,
1795 &devc->lith,
1796 wport->hwbuf_paddr,
1797 HWBUF_SHIFT,
1798 wport->hw_fragshift,
1799 wport->sw_channels,
1800 wport->sample_size);
1801 ad1843_setup_dac(&devc->lith,
1802 wport->sw_framerate,
1803 wport->sw_samplefmt,
1804 wport->sw_channels);
1805 li_enable_interrupts(&devc->lith, WRITE_INTR_MASK);
1807 DBGRV();
1808 return 0;
1812 * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1813 * Only called from pcm_shutdown.
1816 static void pcm_shutdown_port(vwsnd_dev_t *devc,
1817 vwsnd_port_t *aport,
1818 unsigned int mask)
1820 unsigned long flags;
1821 vwsnd_port_hwstate_t hwstate;
1822 DECLARE_WAITQUEUE(wait, current);
1824 aport->swstate = SW_INITIAL;
1825 add_wait_queue(&aport->queue, &wait);
1826 while (1) {
1827 set_current_state(TASK_UNINTERRUPTIBLE);
1828 spin_lock_irqsave(&aport->lock, flags);
1830 hwstate = aport->hwstate;
1832 spin_unlock_irqrestore(&aport->lock, flags);
1833 if (hwstate == HW_STOPPED)
1834 break;
1835 schedule();
1837 current->state = TASK_RUNNING;
1838 remove_wait_queue(&aport->queue, &wait);
1839 li_disable_interrupts(&devc->lith, mask);
1840 if (aport == &devc->rport)
1841 ad1843_shutdown_adc(&devc->lith);
1842 else /* aport == &devc->wport) */
1843 ad1843_shutdown_dac(&devc->lith);
1844 li_shutdown_dma(&aport->chan);
1845 vfree(aport->swbuf);
1846 aport->swbuf = NULL;
1847 aport->byte_count = 0;
1851 * pcm_shutdown undoes what pcm_setup did.
1852 * Also sets the ports' swstate to newstate.
1855 static void pcm_shutdown(vwsnd_dev_t *devc,
1856 vwsnd_port_t *rport,
1857 vwsnd_port_t *wport)
1859 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc, rport, wport);
1861 if (rport && rport->swbuf) {
1862 DBGPV("shutting down rport\n");
1863 pcm_shutdown_port(devc, rport, READ_INTR_MASK);
1865 if (wport && wport->swbuf) {
1866 DBGPV("shutting down wport\n");
1867 pcm_shutdown_port(devc, wport, WRITE_INTR_MASK);
1869 DBGRV();
1872 static void pcm_copy_in(vwsnd_port_t *rport, int swidx, int hwidx, int nb)
1874 char *src = rport->hwbuf + hwidx;
1875 char *dst = rport->swbuf + swidx;
1876 int fmt = rport->sw_samplefmt;
1878 DBGPV("swidx = %d, hwidx = %d\n", swidx, hwidx);
1879 ASSERT(rport->hwbuf != NULL);
1880 ASSERT(rport->swbuf != NULL);
1881 ASSERT(nb > 0 && (nb % 32) == 0);
1882 ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1883 ASSERT(swidx >= 0 && swidx + nb <= rport->swbuf_size);
1884 ASSERT(hwidx >= 0 && hwidx + nb <= rport->hwbuf_size);
1886 if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1888 /* See Sample Format Notes above. */
1890 char *end = src + nb;
1891 while (src < end)
1892 *dst++ = *src++ ^ 0x80;
1893 } else
1894 memcpy(dst, src, nb);
1897 static void pcm_copy_out(vwsnd_port_t *wport, int swidx, int hwidx, int nb)
1899 char *src = wport->swbuf + swidx;
1900 char *dst = wport->hwbuf + hwidx;
1901 int fmt = wport->sw_samplefmt;
1903 ASSERT(nb > 0 && (nb % 32) == 0);
1904 ASSERT(wport->hwbuf != NULL);
1905 ASSERT(wport->swbuf != NULL);
1906 ASSERT(swidx % 32 == 0 && hwidx % 32 == 0);
1907 ASSERT(swidx >= 0 && swidx + nb <= wport->swbuf_size);
1908 ASSERT(hwidx >= 0 && hwidx + nb <= wport->hwbuf_size);
1909 if (fmt == AFMT_MU_LAW || fmt == AFMT_A_LAW || fmt == AFMT_S8) {
1911 /* See Sample Format Notes above. */
1913 char *end = src + nb;
1914 while (src < end)
1915 *dst++ = *src++ ^ 0x80;
1916 } else
1917 memcpy(dst, src, nb);
1921 * pcm_output() is called both from baselevel and from interrupt level.
1922 * This is where audio frames are copied into the hardware-accessible
1923 * ring buffer.
1925 * Locking note: The part of this routine that figures out what to do
1926 * holds wport->lock. The longer part releases wport->lock, but sets
1927 * wport->flags & HW_BUSY. Afterward, it reacquires wport->lock, and
1928 * checks for more work to do.
1930 * If another thread calls pcm_output() while HW_BUSY is set, it
1931 * returns immediately, knowing that the thread that set HW_BUSY will
1932 * look for more work to do before returning.
1934 * This has the advantage that port->lock is held for several short
1935 * periods instead of one long period. Also, when pcm_output is
1936 * called from base level, it reenables interrupts.
1939 static void pcm_output(vwsnd_dev_t *devc, int erflown, int nb)
1941 vwsnd_port_t *wport = &devc->wport;
1942 const int hwmax = wport->hwbuf_max;
1943 const int hwsize = wport->hwbuf_size;
1944 const int swsize = wport->swbuf_size;
1945 const int fragsize = wport->hw_fragsize;
1946 unsigned long iflags;
1948 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
1949 spin_lock_irqsave(&wport->lock, iflags);
1950 if (erflown)
1951 wport->flags |= ERFLOWN;
1952 (void) __swb_inc_u(wport, nb);
1953 if (wport->flags & HW_BUSY) {
1954 spin_unlock_irqrestore(&wport->lock, iflags);
1955 DBGPV("returning: HW BUSY\n");
1956 return;
1958 if (wport->flags & DISABLED) {
1959 spin_unlock_irqrestore(&wport->lock, iflags);
1960 DBGPV("returning: DISABLED\n");
1961 return;
1963 wport->flags |= HW_BUSY;
1964 while (1) {
1965 int swptr, hwptr, hw_avail, sw_avail, swidx;
1966 vwsnd_port_hwstate_t hwstate = wport->hwstate;
1967 vwsnd_port_swstate_t swstate = wport->swstate;
1968 int hw_unavail;
1969 ustmsc_t ustmsc;
1971 hwptr = li_read_hwptr(&wport->chan);
1972 swptr = li_read_swptr(&wport->chan);
1973 hw_unavail = (swptr - hwptr + hwsize) % hwsize;
1974 hw_avail = (hwmax - hw_unavail) & -fragsize;
1975 sw_avail = wport->swb_i_avail & -fragsize;
1976 if (sw_avail && swstate == SW_RUN) {
1977 if (wport->flags & ERFLOWN) {
1978 wport->flags &= ~ERFLOWN;
1980 } else if (swstate == SW_INITIAL ||
1981 swstate == SW_OFF ||
1982 (swstate == SW_DRAIN &&
1983 !sw_avail &&
1984 (wport->flags & ERFLOWN))) {
1985 DBGP("stopping. hwstate = %d\n", hwstate);
1986 if (hwstate != HW_STOPPED) {
1987 li_deactivate_dma(&wport->chan);
1988 wport->hwstate = HW_STOPPED;
1990 wake_up(&wport->queue);
1991 break;
1993 if (!sw_avail || !hw_avail)
1994 break;
1995 spin_unlock_irqrestore(&wport->lock, iflags);
1998 * We gave up the port lock, but we have the HW_BUSY flag.
1999 * Proceed without accessing any nonlocal state.
2000 * Do not exit the loop -- must check for more work.
2003 swidx = wport->swb_i_idx;
2004 nb = hw_avail;
2005 if (nb > sw_avail)
2006 nb = sw_avail;
2007 if (nb > hwsize - swptr)
2008 nb = hwsize - swptr; /* don't overflow hwbuf */
2009 if (nb > swsize - swidx)
2010 nb = swsize - swidx; /* don't overflow swbuf */
2011 ASSERT(nb > 0);
2012 if (nb % fragsize) {
2013 DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2014 DBGP("hw_avail = %d\n", hw_avail);
2015 DBGP("sw_avail = %d\n", sw_avail);
2016 DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2017 DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2019 ASSERT(!(nb % fragsize));
2020 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2021 swidx, swidx + nb, swptr, swptr + nb);
2022 pcm_copy_out(wport, swidx, swptr, nb);
2023 li_write_swptr(&wport->chan, (swptr + nb) % hwsize);
2024 spin_lock_irqsave(&wport->lock, iflags);
2025 if (hwstate == HW_STOPPED) {
2026 DBGPV("starting\n");
2027 li_activate_dma(&wport->chan);
2028 wport->hwstate = HW_RUNNING;
2029 li_read_USTMSC(&wport->chan, &ustmsc);
2030 ASSERT(wport->byte_count % wport->frame_size == 0);
2031 wport->MSC_offset = ustmsc.msc - wport->byte_count / wport->frame_size;
2033 __swb_inc_i(wport, nb);
2034 wport->byte_count += nb;
2035 wport->frag_count += nb / fragsize;
2036 ASSERT(nb % fragsize == 0);
2037 wake_up(&wport->queue);
2039 wport->flags &= ~HW_BUSY;
2040 spin_unlock_irqrestore(&wport->lock, iflags);
2041 DBGRV();
2045 * pcm_input() is called both from baselevel and from interrupt level.
2046 * This is where audio frames are copied out of the hardware-accessible
2047 * ring buffer.
2049 * Locking note: The part of this routine that figures out what to do
2050 * holds rport->lock. The longer part releases rport->lock, but sets
2051 * rport->flags & HW_BUSY. Afterward, it reacquires rport->lock, and
2052 * checks for more work to do.
2054 * If another thread calls pcm_input() while HW_BUSY is set, it
2055 * returns immediately, knowing that the thread that set HW_BUSY will
2056 * look for more work to do before returning.
2058 * This has the advantage that port->lock is held for several short
2059 * periods instead of one long period. Also, when pcm_input is
2060 * called from base level, it reenables interrupts.
2063 static void pcm_input(vwsnd_dev_t *devc, int erflown, int nb)
2065 vwsnd_port_t *rport = &devc->rport;
2066 const int hwmax = rport->hwbuf_max;
2067 const int hwsize = rport->hwbuf_size;
2068 const int swsize = rport->swbuf_size;
2069 const int fragsize = rport->hw_fragsize;
2070 unsigned long iflags;
2072 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc, erflown, nb);
2074 spin_lock_irqsave(&rport->lock, iflags);
2075 if (erflown)
2076 rport->flags |= ERFLOWN;
2077 (void) __swb_inc_u(rport, nb);
2078 if (rport->flags & HW_BUSY || !rport->swbuf) {
2079 spin_unlock_irqrestore(&rport->lock, iflags);
2080 DBGPV("returning: HW BUSY or !swbuf\n");
2081 return;
2083 if (rport->flags & DISABLED) {
2084 spin_unlock_irqrestore(&rport->lock, iflags);
2085 DBGPV("returning: DISABLED\n");
2086 return;
2088 rport->flags |= HW_BUSY;
2089 while (1) {
2090 int swptr, hwptr, hw_avail, sw_avail, swidx;
2091 vwsnd_port_hwstate_t hwstate = rport->hwstate;
2092 vwsnd_port_swstate_t swstate = rport->swstate;
2094 hwptr = li_read_hwptr(&rport->chan);
2095 swptr = li_read_swptr(&rport->chan);
2096 hw_avail = (hwptr - swptr + hwsize) % hwsize & -fragsize;
2097 if (hw_avail > hwmax)
2098 hw_avail = hwmax;
2099 sw_avail = rport->swb_i_avail & -fragsize;
2100 if (swstate != SW_RUN) {
2101 DBGP("stopping. hwstate = %d\n", hwstate);
2102 if (hwstate != HW_STOPPED) {
2103 li_deactivate_dma(&rport->chan);
2104 rport->hwstate = HW_STOPPED;
2106 wake_up(&rport->queue);
2107 break;
2109 if (!sw_avail || !hw_avail)
2110 break;
2111 spin_unlock_irqrestore(&rport->lock, iflags);
2114 * We gave up the port lock, but we have the HW_BUSY flag.
2115 * Proceed without accessing any nonlocal state.
2116 * Do not exit the loop -- must check for more work.
2119 swidx = rport->swb_i_idx;
2120 nb = hw_avail;
2121 if (nb > sw_avail)
2122 nb = sw_avail;
2123 if (nb > hwsize - swptr)
2124 nb = hwsize - swptr; /* don't overflow hwbuf */
2125 if (nb > swsize - swidx)
2126 nb = swsize - swidx; /* don't overflow swbuf */
2127 ASSERT(nb > 0);
2128 if (nb % fragsize) {
2129 DBGP("nb = %d, fragsize = %d\n", nb, fragsize);
2130 DBGP("hw_avail = %d\n", hw_avail);
2131 DBGP("sw_avail = %d\n", sw_avail);
2132 DBGP("hwsize = %d, swptr = %d\n", hwsize, swptr);
2133 DBGP("swsize = %d, swidx = %d\n", swsize, swidx);
2135 ASSERT(!(nb % fragsize));
2136 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2137 swptr, swptr + nb, swidx, swidx + nb);
2138 pcm_copy_in(rport, swidx, swptr, nb);
2139 li_write_swptr(&rport->chan, (swptr + nb) % hwsize);
2140 spin_lock_irqsave(&rport->lock, iflags);
2141 __swb_inc_i(rport, nb);
2142 rport->byte_count += nb;
2143 rport->frag_count += nb / fragsize;
2144 ASSERT(nb % fragsize == 0);
2145 wake_up(&rport->queue);
2147 rport->flags &= ~HW_BUSY;
2148 spin_unlock_irqrestore(&rport->lock, iflags);
2149 DBGRV();
2153 * pcm_flush_frag() writes zero samples to fill the current fragment,
2154 * then flushes it to the hardware.
2156 * It is only meaningful to flush output, not input.
2159 static void pcm_flush_frag(vwsnd_dev_t *devc)
2161 vwsnd_port_t *wport = &devc->wport;
2163 DBGPV("swstate = %d\n", wport->swstate);
2164 if (wport->swstate == SW_RUN) {
2165 int idx = wport->swb_u_idx;
2166 int end = (idx + wport->hw_fragsize - 1)
2167 >> wport->hw_fragshift
2168 << wport->hw_fragshift;
2169 int nb = end - idx;
2170 DBGPV("clearing %d bytes\n", nb);
2171 if (nb)
2172 memset(wport->swbuf + idx,
2173 (char) wport->zero_word,
2174 nb);
2175 wport->swstate = SW_DRAIN;
2176 pcm_output(devc, 0, nb);
2178 DBGRV();
2182 * Wait for output to drain. This sleeps uninterruptibly because
2183 * there is nothing intelligent we can do if interrupted. This
2184 * means the process will be delayed in responding to the signal.
2187 static void pcm_write_sync(vwsnd_dev_t *devc)
2189 vwsnd_port_t *wport = &devc->wport;
2190 DECLARE_WAITQUEUE(wait, current);
2191 unsigned long flags;
2192 vwsnd_port_hwstate_t hwstate;
2194 DBGEV("(devc=0x%p)\n", devc);
2195 add_wait_queue(&wport->queue, &wait);
2196 while (1) {
2197 set_current_state(TASK_UNINTERRUPTIBLE);
2198 spin_lock_irqsave(&wport->lock, flags);
2200 hwstate = wport->hwstate;
2202 spin_unlock_irqrestore(&wport->lock, flags);
2203 if (hwstate == HW_STOPPED)
2204 break;
2205 schedule();
2207 current->state = TASK_RUNNING;
2208 remove_wait_queue(&wport->queue, &wait);
2209 DBGPV("swstate = %d, hwstate = %d\n", wport->swstate, wport->hwstate);
2210 DBGRV();
2213 /*****************************************************************************/
2214 /* audio driver */
2217 * seek on an audio device always fails.
2220 static void vwsnd_audio_read_intr(vwsnd_dev_t *devc, unsigned int status)
2222 int overflown = status & LI_INTR_COMM1_OVERFLOW;
2224 if (status & READ_INTR_MASK)
2225 pcm_input(devc, overflown, 0);
2228 static void vwsnd_audio_write_intr(vwsnd_dev_t *devc, unsigned int status)
2230 int underflown = status & LI_INTR_COMM2_UNDERFLOW;
2232 if (status & WRITE_INTR_MASK)
2233 pcm_output(devc, underflown, 0);
2236 static irqreturn_t vwsnd_audio_intr(int irq, void *dev_id)
2238 vwsnd_dev_t *devc = dev_id;
2239 unsigned int status;
2241 DBGEV("(irq=%d, dev_id=0x%p)\n", irq, dev_id);
2243 status = li_get_clear_intr_status(&devc->lith);
2244 vwsnd_audio_read_intr(devc, status);
2245 vwsnd_audio_write_intr(devc, status);
2246 return IRQ_HANDLED;
2249 static ssize_t vwsnd_audio_do_read(struct file *file,
2250 char *buffer,
2251 size_t count,
2252 loff_t *ppos)
2254 vwsnd_dev_t *devc = file->private_data;
2255 vwsnd_port_t *rport = ((file->f_mode & FMODE_READ) ?
2256 &devc->rport : NULL);
2257 int ret, nb;
2259 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2260 file, buffer, count, ppos);
2262 if (!rport)
2263 return -EINVAL;
2265 if (rport->swbuf == NULL) {
2266 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2267 &devc->wport : NULL;
2268 ret = pcm_setup(devc, rport, wport);
2269 if (ret < 0)
2270 return ret;
2273 if (!access_ok(VERIFY_READ, buffer, count))
2274 return -EFAULT;
2275 ret = 0;
2276 while (count) {
2277 DECLARE_WAITQUEUE(wait, current);
2278 add_wait_queue(&rport->queue, &wait);
2279 while ((nb = swb_inc_u(rport, 0)) == 0) {
2280 DBGPV("blocking\n");
2281 set_current_state(TASK_INTERRUPTIBLE);
2282 if (rport->flags & DISABLED ||
2283 file->f_flags & O_NONBLOCK) {
2284 current->state = TASK_RUNNING;
2285 remove_wait_queue(&rport->queue, &wait);
2286 return ret ? ret : -EAGAIN;
2288 schedule();
2289 if (signal_pending(current)) {
2290 current->state = TASK_RUNNING;
2291 remove_wait_queue(&rport->queue, &wait);
2292 return ret ? ret : -ERESTARTSYS;
2295 current->state = TASK_RUNNING;
2296 remove_wait_queue(&rport->queue, &wait);
2297 pcm_input(devc, 0, 0);
2298 /* nb bytes are available in userbuf. */
2299 if (nb > count)
2300 nb = count;
2301 DBGPV("nb = %d\n", nb);
2302 if (copy_to_user(buffer, rport->swbuf + rport->swb_u_idx, nb))
2303 return -EFAULT;
2304 (void) swb_inc_u(rport, nb);
2305 buffer += nb;
2306 count -= nb;
2307 ret += nb;
2309 DBGPV("returning %d\n", ret);
2310 return ret;
2313 static ssize_t vwsnd_audio_read(struct file *file,
2314 char *buffer,
2315 size_t count,
2316 loff_t *ppos)
2318 vwsnd_dev_t *devc = file->private_data;
2319 ssize_t ret;
2321 mutex_lock(&devc->io_mutex);
2322 ret = vwsnd_audio_do_read(file, buffer, count, ppos);
2323 mutex_unlock(&devc->io_mutex);
2324 return ret;
2327 static ssize_t vwsnd_audio_do_write(struct file *file,
2328 const char *buffer,
2329 size_t count,
2330 loff_t *ppos)
2332 vwsnd_dev_t *devc = file->private_data;
2333 vwsnd_port_t *wport = ((file->f_mode & FMODE_WRITE) ?
2334 &devc->wport : NULL);
2335 int ret, nb;
2337 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2338 file, buffer, count, ppos);
2340 if (!wport)
2341 return -EINVAL;
2343 if (wport->swbuf == NULL) {
2344 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2345 &devc->rport : NULL;
2346 ret = pcm_setup(devc, rport, wport);
2347 if (ret < 0)
2348 return ret;
2350 if (!access_ok(VERIFY_WRITE, buffer, count))
2351 return -EFAULT;
2352 ret = 0;
2353 while (count) {
2354 DECLARE_WAITQUEUE(wait, current);
2355 add_wait_queue(&wport->queue, &wait);
2356 while ((nb = swb_inc_u(wport, 0)) == 0) {
2357 set_current_state(TASK_INTERRUPTIBLE);
2358 if (wport->flags & DISABLED ||
2359 file->f_flags & O_NONBLOCK) {
2360 current->state = TASK_RUNNING;
2361 remove_wait_queue(&wport->queue, &wait);
2362 return ret ? ret : -EAGAIN;
2364 schedule();
2365 if (signal_pending(current)) {
2366 current->state = TASK_RUNNING;
2367 remove_wait_queue(&wport->queue, &wait);
2368 return ret ? ret : -ERESTARTSYS;
2371 current->state = TASK_RUNNING;
2372 remove_wait_queue(&wport->queue, &wait);
2373 /* nb bytes are available in userbuf. */
2374 if (nb > count)
2375 nb = count;
2376 DBGPV("nb = %d\n", nb);
2377 if (copy_from_user(wport->swbuf + wport->swb_u_idx, buffer, nb))
2378 return -EFAULT;
2379 pcm_output(devc, 0, nb);
2380 buffer += nb;
2381 count -= nb;
2382 ret += nb;
2384 DBGPV("returning %d\n", ret);
2385 return ret;
2388 static ssize_t vwsnd_audio_write(struct file *file,
2389 const char *buffer,
2390 size_t count,
2391 loff_t *ppos)
2393 vwsnd_dev_t *devc = file->private_data;
2394 ssize_t ret;
2396 mutex_lock(&devc->io_mutex);
2397 ret = vwsnd_audio_do_write(file, buffer, count, ppos);
2398 mutex_unlock(&devc->io_mutex);
2399 return ret;
2402 /* No kernel lock - fine */
2403 static unsigned int vwsnd_audio_poll(struct file *file,
2404 struct poll_table_struct *wait)
2406 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2407 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2408 &devc->rport : NULL;
2409 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2410 &devc->wport : NULL;
2411 unsigned int mask = 0;
2413 DBGEV("(file=0x%p, wait=0x%p)\n", file, wait);
2415 ASSERT(rport || wport);
2416 if (rport) {
2417 poll_wait(file, &rport->queue, wait);
2418 if (swb_inc_u(rport, 0))
2419 mask |= (POLLIN | POLLRDNORM);
2421 if (wport) {
2422 poll_wait(file, &wport->queue, wait);
2423 if (wport->swbuf == NULL || swb_inc_u(wport, 0))
2424 mask |= (POLLOUT | POLLWRNORM);
2427 DBGPV("returning 0x%x\n", mask);
2428 return mask;
2431 static int vwsnd_audio_do_ioctl(struct inode *inode,
2432 struct file *file,
2433 unsigned int cmd,
2434 unsigned long arg)
2436 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2437 vwsnd_port_t *rport = (file->f_mode & FMODE_READ) ?
2438 &devc->rport : NULL;
2439 vwsnd_port_t *wport = (file->f_mode & FMODE_WRITE) ?
2440 &devc->wport : NULL;
2441 vwsnd_port_t *aport = rport ? rport : wport;
2442 struct audio_buf_info buf_info;
2443 struct count_info info;
2444 unsigned long flags;
2445 int ival;
2448 DBGEV("(inode=0x%p, file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2449 inode, file, cmd, arg);
2450 switch (cmd) {
2451 case OSS_GETVERSION: /* _SIOR ('M', 118, int) */
2452 DBGX("OSS_GETVERSION\n");
2453 ival = SOUND_VERSION;
2454 return put_user(ival, (int *) arg);
2456 case SNDCTL_DSP_GETCAPS: /* _SIOR ('P',15, int) */
2457 DBGX("SNDCTL_DSP_GETCAPS\n");
2458 ival = DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER;
2459 return put_user(ival, (int *) arg);
2461 case SNDCTL_DSP_GETFMTS: /* _SIOR ('P',11, int) */
2462 DBGX("SNDCTL_DSP_GETFMTS\n");
2463 ival = (AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW |
2464 AFMT_U8 | AFMT_S8);
2465 return put_user(ival, (int *) arg);
2466 break;
2468 case SOUND_PCM_READ_RATE: /* _SIOR ('P', 2, int) */
2469 DBGX("SOUND_PCM_READ_RATE\n");
2470 ival = aport->sw_framerate;
2471 return put_user(ival, (int *) arg);
2473 case SOUND_PCM_READ_CHANNELS: /* _SIOR ('P', 6, int) */
2474 DBGX("SOUND_PCM_READ_CHANNELS\n");
2475 ival = aport->sw_channels;
2476 return put_user(ival, (int *) arg);
2478 case SNDCTL_DSP_SPEED: /* _SIOWR('P', 2, int) */
2479 if (get_user(ival, (int *) arg))
2480 return -EFAULT;
2481 DBGX("SNDCTL_DSP_SPEED %d\n", ival);
2482 if (ival) {
2483 if (aport->swstate != SW_INITIAL) {
2484 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2485 aport->swstate);
2486 return -EINVAL;
2488 if (ival < MIN_SPEED)
2489 ival = MIN_SPEED;
2490 if (ival > MAX_SPEED)
2491 ival = MAX_SPEED;
2492 if (rport)
2493 rport->sw_framerate = ival;
2494 if (wport)
2495 wport->sw_framerate = ival;
2496 } else
2497 ival = aport->sw_framerate;
2498 return put_user(ival, (int *) arg);
2500 case SNDCTL_DSP_STEREO: /* _SIOWR('P', 3, int) */
2501 if (get_user(ival, (int *) arg))
2502 return -EFAULT;
2503 DBGX("SNDCTL_DSP_STEREO %d\n", ival);
2504 if (ival != 0 && ival != 1)
2505 return -EINVAL;
2506 if (aport->swstate != SW_INITIAL)
2507 return -EINVAL;
2508 if (rport)
2509 rport->sw_channels = ival + 1;
2510 if (wport)
2511 wport->sw_channels = ival + 1;
2512 return put_user(ival, (int *) arg);
2514 case SNDCTL_DSP_CHANNELS: /* _SIOWR('P', 6, int) */
2515 if (get_user(ival, (int *) arg))
2516 return -EFAULT;
2517 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival);
2518 if (ival != 1 && ival != 2)
2519 return -EINVAL;
2520 if (aport->swstate != SW_INITIAL)
2521 return -EINVAL;
2522 if (rport)
2523 rport->sw_channels = ival;
2524 if (wport)
2525 wport->sw_channels = ival;
2526 return put_user(ival, (int *) arg);
2528 case SNDCTL_DSP_GETBLKSIZE: /* _SIOWR('P', 4, int) */
2529 ival = pcm_setup(devc, rport, wport);
2530 if (ival < 0) {
2531 DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival);
2532 return ival;
2534 ival = 1 << aport->sw_fragshift;
2535 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival);
2536 return put_user(ival, (int *) arg);
2538 case SNDCTL_DSP_SETFRAGMENT: /* _SIOWR('P',10, int) */
2539 if (get_user(ival, (int *) arg))
2540 return -EFAULT;
2541 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2542 ival >> 16, ival & 0xFFFF);
2543 if (aport->swstate != SW_INITIAL)
2544 return -EINVAL;
2546 int sw_fragshift = ival & 0xFFFF;
2547 int sw_subdivshift = aport->sw_subdivshift;
2548 int hw_fragshift = sw_fragshift - sw_subdivshift;
2549 int sw_fragcount = (ival >> 16) & 0xFFFF;
2550 int hw_fragsize;
2551 if (hw_fragshift < MIN_FRAGSHIFT)
2552 hw_fragshift = MIN_FRAGSHIFT;
2553 if (hw_fragshift > MAX_FRAGSHIFT)
2554 hw_fragshift = MAX_FRAGSHIFT;
2555 sw_fragshift = hw_fragshift + aport->sw_subdivshift;
2556 hw_fragsize = 1 << hw_fragshift;
2557 if (sw_fragcount < MIN_FRAGCOUNT(hw_fragsize))
2558 sw_fragcount = MIN_FRAGCOUNT(hw_fragsize);
2559 if (sw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2560 sw_fragcount = MAX_FRAGCOUNT(hw_fragsize);
2561 DBGPV("sw_fragshift = %d\n", sw_fragshift);
2562 DBGPV("rport = 0x%p, wport = 0x%p\n", rport, wport);
2563 if (rport) {
2564 rport->sw_fragshift = sw_fragshift;
2565 rport->sw_fragcount = sw_fragcount;
2567 if (wport) {
2568 wport->sw_fragshift = sw_fragshift;
2569 wport->sw_fragcount = sw_fragcount;
2571 ival = sw_fragcount << 16 | sw_fragshift;
2573 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2574 ival >> 16, ival & 0xFFFF);
2575 return put_user(ival, (int *) arg);
2577 case SNDCTL_DSP_SUBDIVIDE: /* _SIOWR('P', 9, int) */
2578 if (get_user(ival, (int *) arg))
2579 return -EFAULT;
2580 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival);
2581 if (aport->swstate != SW_INITIAL)
2582 return -EINVAL;
2584 int subdivshift;
2585 int hw_fragshift, hw_fragsize, hw_fragcount;
2586 switch (ival) {
2587 case 1: subdivshift = 0; break;
2588 case 2: subdivshift = 1; break;
2589 case 4: subdivshift = 2; break;
2590 default: return -EINVAL;
2592 hw_fragshift = aport->sw_fragshift - subdivshift;
2593 if (hw_fragshift < MIN_FRAGSHIFT ||
2594 hw_fragshift > MAX_FRAGSHIFT)
2595 return -EINVAL;
2596 hw_fragsize = 1 << hw_fragshift;
2597 hw_fragcount = aport->sw_fragcount >> subdivshift;
2598 if (hw_fragcount < MIN_FRAGCOUNT(hw_fragsize) ||
2599 hw_fragcount > MAX_FRAGCOUNT(hw_fragsize))
2600 return -EINVAL;
2601 if (rport)
2602 rport->sw_subdivshift = subdivshift;
2603 if (wport)
2604 wport->sw_subdivshift = subdivshift;
2606 return 0;
2608 case SNDCTL_DSP_SETFMT: /* _SIOWR('P',5, int) */
2609 if (get_user(ival, (int *) arg))
2610 return -EFAULT;
2611 DBGX("SNDCTL_DSP_SETFMT %d\n", ival);
2612 if (ival != AFMT_QUERY) {
2613 if (aport->swstate != SW_INITIAL) {
2614 DBGP("SETFMT failed, swstate = %d\n",
2615 aport->swstate);
2616 return -EINVAL;
2618 switch (ival) {
2619 case AFMT_MU_LAW:
2620 case AFMT_A_LAW:
2621 case AFMT_U8:
2622 case AFMT_S8:
2623 case AFMT_S16_LE:
2624 if (rport)
2625 rport->sw_samplefmt = ival;
2626 if (wport)
2627 wport->sw_samplefmt = ival;
2628 break;
2629 default:
2630 return -EINVAL;
2633 ival = aport->sw_samplefmt;
2634 return put_user(ival, (int *) arg);
2636 case SNDCTL_DSP_GETOSPACE: /* _SIOR ('P',12, audio_buf_info) */
2637 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2638 if (!wport)
2639 return -EINVAL;
2640 ival = pcm_setup(devc, rport, wport);
2641 if (ival < 0)
2642 return ival;
2643 ival = swb_inc_u(wport, 0);
2644 buf_info.fragments = ival >> wport->sw_fragshift;
2645 buf_info.fragstotal = wport->sw_fragcount;
2646 buf_info.fragsize = 1 << wport->sw_fragshift;
2647 buf_info.bytes = ival;
2648 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2649 buf_info.fragments, buf_info.fragstotal,
2650 buf_info.fragsize, buf_info.bytes);
2651 if (copy_to_user((void *) arg, &buf_info, sizeof buf_info))
2652 return -EFAULT;
2653 return 0;
2655 case SNDCTL_DSP_GETISPACE: /* _SIOR ('P',13, audio_buf_info) */
2656 DBGX("SNDCTL_DSP_GETISPACE\n");
2657 if (!rport)
2658 return -EINVAL;
2659 ival = pcm_setup(devc, rport, wport);
2660 if (ival < 0)
2661 return ival;
2662 ival = swb_inc_u(rport, 0);
2663 buf_info.fragments = ival >> rport->sw_fragshift;
2664 buf_info.fragstotal = rport->sw_fragcount;
2665 buf_info.fragsize = 1 << rport->sw_fragshift;
2666 buf_info.bytes = ival;
2667 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2668 buf_info.fragments, buf_info.fragstotal,
2669 buf_info.fragsize, buf_info.bytes);
2670 if (copy_to_user((void *) arg, &buf_info, sizeof buf_info))
2671 return -EFAULT;
2672 return 0;
2674 case SNDCTL_DSP_NONBLOCK: /* _SIO ('P',14) */
2675 DBGX("SNDCTL_DSP_NONBLOCK\n");
2676 file->f_flags |= O_NONBLOCK;
2677 return 0;
2679 case SNDCTL_DSP_RESET: /* _SIO ('P', 0) */
2680 DBGX("SNDCTL_DSP_RESET\n");
2682 * Nothing special needs to be done for input. Input
2683 * samples sit in swbuf, but it will be reinitialized
2684 * to empty when pcm_setup() is called.
2686 if (wport && wport->swbuf) {
2687 wport->swstate = SW_INITIAL;
2688 pcm_output(devc, 0, 0);
2689 pcm_write_sync(devc);
2691 pcm_shutdown(devc, rport, wport);
2692 return 0;
2694 case SNDCTL_DSP_SYNC: /* _SIO ('P', 1) */
2695 DBGX("SNDCTL_DSP_SYNC\n");
2696 if (wport) {
2697 pcm_flush_frag(devc);
2698 pcm_write_sync(devc);
2700 pcm_shutdown(devc, rport, wport);
2701 return 0;
2703 case SNDCTL_DSP_POST: /* _SIO ('P', 8) */
2704 DBGX("SNDCTL_DSP_POST\n");
2705 if (!wport)
2706 return -EINVAL;
2707 pcm_flush_frag(devc);
2708 return 0;
2710 case SNDCTL_DSP_GETIPTR: /* _SIOR ('P', 17, count_info) */
2711 DBGX("SNDCTL_DSP_GETIPTR\n");
2712 if (!rport)
2713 return -EINVAL;
2714 spin_lock_irqsave(&rport->lock, flags);
2716 ustmsc_t ustmsc;
2717 if (rport->hwstate == HW_RUNNING) {
2718 ASSERT(rport->swstate == SW_RUN);
2719 li_read_USTMSC(&rport->chan, &ustmsc);
2720 info.bytes = ustmsc.msc - rport->MSC_offset;
2721 info.bytes *= rport->frame_size;
2722 } else {
2723 info.bytes = rport->byte_count;
2725 info.blocks = rport->frag_count;
2726 info.ptr = 0; /* not implemented */
2727 rport->frag_count = 0;
2729 spin_unlock_irqrestore(&rport->lock, flags);
2730 if (copy_to_user((void *) arg, &info, sizeof info))
2731 return -EFAULT;
2732 return 0;
2734 case SNDCTL_DSP_GETOPTR: /* _SIOR ('P',18, count_info) */
2735 DBGX("SNDCTL_DSP_GETOPTR\n");
2736 if (!wport)
2737 return -EINVAL;
2738 spin_lock_irqsave(&wport->lock, flags);
2740 ustmsc_t ustmsc;
2741 if (wport->hwstate == HW_RUNNING) {
2742 ASSERT(wport->swstate == SW_RUN);
2743 li_read_USTMSC(&wport->chan, &ustmsc);
2744 info.bytes = ustmsc.msc - wport->MSC_offset;
2745 info.bytes *= wport->frame_size;
2746 } else {
2747 info.bytes = wport->byte_count;
2749 info.blocks = wport->frag_count;
2750 info.ptr = 0; /* not implemented */
2751 wport->frag_count = 0;
2753 spin_unlock_irqrestore(&wport->lock, flags);
2754 if (copy_to_user((void *) arg, &info, sizeof info))
2755 return -EFAULT;
2756 return 0;
2758 case SNDCTL_DSP_GETODELAY: /* _SIOR ('P', 23, int) */
2759 DBGX("SNDCTL_DSP_GETODELAY\n");
2760 if (!wport)
2761 return -EINVAL;
2762 spin_lock_irqsave(&wport->lock, flags);
2764 int fsize = wport->frame_size;
2765 ival = wport->swb_i_avail / fsize;
2766 if (wport->hwstate == HW_RUNNING) {
2767 int swptr, hwptr, hwframes, hwbytes, hwsize;
2768 int totalhwbytes;
2769 ustmsc_t ustmsc;
2771 hwsize = wport->hwbuf_size;
2772 swptr = li_read_swptr(&wport->chan);
2773 li_read_USTMSC(&wport->chan, &ustmsc);
2774 hwframes = ustmsc.msc - wport->MSC_offset;
2775 totalhwbytes = hwframes * fsize;
2776 hwptr = totalhwbytes % hwsize;
2777 hwbytes = (swptr - hwptr + hwsize) % hwsize;
2778 ival += hwbytes / fsize;
2781 spin_unlock_irqrestore(&wport->lock, flags);
2782 return put_user(ival, (int *) arg);
2784 case SNDCTL_DSP_PROFILE: /* _SIOW ('P', 23, int) */
2785 DBGX("SNDCTL_DSP_PROFILE\n");
2788 * Thomas Sailer explains SNDCTL_DSP_PROFILE
2789 * (private email, March 24, 1999):
2791 * This gives the sound driver a hint on what it
2792 * should do with partial fragments
2793 * (i.e. fragments partially filled with write).
2794 * This can direct the driver to zero them or
2795 * leave them alone. But don't ask me what this
2796 * is good for, my driver just zeroes the last
2797 * fragment before the receiver stops, no idea
2798 * what good for any other behaviour could
2799 * be. Implementing it as NOP seems safe.
2802 break;
2804 case SNDCTL_DSP_GETTRIGGER: /* _SIOR ('P',16, int) */
2805 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2806 ival = 0;
2807 if (rport) {
2808 spin_lock_irqsave(&rport->lock, flags);
2810 if (!(rport->flags & DISABLED))
2811 ival |= PCM_ENABLE_INPUT;
2813 spin_unlock_irqrestore(&rport->lock, flags);
2815 if (wport) {
2816 spin_lock_irqsave(&wport->lock, flags);
2818 if (!(wport->flags & DISABLED))
2819 ival |= PCM_ENABLE_OUTPUT;
2821 spin_unlock_irqrestore(&wport->lock, flags);
2823 return put_user(ival, (int *) arg);
2825 case SNDCTL_DSP_SETTRIGGER: /* _SIOW ('P',16, int) */
2826 if (get_user(ival, (int *) arg))
2827 return -EFAULT;
2828 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival);
2831 * If user is disabling I/O and port is not in initial
2832 * state, fail with EINVAL.
2835 if (((rport && !(ival & PCM_ENABLE_INPUT)) ||
2836 (wport && !(ival & PCM_ENABLE_OUTPUT))) &&
2837 aport->swstate != SW_INITIAL)
2838 return -EINVAL;
2840 if (rport) {
2841 vwsnd_port_hwstate_t hwstate;
2842 spin_lock_irqsave(&rport->lock, flags);
2844 hwstate = rport->hwstate;
2845 if (ival & PCM_ENABLE_INPUT)
2846 rport->flags &= ~DISABLED;
2847 else
2848 rport->flags |= DISABLED;
2850 spin_unlock_irqrestore(&rport->lock, flags);
2851 if (hwstate != HW_RUNNING && ival & PCM_ENABLE_INPUT) {
2853 if (rport->swstate == SW_INITIAL)
2854 pcm_setup(devc, rport, wport);
2855 else
2856 li_activate_dma(&rport->chan);
2859 if (wport) {
2860 vwsnd_port_flags_t pflags;
2861 spin_lock_irqsave(&wport->lock, flags);
2863 pflags = wport->flags;
2864 if (ival & PCM_ENABLE_OUTPUT)
2865 wport->flags &= ~DISABLED;
2866 else
2867 wport->flags |= DISABLED;
2869 spin_unlock_irqrestore(&wport->lock, flags);
2870 if (pflags & DISABLED && ival & PCM_ENABLE_OUTPUT) {
2871 if (wport->swstate == SW_RUN)
2872 pcm_output(devc, 0, 0);
2875 return 0;
2877 default:
2878 DBGP("unknown ioctl 0x%x\n", cmd);
2879 return -EINVAL;
2881 DBGP("unimplemented ioctl 0x%x\n", cmd);
2882 return -EINVAL;
2885 static int vwsnd_audio_ioctl(struct inode *inode,
2886 struct file *file,
2887 unsigned int cmd,
2888 unsigned long arg)
2890 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
2891 int ret;
2893 mutex_lock(&devc->io_mutex);
2894 ret = vwsnd_audio_do_ioctl(inode, file, cmd, arg);
2895 mutex_unlock(&devc->io_mutex);
2896 return ret;
2899 /* No mmap. */
2901 static int vwsnd_audio_mmap(struct file *file, struct vm_area_struct *vma)
2903 DBGE("(file=0x%p, vma=0x%p)\n", file, vma);
2904 return -ENODEV;
2908 * Open the audio device for read and/or write.
2910 * Returns 0 on success, -errno on failure.
2913 static int vwsnd_audio_open(struct inode *inode, struct file *file)
2915 vwsnd_dev_t *devc;
2916 int minor = iminor(inode);
2917 int sw_samplefmt;
2919 DBGE("(inode=0x%p, file=0x%p)\n", inode, file);
2921 INC_USE_COUNT;
2922 for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
2923 if ((devc->audio_minor & ~0x0F) == (minor & ~0x0F))
2924 break;
2926 if (devc == NULL) {
2927 DEC_USE_COUNT;
2928 return -ENODEV;
2931 mutex_lock(&devc->open_mutex);
2932 while (devc->open_mode & file->f_mode) {
2933 mutex_unlock(&devc->open_mutex);
2934 if (file->f_flags & O_NONBLOCK) {
2935 DEC_USE_COUNT;
2936 return -EBUSY;
2938 interruptible_sleep_on(&devc->open_wait);
2939 if (signal_pending(current)) {
2940 DEC_USE_COUNT;
2941 return -ERESTARTSYS;
2943 mutex_lock(&devc->open_mutex);
2945 devc->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2946 mutex_unlock(&devc->open_mutex);
2948 /* get default sample format from minor number. */
2950 sw_samplefmt = 0;
2951 if ((minor & 0xF) == SND_DEV_DSP)
2952 sw_samplefmt = AFMT_U8;
2953 else if ((minor & 0xF) == SND_DEV_AUDIO)
2954 sw_samplefmt = AFMT_MU_LAW;
2955 else if ((minor & 0xF) == SND_DEV_DSP16)
2956 sw_samplefmt = AFMT_S16_LE;
2957 else
2958 ASSERT(0);
2960 /* Initialize vwsnd_ports. */
2962 mutex_lock(&devc->io_mutex);
2964 if (file->f_mode & FMODE_READ) {
2965 devc->rport.swstate = SW_INITIAL;
2966 devc->rport.flags = 0;
2967 devc->rport.sw_channels = 1;
2968 devc->rport.sw_samplefmt = sw_samplefmt;
2969 devc->rport.sw_framerate = 8000;
2970 devc->rport.sw_fragshift = DEFAULT_FRAGSHIFT;
2971 devc->rport.sw_fragcount = DEFAULT_FRAGCOUNT;
2972 devc->rport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2973 devc->rport.byte_count = 0;
2974 devc->rport.frag_count = 0;
2976 if (file->f_mode & FMODE_WRITE) {
2977 devc->wport.swstate = SW_INITIAL;
2978 devc->wport.flags = 0;
2979 devc->wport.sw_channels = 1;
2980 devc->wport.sw_samplefmt = sw_samplefmt;
2981 devc->wport.sw_framerate = 8000;
2982 devc->wport.sw_fragshift = DEFAULT_FRAGSHIFT;
2983 devc->wport.sw_fragcount = DEFAULT_FRAGCOUNT;
2984 devc->wport.sw_subdivshift = DEFAULT_SUBDIVSHIFT;
2985 devc->wport.byte_count = 0;
2986 devc->wport.frag_count = 0;
2989 mutex_unlock(&devc->io_mutex);
2991 file->private_data = devc;
2992 DBGRV();
2993 return 0;
2997 * Release (close) the audio device.
3000 static int vwsnd_audio_release(struct inode *inode, struct file *file)
3002 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
3003 vwsnd_port_t *wport = NULL, *rport = NULL;
3004 int err = 0;
3006 lock_kernel();
3007 mutex_lock(&devc->io_mutex);
3009 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3011 if (file->f_mode & FMODE_READ)
3012 rport = &devc->rport;
3013 if (file->f_mode & FMODE_WRITE) {
3014 wport = &devc->wport;
3015 pcm_flush_frag(devc);
3016 pcm_write_sync(devc);
3018 pcm_shutdown(devc, rport, wport);
3019 if (rport)
3020 rport->swstate = SW_OFF;
3021 if (wport)
3022 wport->swstate = SW_OFF;
3024 mutex_unlock(&devc->io_mutex);
3026 mutex_lock(&devc->open_mutex);
3028 devc->open_mode &= ~file->f_mode;
3030 mutex_unlock(&devc->open_mutex);
3031 wake_up(&devc->open_wait);
3032 DEC_USE_COUNT;
3033 DBGR();
3034 unlock_kernel();
3035 return err;
3038 static const struct file_operations vwsnd_audio_fops = {
3039 .owner = THIS_MODULE,
3040 .llseek = no_llseek,
3041 .read = vwsnd_audio_read,
3042 .write = vwsnd_audio_write,
3043 .poll = vwsnd_audio_poll,
3044 .ioctl = vwsnd_audio_ioctl,
3045 .mmap = vwsnd_audio_mmap,
3046 .open = vwsnd_audio_open,
3047 .release = vwsnd_audio_release,
3050 /*****************************************************************************/
3051 /* mixer driver */
3053 /* open the mixer device. */
3055 static int vwsnd_mixer_open(struct inode *inode, struct file *file)
3057 vwsnd_dev_t *devc;
3059 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3061 INC_USE_COUNT;
3062 for (devc = vwsnd_dev_list; devc; devc = devc->next_dev)
3063 if (devc->mixer_minor == iminor(inode))
3064 break;
3066 if (devc == NULL) {
3067 DEC_USE_COUNT;
3068 return -ENODEV;
3070 file->private_data = devc;
3071 return 0;
3074 /* release (close) the mixer device. */
3076 static int vwsnd_mixer_release(struct inode *inode, struct file *file)
3078 DBGEV("(inode=0x%p, file=0x%p)\n", inode, file);
3079 DEC_USE_COUNT;
3080 return 0;
3083 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3085 static int mixer_read_ioctl(vwsnd_dev_t *devc, unsigned int nr, void __user *arg)
3087 int val = -1;
3089 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3091 switch (nr) {
3092 case SOUND_MIXER_CAPS:
3093 val = SOUND_CAP_EXCL_INPUT;
3094 break;
3096 case SOUND_MIXER_DEVMASK:
3097 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3098 SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3099 break;
3101 case SOUND_MIXER_STEREODEVS:
3102 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3103 SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_RECLEV);
3104 break;
3106 case SOUND_MIXER_OUTMASK:
3107 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3108 SOUND_MASK_MIC | SOUND_MASK_CD);
3109 break;
3111 case SOUND_MIXER_RECMASK:
3112 val = (SOUND_MASK_PCM | SOUND_MASK_LINE |
3113 SOUND_MASK_MIC | SOUND_MASK_CD);
3114 break;
3116 case SOUND_MIXER_PCM:
3117 val = ad1843_get_gain(&devc->lith, &ad1843_gain_PCM);
3118 break;
3120 case SOUND_MIXER_LINE:
3121 val = ad1843_get_gain(&devc->lith, &ad1843_gain_LINE);
3122 break;
3124 case SOUND_MIXER_MIC:
3125 val = ad1843_get_gain(&devc->lith, &ad1843_gain_MIC);
3126 break;
3128 case SOUND_MIXER_CD:
3129 val = ad1843_get_gain(&devc->lith, &ad1843_gain_CD);
3130 break;
3132 case SOUND_MIXER_RECLEV:
3133 val = ad1843_get_gain(&devc->lith, &ad1843_gain_RECLEV);
3134 break;
3136 case SOUND_MIXER_RECSRC:
3137 val = ad1843_get_recsrc(&devc->lith);
3138 break;
3140 case SOUND_MIXER_OUTSRC:
3141 val = ad1843_get_outsrc(&devc->lith);
3142 break;
3144 default:
3145 return -EINVAL;
3147 return put_user(val, (int __user *) arg);
3150 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3152 static int mixer_write_ioctl(vwsnd_dev_t *devc, unsigned int nr, void __user *arg)
3154 int val;
3155 int err;
3157 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc, nr, arg);
3159 err = get_user(val, (int __user *) arg);
3160 if (err)
3161 return -EFAULT;
3162 switch (nr) {
3163 case SOUND_MIXER_PCM:
3164 val = ad1843_set_gain(&devc->lith, &ad1843_gain_PCM, val);
3165 break;
3167 case SOUND_MIXER_LINE:
3168 val = ad1843_set_gain(&devc->lith, &ad1843_gain_LINE, val);
3169 break;
3171 case SOUND_MIXER_MIC:
3172 val = ad1843_set_gain(&devc->lith, &ad1843_gain_MIC, val);
3173 break;
3175 case SOUND_MIXER_CD:
3176 val = ad1843_set_gain(&devc->lith, &ad1843_gain_CD, val);
3177 break;
3179 case SOUND_MIXER_RECLEV:
3180 val = ad1843_set_gain(&devc->lith, &ad1843_gain_RECLEV, val);
3181 break;
3183 case SOUND_MIXER_RECSRC:
3184 if (devc->rport.swbuf || devc->wport.swbuf)
3185 return -EBUSY; /* can't change recsrc while running */
3186 val = ad1843_set_recsrc(&devc->lith, val);
3187 break;
3189 case SOUND_MIXER_OUTSRC:
3190 val = ad1843_set_outsrc(&devc->lith, val);
3191 break;
3193 default:
3194 return -EINVAL;
3196 if (val < 0)
3197 return val;
3198 return put_user(val, (int __user *) arg);
3201 /* This is the ioctl entry to the mixer driver. */
3203 static int vwsnd_mixer_ioctl(struct inode *ioctl,
3204 struct file *file,
3205 unsigned int cmd,
3206 unsigned long arg)
3208 vwsnd_dev_t *devc = (vwsnd_dev_t *) file->private_data;
3209 const unsigned int nrmask = _IOC_NRMASK << _IOC_NRSHIFT;
3210 const unsigned int nr = (cmd & nrmask) >> _IOC_NRSHIFT;
3211 int retval;
3213 DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc, cmd, arg);
3215 mutex_lock(&devc->mix_mutex);
3217 if ((cmd & ~nrmask) == MIXER_READ(0))
3218 retval = mixer_read_ioctl(devc, nr, (void __user *) arg);
3219 else if ((cmd & ~nrmask) == MIXER_WRITE(0))
3220 retval = mixer_write_ioctl(devc, nr, (void __user *) arg);
3221 else
3222 retval = -EINVAL;
3224 mutex_unlock(&devc->mix_mutex);
3225 return retval;
3228 static const struct file_operations vwsnd_mixer_fops = {
3229 .owner = THIS_MODULE,
3230 .llseek = no_llseek,
3231 .ioctl = vwsnd_mixer_ioctl,
3232 .open = vwsnd_mixer_open,
3233 .release = vwsnd_mixer_release,
3236 /*****************************************************************************/
3237 /* probe/attach/unload */
3239 /* driver probe routine. Return nonzero if hardware is found. */
3241 static int __init probe_vwsnd(struct address_info *hw_config)
3243 lithium_t lith;
3244 int w;
3245 unsigned long later;
3247 DBGEV("(hw_config=0x%p)\n", hw_config);
3249 /* XXX verify lithium present (to prevent crash on non-vw) */
3251 if (li_create(&lith, hw_config->io_base) != 0) {
3252 printk(KERN_WARNING "probe_vwsnd: can't map lithium\n");
3253 return 0;
3255 later = jiffies + 2;
3256 li_writel(&lith, LI_HOST_CONTROLLER, LI_HC_LINK_ENABLE);
3257 do {
3258 w = li_readl(&lith, LI_HOST_CONTROLLER);
3259 } while (w == LI_HC_LINK_ENABLE && time_before(jiffies, later));
3261 li_destroy(&lith);
3263 DBGPV("HC = 0x%04x\n", w);
3265 if ((w == LI_HC_LINK_ENABLE) || (w & LI_HC_LINK_CODEC)) {
3267 /* This may indicate a beta machine with no audio,
3268 * or a future machine with different audio.
3269 * On beta-release 320 w/ no audio, HC == 0x4000 */
3271 printk(KERN_WARNING "probe_vwsnd: audio codec not found\n");
3272 return 0;
3275 if (w & LI_HC_LINK_FAILURE) {
3276 printk(KERN_WARNING "probe_vwsnd: can't init audio codec\n");
3277 return 0;
3280 printk(KERN_INFO "vwsnd: lithium audio at mmio %#x irq %d\n",
3281 hw_config->io_base, hw_config->irq);
3283 return 1;
3287 * driver attach routine. Initialize driver data structures and
3288 * initialize hardware. A new vwsnd_dev_t is allocated and put
3289 * onto the global list, vwsnd_dev_list.
3291 * Return +minor_dev on success, -errno on failure.
3294 static int __init attach_vwsnd(struct address_info *hw_config)
3296 vwsnd_dev_t *devc = NULL;
3297 int err = -ENOMEM;
3299 DBGEV("(hw_config=0x%p)\n", hw_config);
3301 devc = kmalloc(sizeof (vwsnd_dev_t), GFP_KERNEL);
3302 if (devc == NULL)
3303 goto fail0;
3305 err = li_create(&devc->lith, hw_config->io_base);
3306 if (err)
3307 goto fail1;
3309 init_waitqueue_head(&devc->open_wait);
3311 devc->rport.hwbuf_size = HWBUF_SIZE;
3312 devc->rport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3313 if (!devc->rport.hwbuf_vaddr)
3314 goto fail2;
3315 devc->rport.hwbuf = (void *) devc->rport.hwbuf_vaddr;
3316 devc->rport.hwbuf_paddr = virt_to_phys(devc->rport.hwbuf);
3319 * Quote from the NT driver:
3321 * // WARNING!!! HACK to setup output dma!!!
3322 * // This is required because even on output there is some data
3323 * // trickling into the input DMA channel. This is a bug in the
3324 * // Lithium microcode.
3325 * // --sde
3327 * We set the input side's DMA base address here. It will remain
3328 * valid until the driver is unloaded.
3331 li_writel(&devc->lith, LI_COMM1_BASE,
3332 devc->rport.hwbuf_paddr >> 8 | 1 << (37 - 8));
3334 devc->wport.hwbuf_size = HWBUF_SIZE;
3335 devc->wport.hwbuf_vaddr = __get_free_pages(GFP_KERNEL, HWBUF_ORDER);
3336 if (!devc->wport.hwbuf_vaddr)
3337 goto fail3;
3338 devc->wport.hwbuf = (void *) devc->wport.hwbuf_vaddr;
3339 devc->wport.hwbuf_paddr = virt_to_phys(devc->wport.hwbuf);
3340 DBGP("wport hwbuf = 0x%p\n", devc->wport.hwbuf);
3342 DBGDO(shut_up++);
3343 err = ad1843_init(&devc->lith);
3344 DBGDO(shut_up--);
3345 if (err)
3346 goto fail4;
3348 /* install interrupt handler */
3350 err = request_irq(hw_config->irq, vwsnd_audio_intr, 0, "vwsnd", devc);
3351 if (err)
3352 goto fail5;
3354 /* register this device's drivers. */
3356 devc->audio_minor = register_sound_dsp(&vwsnd_audio_fops, -1);
3357 if ((err = devc->audio_minor) < 0) {
3358 DBGDO(printk(KERN_WARNING
3359 "attach_vwsnd: register_sound_dsp error %d\n",
3360 err));
3361 goto fail6;
3363 devc->mixer_minor = register_sound_mixer(&vwsnd_mixer_fops,
3364 devc->audio_minor >> 4);
3365 if ((err = devc->mixer_minor) < 0) {
3366 DBGDO(printk(KERN_WARNING
3367 "attach_vwsnd: register_sound_mixer error %d\n",
3368 err));
3369 goto fail7;
3372 /* Squirrel away device indices for unload routine. */
3374 hw_config->slots[0] = devc->audio_minor;
3376 /* Initialize as much of *devc as possible */
3378 mutex_init(&devc->open_mutex);
3379 mutex_init(&devc->io_mutex);
3380 mutex_init(&devc->mix_mutex);
3381 devc->open_mode = 0;
3382 spin_lock_init(&devc->rport.lock);
3383 init_waitqueue_head(&devc->rport.queue);
3384 devc->rport.swstate = SW_OFF;
3385 devc->rport.hwstate = HW_STOPPED;
3386 devc->rport.flags = 0;
3387 devc->rport.swbuf = NULL;
3388 spin_lock_init(&devc->wport.lock);
3389 init_waitqueue_head(&devc->wport.queue);
3390 devc->wport.swstate = SW_OFF;
3391 devc->wport.hwstate = HW_STOPPED;
3392 devc->wport.flags = 0;
3393 devc->wport.swbuf = NULL;
3395 /* Success. Link us onto the local device list. */
3397 devc->next_dev = vwsnd_dev_list;
3398 vwsnd_dev_list = devc;
3399 return devc->audio_minor;
3401 /* So many ways to fail. Undo what we did. */
3403 fail7:
3404 unregister_sound_dsp(devc->audio_minor);
3405 fail6:
3406 free_irq(hw_config->irq, devc);
3407 fail5:
3408 fail4:
3409 free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3410 fail3:
3411 free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3412 fail2:
3413 li_destroy(&devc->lith);
3414 fail1:
3415 kfree(devc);
3416 fail0:
3417 return err;
3420 static int __exit unload_vwsnd(struct address_info *hw_config)
3422 vwsnd_dev_t *devc, **devcp;
3424 DBGE("()\n");
3426 devcp = &vwsnd_dev_list;
3427 while ((devc = *devcp)) {
3428 if (devc->audio_minor == hw_config->slots[0]) {
3429 *devcp = devc->next_dev;
3430 break;
3432 devcp = &devc->next_dev;
3435 if (!devc)
3436 return -ENODEV;
3438 unregister_sound_mixer(devc->mixer_minor);
3439 unregister_sound_dsp(devc->audio_minor);
3440 free_irq(hw_config->irq, devc);
3441 free_pages(devc->wport.hwbuf_vaddr, HWBUF_ORDER);
3442 free_pages(devc->rport.hwbuf_vaddr, HWBUF_ORDER);
3443 li_destroy(&devc->lith);
3444 kfree(devc);
3446 return 0;
3449 /*****************************************************************************/
3450 /* initialization and loadable kernel module interface */
3452 static struct address_info the_hw_config = {
3453 0xFF001000, /* lithium phys addr */
3454 CO_IRQ(CO_APIC_LI_AUDIO) /* irq */
3457 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3458 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3459 MODULE_LICENSE("GPL");
3461 static int __init init_vwsnd(void)
3463 int err;
3465 DBGXV("\n");
3466 DBGXV("sound::vwsnd::init_module()\n");
3468 if (!probe_vwsnd(&the_hw_config))
3469 return -ENODEV;
3471 err = attach_vwsnd(&the_hw_config);
3472 if (err < 0)
3473 return err;
3474 return 0;
3477 static void __exit cleanup_vwsnd(void)
3479 DBGX("sound::vwsnd::cleanup_module()\n");
3481 unload_vwsnd(&the_hw_config);
3484 module_init(init_vwsnd);
3485 module_exit(cleanup_vwsnd);