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v2.6.22.24-op1
[linux-2.6.22.y-op.git] / drivers / net / sky2.c
blob607b1a3228d5fee3a2c5b568aca24a8d7b718086
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
68
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
91 static int copybreak __read_mostly = 128;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
99 static const struct pci_device_id sky2_id_table[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
129 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
130 { 0 }
131 };
132
133 MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135 /* Avoid conditionals by using array */
136 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
138 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
139
140 /* This driver supports yukon2 chipset only */
141 static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "Extreme", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
147 };
148
149 /* Access to external PHY */
150 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
151 {
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
160 return 0;
161 udelay(1);
162 }
163
164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
165 return -ETIMEDOUT;
166 }
167
168 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
169 {
170 int i;
171
172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
181 udelay(1);
182 }
183
184 return -ETIMEDOUT;
185 }
186
187 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188 {
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
194 }
195
196
197 static void sky2_power_on(struct sky2_hw *hw)
198 {
199 /* switch power to VCC (WA for VAUX problem) */
200 sky2_write8(hw, B0_POWER_CTRL,
201 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
202
203 /* disable Core Clock Division, */
204 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
205
206 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
207 /* enable bits are inverted */
208 sky2_write8(hw, B2_Y2_CLK_GATE,
209 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
210 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
211 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
212 else
213 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
214
215 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
216 u32 reg1;
217
218 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
219 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
220 reg1 &= P_ASPM_CONTROL_MSK;
221 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
222 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
223 }
224 }
225
226 static void sky2_power_aux(struct sky2_hw *hw)
227 {
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230 else
231 /* enable bits are inverted */
232 sky2_write8(hw, B2_Y2_CLK_GATE,
233 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
234 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
235 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
236
237 /* switch power to VAUX */
238 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
239 sky2_write8(hw, B0_POWER_CTRL,
240 (PC_VAUX_ENA | PC_VCC_ENA |
241 PC_VAUX_ON | PC_VCC_OFF));
242 }
243
244 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
245 {
246 u16 reg;
247
248 /* disable all GMAC IRQ's */
249 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
250 /* disable PHY IRQs */
251 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
252
253 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
254 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
255 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
256 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
257
258 reg = gma_read16(hw, port, GM_RX_CTRL);
259 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
260 gma_write16(hw, port, GM_RX_CTRL, reg);
261 }
262
263 /* flow control to advertise bits */
264 static const u16 copper_fc_adv[] = {
265 [FC_NONE] = 0,
266 [FC_TX] = PHY_M_AN_ASP,
267 [FC_RX] = PHY_M_AN_PC,
268 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
269 };
270
271 /* flow control to advertise bits when using 1000BaseX */
272 static const u16 fiber_fc_adv[] = {
273 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
274 [FC_TX] = PHY_M_P_ASYM_MD_X,
275 [FC_RX] = PHY_M_P_SYM_MD_X,
276 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
277 };
278
279 /* flow control to GMA disable bits */
280 static const u16 gm_fc_disable[] = {
281 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
282 [FC_TX] = GM_GPCR_FC_RX_DIS,
283 [FC_RX] = GM_GPCR_FC_TX_DIS,
284 [FC_BOTH] = 0,
285 };
286
287
288 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
289 {
290 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
291 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
292
293 if (sky2->autoneg == AUTONEG_ENABLE
294 && !(hw->chip_id == CHIP_ID_YUKON_XL
295 || hw->chip_id == CHIP_ID_YUKON_EC_U
296 || hw->chip_id == CHIP_ID_YUKON_EX)) {
297 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
298
299 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
300 PHY_M_EC_MAC_S_MSK);
301 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
302
303 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 /* set downshift counter to 3x and enable downshift */
306 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 else
308 /* set master & slave downshift counter to 1x */
309 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (sky2_is_copper(hw)) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 /* downshift on PHY 88E1112 and 88E1149 is changed */
327 if (sky2->autoneg == AUTONEG_ENABLE
328 && (hw->chip_id == CHIP_ID_YUKON_XL
329 || hw->chip_id == CHIP_ID_YUKON_EC_U
330 || hw->chip_id == CHIP_ID_YUKON_EX)) {
331 /* set downshift counter to 3x and enable downshift */
332 ctrl &= ~PHY_M_PC_DSC_MSK;
333 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
334 }
335 }
336 } else {
337 /* workaround for deviation #4.88 (CRC errors) */
338 /* disable Automatic Crossover */
339
340 ctrl &= ~PHY_M_PC_MDIX_MSK;
341 }
342
343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344
345 /* special setup for PHY 88E1112 Fiber */
346 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
347 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
348
349 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl &= ~PHY_M_MAC_MD_MSK;
353 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
354 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
355
356 if (hw->pmd_type == 'P') {
357 /* select page 1 to access Fiber registers */
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
359
360 /* for SFP-module set SIGDET polarity to low */
361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
362 ctrl |= PHY_M_FIB_SIGD_POL;
363 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
364 }
365
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
367 }
368
369 ctrl = PHY_CT_RESET;
370 ct1000 = 0;
371 adv = PHY_AN_CSMA;
372 reg = 0;
373
374 if (sky2->autoneg == AUTONEG_ENABLE) {
375 if (sky2_is_copper(hw)) {
376 if (sky2->advertising & ADVERTISED_1000baseT_Full)
377 ct1000 |= PHY_M_1000C_AFD;
378 if (sky2->advertising & ADVERTISED_1000baseT_Half)
379 ct1000 |= PHY_M_1000C_AHD;
380 if (sky2->advertising & ADVERTISED_100baseT_Full)
381 adv |= PHY_M_AN_100_FD;
382 if (sky2->advertising & ADVERTISED_100baseT_Half)
383 adv |= PHY_M_AN_100_HD;
384 if (sky2->advertising & ADVERTISED_10baseT_Full)
385 adv |= PHY_M_AN_10_FD;
386 if (sky2->advertising & ADVERTISED_10baseT_Half)
387 adv |= PHY_M_AN_10_HD;
388
389 adv |= copper_fc_adv[sky2->flow_mode];
390 } else { /* special defines for FIBER (88E1040S only) */
391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 adv |= PHY_M_AN_1000X_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 adv |= PHY_M_AN_1000X_AHD;
395
396 adv |= fiber_fc_adv[sky2->flow_mode];
397 }
398
399 /* Restart Auto-negotiation */
400 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
401 } else {
402 /* forced speed/duplex settings */
403 ct1000 = PHY_M_1000C_MSE;
404
405 /* Disable auto update for duplex flow control and speed */
406 reg |= GM_GPCR_AU_ALL_DIS;
407
408 switch (sky2->speed) {
409 case SPEED_1000:
410 ctrl |= PHY_CT_SP1000;
411 reg |= GM_GPCR_SPEED_1000;
412 break;
413 case SPEED_100:
414 ctrl |= PHY_CT_SP100;
415 reg |= GM_GPCR_SPEED_100;
416 break;
417 }
418
419 if (sky2->duplex == DUPLEX_FULL) {
420 reg |= GM_GPCR_DUP_FULL;
421 ctrl |= PHY_CT_DUP_MD;
422 } else if (sky2->speed < SPEED_1000)
423 sky2->flow_mode = FC_NONE;
424
425
426 reg |= gm_fc_disable[sky2->flow_mode];
427
428 /* Forward pause packets to GMAC? */
429 if (sky2->flow_mode & FC_RX)
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
431 else
432 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
433 }
434
435 gma_write16(hw, port, GM_GP_CTRL, reg);
436
437 if (hw->chip_id != CHIP_ID_YUKON_FE)
438 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
439
440 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
441 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
442
443 /* Setup Phy LED's */
444 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
445 ledover = 0;
446
447 switch (hw->chip_id) {
448 case CHIP_ID_YUKON_FE:
449 /* on 88E3082 these bits are at 11..9 (shifted left) */
450 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
451
452 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
453
454 /* delete ACT LED control bits */
455 ctrl &= ~PHY_M_FELP_LED1_MSK;
456 /* change ACT LED control to blink mode */
457 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
458 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
459 break;
460
461 case CHIP_ID_YUKON_XL:
462 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
463
464 /* select page 3 to access LED control register */
465 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
466
467 /* set LED Function Control register */
468 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
469 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
470 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
471 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
472 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
473
474 /* set Polarity Control register */
475 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
476 (PHY_M_POLC_LS1_P_MIX(4) |
477 PHY_M_POLC_IS0_P_MIX(4) |
478 PHY_M_POLC_LOS_CTRL(2) |
479 PHY_M_POLC_INIT_CTRL(2) |
480 PHY_M_POLC_STA1_CTRL(2) |
481 PHY_M_POLC_STA0_CTRL(2)));
482
483 /* restore page register */
484 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
485 break;
486
487 case CHIP_ID_YUKON_EC_U:
488 case CHIP_ID_YUKON_EX:
489 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
490
491 /* select page 3 to access LED control register */
492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
493
494 /* set LED Function Control register */
495 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
496 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
497 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
498 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
499 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
500
501 /* set Blink Rate in LED Timer Control Register */
502 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
503 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
504 /* restore page register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
506 break;
507
508 default:
509 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
510 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
511 /* turn off the Rx LED (LED_RX) */
512 ledover &= ~PHY_M_LED_MO_RX;
513 }
514
515 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
516 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
517 /* apply fixes in PHY AFE */
518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
519
520 /* increase differential signal amplitude in 10BASE-T */
521 gm_phy_write(hw, port, 0x18, 0xaa99);
522 gm_phy_write(hw, port, 0x17, 0x2011);
523
524 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
525 gm_phy_write(hw, port, 0x18, 0xa204);
526 gm_phy_write(hw, port, 0x17, 0x2002);
527
528 /* set page register to 0 */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
530 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
531 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
532
533 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
534 /* turn on 100 Mbps LED (LED_LINK100) */
535 ledover |= PHY_M_LED_MO_100;
536 }
537
538 if (ledover)
539 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
540
541 }
542
543 /* Enable phy interrupt on auto-negotiation complete (or link up) */
544 if (sky2->autoneg == AUTONEG_ENABLE)
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
546 else
547 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
548 }
549
550 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
551 {
552 u32 reg1;
553 static const u32 phy_power[]
554 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
555
556 /* looks like this XL is back asswards .. */
557 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
558 onoff = !onoff;
559
560 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
561 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
562 if (onoff)
563 /* Turn off phy power saving */
564 reg1 &= ~phy_power[port];
565 else
566 reg1 |= phy_power[port];
567
568 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
569 sky2_pci_read32(hw, PCI_DEV_REG1);
570 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
571 udelay(100);
572 }
573
574 /* Force a renegotiation */
575 static void sky2_phy_reinit(struct sky2_port *sky2)
576 {
577 spin_lock_bh(&sky2->phy_lock);
578 sky2_phy_init(sky2->hw, sky2->port);
579 spin_unlock_bh(&sky2->phy_lock);
580 }
581
582 /* Put device in state to listen for Wake On Lan */
583 static void sky2_wol_init(struct sky2_port *sky2)
584 {
585 struct sky2_hw *hw = sky2->hw;
586 unsigned port = sky2->port;
587 enum flow_control save_mode;
588 u16 ctrl;
589 u32 reg1;
590
591 /* Bring hardware out of reset */
592 sky2_write16(hw, B0_CTST, CS_RST_CLR);
593 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
594
595 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
596 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
597
598 /* Force to 10/100
599 * sky2_reset will re-enable on resume
600 */
601 save_mode = sky2->flow_mode;
602 ctrl = sky2->advertising;
603
604 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
605 sky2->flow_mode = FC_NONE;
606 sky2_phy_power(hw, port, 1);
607 sky2_phy_reinit(sky2);
608
609 sky2->flow_mode = save_mode;
610 sky2->advertising = ctrl;
611
612 /* Set GMAC to no flow control and auto update for speed/duplex */
613 gma_write16(hw, port, GM_GP_CTRL,
614 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
615 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
616
617 /* Set WOL address */
618 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
619 sky2->netdev->dev_addr, ETH_ALEN);
620
621 /* Turn on appropriate WOL control bits */
622 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
623 ctrl = 0;
624 if (sky2->wol & WAKE_PHY)
625 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
626 else
627 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
628
629 if (sky2->wol & WAKE_MAGIC)
630 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
631 else
632 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
633
634 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
635 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
636
637 /* Turn on legacy PCI-Express PME mode */
638 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
639 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
640 reg1 |= PCI_Y2_PME_LEGACY;
641 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
643
644 /* block receiver */
645 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
646
647 }
648
649 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
650 {
651 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
652 u16 reg;
653 int i;
654 const u8 *addr = hw->dev[port]->dev_addr;
655
656 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
657 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
658
659 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
660
661 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
662 /* WA DEV_472 -- looks like crossed wires on port 2 */
663 /* clear GMAC 1 Control reset */
664 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
665 do {
666 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
667 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
668 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
669 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
670 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
671 }
672
673 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
674
675 /* Enable Transmit FIFO Underrun */
676 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
677
678 spin_lock_bh(&sky2->phy_lock);
679 sky2_phy_init(hw, port);
680 spin_unlock_bh(&sky2->phy_lock);
681
682 /* MIB clear */
683 reg = gma_read16(hw, port, GM_PHY_ADDR);
684 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
685
686 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
687 gma_read16(hw, port, i);
688 gma_write16(hw, port, GM_PHY_ADDR, reg);
689
690 /* transmit control */
691 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
692
693 /* receive control reg: unicast + multicast + no FCS */
694 gma_write16(hw, port, GM_RX_CTRL,
695 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
696
697 /* transmit flow control */
698 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
699
700 /* transmit parameter */
701 gma_write16(hw, port, GM_TX_PARAM,
702 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
703 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
704 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
705 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
706
707 /* serial mode register */
708 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
709 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
710
711 if (hw->dev[port]->mtu > ETH_DATA_LEN)
712 reg |= GM_SMOD_JUMBO_ENA;
713
714 gma_write16(hw, port, GM_SERIAL_MODE, reg);
715
716 /* virtual address for data */
717 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
718
719 /* physical address: used for pause frames */
720 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
721
722 /* ignore counter overflows */
723 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
724 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
725 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
726
727 /* Configure Rx MAC FIFO */
728 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
729 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
730 GMF_OPER_ON | GMF_RX_F_FL_ON);
731
732 /* Flush Rx MAC FIFO on any flow control or error */
733 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
734
735 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
736 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
737
738 /* Configure Tx MAC FIFO */
739 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
740 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
741
742 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
743 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
744 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
745
746 /* set Tx GMAC FIFO Almost Empty Threshold */
747 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
748 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
749
750 if (hw->dev[port]->mtu > ETH_DATA_LEN)
751 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
752 TX_JUMBO_ENA | TX_STFW_DIS);
753 else
754 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
755 TX_JUMBO_DIS | TX_STFW_ENA);
756 }
757
758 }
759
760 /* Assign Ram Buffer allocation to queue */
761 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
762 {
763 u32 end;
764
765 /* convert from K bytes to qwords used for hw register */
766 start *= 1024/8;
767 space *= 1024/8;
768 end = start + space - 1;
769
770 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
771 sky2_write32(hw, RB_ADDR(q, RB_START), start);
772 sky2_write32(hw, RB_ADDR(q, RB_END), end);
773 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
774 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
775
776 if (q == Q_R1 || q == Q_R2) {
777 u32 tp = space - space/4;
778
779 /* On receive queue's set the thresholds
780 * give receiver priority when > 3/4 full
781 * send pause when down to 2K
782 */
783 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
784 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
785
786 tp = space - 2048/8;
787 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
789 } else {
790 /* Enable store & forward on Tx queue's because
791 * Tx FIFO is only 1K on Yukon
792 */
793 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
794 }
795
796 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
797 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
798 }
799
800 /* Setup Bus Memory Interface */
801 static void sky2_qset(struct sky2_hw *hw, u16 q)
802 {
803 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
806 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
807 }
808
809 /* Setup prefetch unit registers. This is the interface between
810 * hardware and driver list elements
811 */
812 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
813 u64 addr, u32 last)
814 {
815 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
819 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
821
822 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
823 }
824
825 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
826 {
827 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
828
829 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
830 le->ctrl = 0;
831 return le;
832 }
833
834 static void tx_init(struct sky2_port *sky2)
835 {
836 struct sky2_tx_le *le;
837
838 sky2->tx_prod = sky2->tx_cons = 0;
839 sky2->tx_tcpsum = 0;
840 sky2->tx_last_mss = 0;
841
842 le = get_tx_le(sky2);
843 le->addr = 0;
844 le->opcode = OP_ADDR64 | HW_OWNER;
845 sky2->tx_addr64 = 0;
846 }
847
848 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
849 struct sky2_tx_le *le)
850 {
851 return sky2->tx_ring + (le - sky2->tx_le);
852 }
853
854 /* Update chip's next pointer */
855 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
856 {
857 /* Make sure write' to descriptors are complete before we tell hardware */
858 wmb();
859 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
860
861 /* Synchronize I/O on since next processor may write to tail */
862 mmiowb();
863 }
864
865
866 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
867 {
868 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
869 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
870 le->ctrl = 0;
871 return le;
872 }
873
874 /* Return high part of DMA address (could be 32 or 64 bit) */
875 static inline u32 high32(dma_addr_t a)
876 {
877 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
878 }
879
880 /* Build description to hardware for one receive segment */
881 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
882 dma_addr_t map, unsigned len)
883 {
884 struct sky2_rx_le *le;
885 u32 hi = high32(map);
886
887 if (sky2->rx_addr64 != hi) {
888 le = sky2_next_rx(sky2);
889 le->addr = cpu_to_le32(hi);
890 le->opcode = OP_ADDR64 | HW_OWNER;
891 sky2->rx_addr64 = high32(map + len);
892 }
893
894 le = sky2_next_rx(sky2);
895 le->addr = cpu_to_le32((u32) map);
896 le->length = cpu_to_le16(len);
897 le->opcode = op | HW_OWNER;
898 }
899
900 /* Build description to hardware for one possibly fragmented skb */
901 static void sky2_rx_submit(struct sky2_port *sky2,
902 const struct rx_ring_info *re)
903 {
904 int i;
905
906 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
907
908 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
909 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
910 }
911
912
913 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
914 unsigned size)
915 {
916 struct sk_buff *skb = re->skb;
917 int i;
918
919 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
920 pci_unmap_len_set(re, data_size, size);
921
922 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
923 re->frag_addr[i] = pci_map_page(pdev,
924 skb_shinfo(skb)->frags[i].page,
925 skb_shinfo(skb)->frags[i].page_offset,
926 skb_shinfo(skb)->frags[i].size,
927 PCI_DMA_FROMDEVICE);
928 }
929
930 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
931 {
932 struct sk_buff *skb = re->skb;
933 int i;
934
935 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
936 PCI_DMA_FROMDEVICE);
937
938 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
939 pci_unmap_page(pdev, re->frag_addr[i],
940 skb_shinfo(skb)->frags[i].size,
941 PCI_DMA_FROMDEVICE);
942 }
943
944 /* Tell chip where to start receive checksum.
945 * Actually has two checksums, but set both same to avoid possible byte
946 * order problems.
947 */
948 static void rx_set_checksum(struct sky2_port *sky2)
949 {
950 struct sky2_rx_le *le;
951
952 le = sky2_next_rx(sky2);
953 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
954 le->ctrl = 0;
955 le->opcode = OP_TCPSTART | HW_OWNER;
956
957 sky2_write32(sky2->hw,
958 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
959 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
960
961 }
962
963 /*
964 * The RX Stop command will not work for Yukon-2 if the BMU does not
965 * reach the end of packet and since we can't make sure that we have
966 * incoming data, we must reset the BMU while it is not doing a DMA
967 * transfer. Since it is possible that the RX path is still active,
968 * the RX RAM buffer will be stopped first, so any possible incoming
969 * data will not trigger a DMA. After the RAM buffer is stopped, the
970 * BMU is polled until any DMA in progress is ended and only then it
971 * will be reset.
972 */
973 static void sky2_rx_stop(struct sky2_port *sky2)
974 {
975 struct sky2_hw *hw = sky2->hw;
976 unsigned rxq = rxqaddr[sky2->port];
977 int i;
978
979 /* disable the RAM Buffer receive queue */
980 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
981
982 for (i = 0; i < 0xffff; i++)
983 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
984 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
985 goto stopped;
986
987 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
988 sky2->netdev->name);
989 stopped:
990 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
991
992 /* reset the Rx prefetch unit */
993 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
994 mmiowb();
995 }
996
997 /* Clean out receive buffer area, assumes receiver hardware stopped */
998 static void sky2_rx_clean(struct sky2_port *sky2)
999 {
1000 unsigned i;
1001
1002 memset(sky2->rx_le, 0, RX_LE_BYTES);
1003 for (i = 0; i < sky2->rx_pending; i++) {
1004 struct rx_ring_info *re = sky2->rx_ring + i;
1005
1006 if (re->skb) {
1007 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1008 kfree_skb(re->skb);
1009 re->skb = NULL;
1010 }
1011 }
1012 }
1013
1014 /* Basic MII support */
1015 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1016 {
1017 struct mii_ioctl_data *data = if_mii(ifr);
1018 struct sky2_port *sky2 = netdev_priv(dev);
1019 struct sky2_hw *hw = sky2->hw;
1020 int err = -EOPNOTSUPP;
1021
1022 if (!netif_running(dev))
1023 return -ENODEV; /* Phy still in reset */
1024
1025 switch (cmd) {
1026 case SIOCGMIIPHY:
1027 data->phy_id = PHY_ADDR_MARV;
1028
1029 /* fallthru */
1030 case SIOCGMIIREG: {
1031 u16 val = 0;
1032
1033 spin_lock_bh(&sky2->phy_lock);
1034 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1035 spin_unlock_bh(&sky2->phy_lock);
1036
1037 data->val_out = val;
1038 break;
1039 }
1040
1041 case SIOCSMIIREG:
1042 if (!capable(CAP_NET_ADMIN))
1043 return -EPERM;
1044
1045 spin_lock_bh(&sky2->phy_lock);
1046 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1047 data->val_in);
1048 spin_unlock_bh(&sky2->phy_lock);
1049 break;
1050 }
1051 return err;
1052 }
1053
1054 #ifdef SKY2_VLAN_TAG_USED
1055 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1056 {
1057 struct sky2_port *sky2 = netdev_priv(dev);
1058 struct sky2_hw *hw = sky2->hw;
1059 u16 port = sky2->port;
1060
1061 netif_tx_lock_bh(dev);
1062 netif_poll_disable(sky2->hw->dev[0]);
1063
1064 sky2->vlgrp = grp;
1065 if (grp) {
1066 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1067 RX_VLAN_STRIP_ON);
1068 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1069 TX_VLAN_TAG_ON);
1070 } else {
1071 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1072 RX_VLAN_STRIP_OFF);
1073 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1074 TX_VLAN_TAG_OFF);
1075 }
1076
1077 netif_poll_enable(sky2->hw->dev[0]);
1078 netif_tx_unlock_bh(dev);
1079 }
1080 #endif
1081
1082 /*
1083 * Allocate an skb for receiving. If the MTU is large enough
1084 * make the skb non-linear with a fragment list of pages.
1085 *
1086 * It appears the hardware has a bug in the FIFO logic that
1087 * cause it to hang if the FIFO gets overrun and the receive buffer
1088 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1089 * aligned except if slab debugging is enabled.
1090 */
1091 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1092 {
1093 struct sk_buff *skb;
1094 unsigned long p;
1095 int i;
1096
1097 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1098 if (!skb)
1099 goto nomem;
1100
1101 p = (unsigned long) skb->data;
1102 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1103
1104 for (i = 0; i < sky2->rx_nfrags; i++) {
1105 struct page *page = alloc_page(GFP_ATOMIC);
1106
1107 if (!page)
1108 goto free_partial;
1109 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1110 }
1111
1112 return skb;
1113 free_partial:
1114 kfree_skb(skb);
1115 nomem:
1116 return NULL;
1117 }
1118
1119 /*
1120 * Allocate and setup receiver buffer pool.
1121 * Normal case this ends up creating one list element for skb
1122 * in the receive ring. Worst case if using large MTU and each
1123 * allocation falls on a different 64 bit region, that results
1124 * in 6 list elements per ring entry.
1125 * One element is used for checksum enable/disable, and one
1126 * extra to avoid wrap.
1127 */
1128 static int sky2_rx_start(struct sky2_port *sky2)
1129 {
1130 struct sky2_hw *hw = sky2->hw;
1131 struct rx_ring_info *re;
1132 unsigned rxq = rxqaddr[sky2->port];
1133 unsigned i, size, space, thresh;
1134
1135 sky2->rx_put = sky2->rx_next = 0;
1136 sky2_qset(hw, rxq);
1137
1138 /* On PCI express lowering the watermark gives better performance */
1139 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1140 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1141
1142 /* These chips have no ram buffer?
1143 * MAC Rx RAM Read is controlled by hardware */
1144 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1145 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1146 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1147 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1148
1149 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1150
1151 rx_set_checksum(sky2);
1152
1153 /* Space needed for frame data + headers rounded up */
1154 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1155 + 8;
1156
1157 /* Stopping point for hardware truncation */
1158 thresh = (size - 8) / sizeof(u32);
1159
1160 /* Account for overhead of skb - to avoid order > 0 allocation */
1161 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1162 + sizeof(struct skb_shared_info);
1163
1164 sky2->rx_nfrags = space >> PAGE_SHIFT;
1165 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1166
1167 if (sky2->rx_nfrags != 0) {
1168 /* Compute residue after pages */
1169 space = sky2->rx_nfrags << PAGE_SHIFT;
1170
1171 if (space < size)
1172 size -= space;
1173 else
1174 size = 0;
1175
1176 /* Optimize to handle small packets and headers */
1177 if (size < copybreak)
1178 size = copybreak;
1179 if (size < ETH_HLEN)
1180 size = ETH_HLEN;
1181 }
1182 sky2->rx_data_size = size;
1183
1184 /* Fill Rx ring */
1185 for (i = 0; i < sky2->rx_pending; i++) {
1186 re = sky2->rx_ring + i;
1187
1188 re->skb = sky2_rx_alloc(sky2);
1189 if (!re->skb)
1190 goto nomem;
1191
1192 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1193 sky2_rx_submit(sky2, re);
1194 }
1195
1196 /*
1197 * The receiver hangs if it receives frames larger than the
1198 * packet buffer. As a workaround, truncate oversize frames, but
1199 * the register is limited to 9 bits, so if you do frames > 2052
1200 * you better get the MTU right!
1201 */
1202 if (thresh > 0x1ff)
1203 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1204 else {
1205 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1206 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1207 }
1208
1209 /* Tell chip about available buffers */
1210 sky2_put_idx(hw, rxq, sky2->rx_put);
1211 return 0;
1212 nomem:
1213 sky2_rx_clean(sky2);
1214 return -ENOMEM;
1215 }
1216
1217 /* Bring up network interface. */
1218 static int sky2_up(struct net_device *dev)
1219 {
1220 struct sky2_port *sky2 = netdev_priv(dev);
1221 struct sky2_hw *hw = sky2->hw;
1222 unsigned port = sky2->port;
1223 u32 ramsize, imask;
1224 int cap, err = -ENOMEM;
1225 struct net_device *otherdev = hw->dev[sky2->port^1];
1226
1227 /*
1228 * On dual port PCI-X card, there is an problem where status
1229 * can be received out of order due to split transactions
1230 */
1231 if (otherdev && netif_running(otherdev) &&
1232 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1233 struct sky2_port *osky2 = netdev_priv(otherdev);
1234 u16 cmd;
1235
1236 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1237 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1238 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1239
1240 sky2->rx_csum = 0;
1241 osky2->rx_csum = 0;
1242 }
1243
1244 if (netif_msg_ifup(sky2))
1245 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1246
1247 netif_carrier_off(dev);
1248
1249 /* must be power of 2 */
1250 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1251 TX_RING_SIZE *
1252 sizeof(struct sky2_tx_le),
1253 &sky2->tx_le_map);
1254 if (!sky2->tx_le)
1255 goto err_out;
1256
1257 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1258 GFP_KERNEL);
1259 if (!sky2->tx_ring)
1260 goto err_out;
1261
1262 tx_init(sky2);
1263
1264 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1265 &sky2->rx_le_map);
1266 if (!sky2->rx_le)
1267 goto err_out;
1268 memset(sky2->rx_le, 0, RX_LE_BYTES);
1269
1270 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1271 GFP_KERNEL);
1272 if (!sky2->rx_ring)
1273 goto err_out;
1274
1275 sky2_phy_power(hw, port, 1);
1276
1277 sky2_mac_init(hw, port);
1278
1279 /* Register is number of 4K blocks on internal RAM buffer. */
1280 ramsize = sky2_read8(hw, B2_E_0) * 4;
1281 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1282
1283 if (ramsize > 0) {
1284 u32 rxspace;
1285
1286 if (ramsize < 16)
1287 rxspace = ramsize / 2;
1288 else
1289 rxspace = 8 + (2*(ramsize - 16))/3;
1290
1291 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1292 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1293
1294 /* Make sure SyncQ is disabled */
1295 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1296 RB_RST_SET);
1297 }
1298
1299 sky2_qset(hw, txqaddr[port]);
1300
1301 /* Set almost empty threshold */
1302 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1303 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1304 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1305
1306 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1307 TX_RING_SIZE - 1);
1308
1309 err = sky2_rx_start(sky2);
1310 if (err)
1311 goto err_out;
1312
1313 /* Enable interrupts from phy/mac for port */
1314 imask = sky2_read32(hw, B0_IMSK);
1315 imask |= portirq_msk[port];
1316 sky2_write32(hw, B0_IMSK, imask);
1317
1318 return 0;
1319
1320 err_out:
1321 if (sky2->rx_le) {
1322 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1323 sky2->rx_le, sky2->rx_le_map);
1324 sky2->rx_le = NULL;
1325 }
1326 if (sky2->tx_le) {
1327 pci_free_consistent(hw->pdev,
1328 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1329 sky2->tx_le, sky2->tx_le_map);
1330 sky2->tx_le = NULL;
1331 }
1332 kfree(sky2->tx_ring);
1333 kfree(sky2->rx_ring);
1334
1335 sky2->tx_ring = NULL;
1336 sky2->rx_ring = NULL;
1337 return err;
1338 }
1339
1340 /* Modular subtraction in ring */
1341 static inline int tx_dist(unsigned tail, unsigned head)
1342 {
1343 return (head - tail) & (TX_RING_SIZE - 1);
1344 }
1345
1346 /* Number of list elements available for next tx */
1347 static inline int tx_avail(const struct sky2_port *sky2)
1348 {
1349 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1350 }
1351
1352 /* Estimate of number of transmit list elements required */
1353 static unsigned tx_le_req(const struct sk_buff *skb)
1354 {
1355 unsigned count;
1356
1357 count = sizeof(dma_addr_t) / sizeof(u32);
1358 count += skb_shinfo(skb)->nr_frags * count;
1359
1360 if (skb_is_gso(skb))
1361 ++count;
1362
1363 if (skb->ip_summed == CHECKSUM_PARTIAL)
1364 ++count;
1365
1366 return count;
1367 }
1368
1369 /*
1370 * Put one packet in ring for transmit.
1371 * A single packet can generate multiple list elements, and
1372 * the number of ring elements will probably be less than the number
1373 * of list elements used.
1374 */
1375 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1376 {
1377 struct sky2_port *sky2 = netdev_priv(dev);
1378 struct sky2_hw *hw = sky2->hw;
1379 struct sky2_tx_le *le = NULL;
1380 struct tx_ring_info *re;
1381 unsigned i, len;
1382 dma_addr_t mapping;
1383 u32 addr64;
1384 u16 mss;
1385 u8 ctrl;
1386
1387 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1388 return NETDEV_TX_BUSY;
1389
1390 if (unlikely(netif_msg_tx_queued(sky2)))
1391 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1392 dev->name, sky2->tx_prod, skb->len);
1393
1394 len = skb_headlen(skb);
1395 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1396 addr64 = high32(mapping);
1397
1398 /* Send high bits if changed or crosses boundary */
1399 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1400 le = get_tx_le(sky2);
1401 le->addr = cpu_to_le32(addr64);
1402 le->opcode = OP_ADDR64 | HW_OWNER;
1403 sky2->tx_addr64 = high32(mapping + len);
1404 }
1405
1406 /* Check for TCP Segmentation Offload */
1407 mss = skb_shinfo(skb)->gso_size;
1408 if (mss != 0) {
1409 mss += tcp_optlen(skb); /* TCP options */
1410 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
1411 mss += ETH_HLEN;
1412
1413 if (mss != sky2->tx_last_mss) {
1414 le = get_tx_le(sky2);
1415 le->addr = cpu_to_le32(mss);
1416 le->opcode = OP_LRGLEN | HW_OWNER;
1417 sky2->tx_last_mss = mss;
1418 }
1419 }
1420
1421 ctrl = 0;
1422 #ifdef SKY2_VLAN_TAG_USED
1423 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1424 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1425 if (!le) {
1426 le = get_tx_le(sky2);
1427 le->addr = 0;
1428 le->opcode = OP_VLAN|HW_OWNER;
1429 } else
1430 le->opcode |= OP_VLAN;
1431 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1432 ctrl |= INS_VLAN;
1433 }
1434 #endif
1435
1436 /* Handle TCP checksum offload */
1437 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1438 const unsigned offset = skb_transport_offset(skb);
1439 u32 tcpsum;
1440
1441 tcpsum = offset << 16; /* sum start */
1442 tcpsum |= offset + skb->csum_offset; /* sum write */
1443
1444 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1445 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1446 ctrl |= UDPTCP;
1447
1448 if (tcpsum != sky2->tx_tcpsum) {
1449 sky2->tx_tcpsum = tcpsum;
1450
1451 le = get_tx_le(sky2);
1452 le->addr = cpu_to_le32(tcpsum);
1453 le->length = 0; /* initial checksum value */
1454 le->ctrl = 1; /* one packet */
1455 le->opcode = OP_TCPLISW | HW_OWNER;
1456 }
1457 }
1458
1459 le = get_tx_le(sky2);
1460 le->addr = cpu_to_le32((u32) mapping);
1461 le->length = cpu_to_le16(len);
1462 le->ctrl = ctrl;
1463 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1464
1465 re = tx_le_re(sky2, le);
1466 re->skb = skb;
1467 pci_unmap_addr_set(re, mapaddr, mapping);
1468 pci_unmap_len_set(re, maplen, len);
1469
1470 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1471 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1472
1473 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1474 frag->size, PCI_DMA_TODEVICE);
1475 addr64 = high32(mapping);
1476 if (addr64 != sky2->tx_addr64) {
1477 le = get_tx_le(sky2);
1478 le->addr = cpu_to_le32(addr64);
1479 le->ctrl = 0;
1480 le->opcode = OP_ADDR64 | HW_OWNER;
1481 sky2->tx_addr64 = addr64;
1482 }
1483
1484 le = get_tx_le(sky2);
1485 le->addr = cpu_to_le32((u32) mapping);
1486 le->length = cpu_to_le16(frag->size);
1487 le->ctrl = ctrl;
1488 le->opcode = OP_BUFFER | HW_OWNER;
1489
1490 re = tx_le_re(sky2, le);
1491 re->skb = skb;
1492 pci_unmap_addr_set(re, mapaddr, mapping);
1493 pci_unmap_len_set(re, maplen, frag->size);
1494 }
1495
1496 le->ctrl |= EOP;
1497
1498 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1499 netif_stop_queue(dev);
1500
1501 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1502
1503 dev->trans_start = jiffies;
1504 return NETDEV_TX_OK;
1505 }
1506
1507 /*
1508 * Free ring elements from starting at tx_cons until "done"
1509 *
1510 * NB: the hardware will tell us about partial completion of multi-part
1511 * buffers so make sure not to free skb to early.
1512 */
1513 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1514 {
1515 struct net_device *dev = sky2->netdev;
1516 struct pci_dev *pdev = sky2->hw->pdev;
1517 unsigned idx;
1518
1519 BUG_ON(done >= TX_RING_SIZE);
1520
1521 for (idx = sky2->tx_cons; idx != done;
1522 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1523 struct sky2_tx_le *le = sky2->tx_le + idx;
1524 struct tx_ring_info *re = sky2->tx_ring + idx;
1525
1526 switch(le->opcode & ~HW_OWNER) {
1527 case OP_LARGESEND:
1528 case OP_PACKET:
1529 pci_unmap_single(pdev,
1530 pci_unmap_addr(re, mapaddr),
1531 pci_unmap_len(re, maplen),
1532 PCI_DMA_TODEVICE);
1533 break;
1534 case OP_BUFFER:
1535 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1536 pci_unmap_len(re, maplen),
1537 PCI_DMA_TODEVICE);
1538 break;
1539 }
1540
1541 if (le->ctrl & EOP) {
1542 if (unlikely(netif_msg_tx_done(sky2)))
1543 printk(KERN_DEBUG "%s: tx done %u\n",
1544 dev->name, idx);
1545 sky2->net_stats.tx_packets++;
1546 sky2->net_stats.tx_bytes += re->skb->len;
1547
1548 dev_kfree_skb_any(re->skb);
1549 }
1550
1551 le->opcode = 0; /* paranoia */
1552 }
1553
1554 sky2->tx_cons = idx;
1555 smp_mb();
1556
1557 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1558 netif_wake_queue(dev);
1559 }
1560
1561 /* Cleanup all untransmitted buffers, assume transmitter not running */
1562 static void sky2_tx_clean(struct net_device *dev)
1563 {
1564 struct sky2_port *sky2 = netdev_priv(dev);
1565
1566 netif_tx_lock_bh(dev);
1567 sky2_tx_complete(sky2, sky2->tx_prod);
1568 netif_tx_unlock_bh(dev);
1569 }
1570
1571 /* Network shutdown */
1572 static int sky2_down(struct net_device *dev)
1573 {
1574 struct sky2_port *sky2 = netdev_priv(dev);
1575 struct sky2_hw *hw = sky2->hw;
1576 unsigned port = sky2->port;
1577 u16 ctrl;
1578 u32 imask;
1579
1580 /* Never really got started! */
1581 if (!sky2->tx_le)
1582 return 0;
1583
1584 if (netif_msg_ifdown(sky2))
1585 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1586
1587 /* Stop more packets from being queued */
1588 netif_stop_queue(dev);
1589
1590 /* Disable port IRQ */
1591 imask = sky2_read32(hw, B0_IMSK);
1592 imask &= ~portirq_msk[port];
1593 sky2_write32(hw, B0_IMSK, imask);
1594
1595 sky2_gmac_reset(hw, port);
1596
1597 /* Stop transmitter */
1598 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1599 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1600
1601 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1602 RB_RST_SET | RB_DIS_OP_MD);
1603
1604 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1605 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1606 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1607
1608 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1609
1610 /* Workaround shared GMAC reset */
1611 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1612 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1613 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1614
1615 /* Disable Force Sync bit and Enable Alloc bit */
1616 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1617 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1618
1619 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1620 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1621 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1622
1623 /* Reset the PCI FIFO of the async Tx queue */
1624 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1625 BMU_RST_SET | BMU_FIFO_RST);
1626
1627 /* Reset the Tx prefetch units */
1628 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1629 PREF_UNIT_RST_SET);
1630
1631 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1632
1633 sky2_rx_stop(sky2);
1634
1635 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1636 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1637
1638 sky2_phy_power(hw, port, 0);
1639
1640 netif_carrier_off(dev);
1641
1642 /* turn off LED's */
1643 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1644
1645 synchronize_irq(hw->pdev->irq);
1646
1647 sky2_tx_clean(dev);
1648 sky2_rx_clean(sky2);
1649
1650 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1651 sky2->rx_le, sky2->rx_le_map);
1652 kfree(sky2->rx_ring);
1653
1654 pci_free_consistent(hw->pdev,
1655 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1656 sky2->tx_le, sky2->tx_le_map);
1657 kfree(sky2->tx_ring);
1658
1659 sky2->tx_le = NULL;
1660 sky2->rx_le = NULL;
1661
1662 sky2->rx_ring = NULL;
1663 sky2->tx_ring = NULL;
1664
1665 return 0;
1666 }
1667
1668 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1669 {
1670 if (!sky2_is_copper(hw))
1671 return SPEED_1000;
1672
1673 if (hw->chip_id == CHIP_ID_YUKON_FE)
1674 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1675
1676 switch (aux & PHY_M_PS_SPEED_MSK) {
1677 case PHY_M_PS_SPEED_1000:
1678 return SPEED_1000;
1679 case PHY_M_PS_SPEED_100:
1680 return SPEED_100;
1681 default:
1682 return SPEED_10;
1683 }
1684 }
1685
1686 static void sky2_link_up(struct sky2_port *sky2)
1687 {
1688 struct sky2_hw *hw = sky2->hw;
1689 unsigned port = sky2->port;
1690 u16 reg;
1691 static const char *fc_name[] = {
1692 [FC_NONE] = "none",
1693 [FC_TX] = "tx",
1694 [FC_RX] = "rx",
1695 [FC_BOTH] = "both",
1696 };
1697
1698 /* enable Rx/Tx */
1699 reg = gma_read16(hw, port, GM_GP_CTRL);
1700 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1701 gma_write16(hw, port, GM_GP_CTRL, reg);
1702
1703 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1704
1705 netif_carrier_on(sky2->netdev);
1706
1707 mod_timer(&hw->watchdog_timer, jiffies + 1);
1708
1709 /* Turn on link LED */
1710 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1711 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1712
1713 if (hw->chip_id == CHIP_ID_YUKON_XL
1714 || hw->chip_id == CHIP_ID_YUKON_EC_U
1715 || hw->chip_id == CHIP_ID_YUKON_EX) {
1716 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1717 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1718
1719 switch(sky2->speed) {
1720 case SPEED_10:
1721 led |= PHY_M_LEDC_INIT_CTRL(7);
1722 break;
1723
1724 case SPEED_100:
1725 led |= PHY_M_LEDC_STA1_CTRL(7);
1726 break;
1727
1728 case SPEED_1000:
1729 led |= PHY_M_LEDC_STA0_CTRL(7);
1730 break;
1731 }
1732
1733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1734 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1735 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1736 }
1737
1738 if (netif_msg_link(sky2))
1739 printk(KERN_INFO PFX
1740 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1741 sky2->netdev->name, sky2->speed,
1742 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1743 fc_name[sky2->flow_status]);
1744 }
1745
1746 static void sky2_link_down(struct sky2_port *sky2)
1747 {
1748 struct sky2_hw *hw = sky2->hw;
1749 unsigned port = sky2->port;
1750 u16 reg;
1751
1752 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1753
1754 reg = gma_read16(hw, port, GM_GP_CTRL);
1755 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1756 gma_write16(hw, port, GM_GP_CTRL, reg);
1757
1758 netif_carrier_off(sky2->netdev);
1759
1760 /* Turn on link LED */
1761 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1762
1763 if (netif_msg_link(sky2))
1764 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1765
1766 sky2_phy_init(hw, port);
1767 }
1768
1769 static enum flow_control sky2_flow(int rx, int tx)
1770 {
1771 if (rx)
1772 return tx ? FC_BOTH : FC_RX;
1773 else
1774 return tx ? FC_TX : FC_NONE;
1775 }
1776
1777 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1778 {
1779 struct sky2_hw *hw = sky2->hw;
1780 unsigned port = sky2->port;
1781 u16 advert, lpa;
1782
1783 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1784 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1785 if (lpa & PHY_M_AN_RF) {
1786 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1787 return -1;
1788 }
1789
1790 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1791 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1792 sky2->netdev->name);
1793 return -1;
1794 }
1795
1796 sky2->speed = sky2_phy_speed(hw, aux);
1797 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1798
1799 /* Since the pause result bits seem to in different positions on
1800 * different chips. look at registers.
1801 */
1802 if (!sky2_is_copper(hw)) {
1803 /* Shift for bits in fiber PHY */
1804 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1805 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1806
1807 if (advert & ADVERTISE_1000XPAUSE)
1808 advert |= ADVERTISE_PAUSE_CAP;
1809 if (advert & ADVERTISE_1000XPSE_ASYM)
1810 advert |= ADVERTISE_PAUSE_ASYM;
1811 if (lpa & LPA_1000XPAUSE)
1812 lpa |= LPA_PAUSE_CAP;
1813 if (lpa & LPA_1000XPAUSE_ASYM)
1814 lpa |= LPA_PAUSE_ASYM;
1815 }
1816
1817 sky2->flow_status = FC_NONE;
1818 if (advert & ADVERTISE_PAUSE_CAP) {
1819 if (lpa & LPA_PAUSE_CAP)
1820 sky2->flow_status = FC_BOTH;
1821 else if (advert & ADVERTISE_PAUSE_ASYM)
1822 sky2->flow_status = FC_RX;
1823 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1824 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1825 sky2->flow_status = FC_TX;
1826 }
1827
1828 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1829 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1830 sky2->flow_status = FC_NONE;
1831
1832 if (sky2->flow_status & FC_TX)
1833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1834 else
1835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1836
1837 return 0;
1838 }
1839
1840 /* Interrupt from PHY */
1841 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1842 {
1843 struct net_device *dev = hw->dev[port];
1844 struct sky2_port *sky2 = netdev_priv(dev);
1845 u16 istatus, phystat;
1846
1847 if (!netif_running(dev))
1848 return;
1849
1850 spin_lock(&sky2->phy_lock);
1851 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1852 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1853
1854 if (netif_msg_intr(sky2))
1855 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1856 sky2->netdev->name, istatus, phystat);
1857
1858 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1859 if (sky2_autoneg_done(sky2, phystat) == 0)
1860 sky2_link_up(sky2);
1861 goto out;
1862 }
1863
1864 if (istatus & PHY_M_IS_LSP_CHANGE)
1865 sky2->speed = sky2_phy_speed(hw, phystat);
1866
1867 if (istatus & PHY_M_IS_DUP_CHANGE)
1868 sky2->duplex =
1869 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1870
1871 if (istatus & PHY_M_IS_LST_CHANGE) {
1872 if (phystat & PHY_M_PS_LINK_UP)
1873 sky2_link_up(sky2);
1874 else
1875 sky2_link_down(sky2);
1876 }
1877 out:
1878 spin_unlock(&sky2->phy_lock);
1879 }
1880
1881 /* Transmit timeout is only called if we are running, carrier is up
1882 * and tx queue is full (stopped).
1883 */
1884 static void sky2_tx_timeout(struct net_device *dev)
1885 {
1886 struct sky2_port *sky2 = netdev_priv(dev);
1887 struct sky2_hw *hw = sky2->hw;
1888
1889 if (netif_msg_timer(sky2))
1890 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1891
1892 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1893 dev->name, sky2->tx_cons, sky2->tx_prod,
1894 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1895 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1896
1897 /* can't restart safely under softirq */
1898 schedule_work(&hw->restart_work);
1899 }
1900
1901 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1902 {
1903 struct sky2_port *sky2 = netdev_priv(dev);
1904 struct sky2_hw *hw = sky2->hw;
1905 unsigned port = sky2->port;
1906 int err;
1907 u16 ctl, mode;
1908 u32 imask;
1909
1910 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1911 return -EINVAL;
1912
1913 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1914 return -EINVAL;
1915
1916 if (!netif_running(dev)) {
1917 dev->mtu = new_mtu;
1918 return 0;
1919 }
1920
1921 imask = sky2_read32(hw, B0_IMSK);
1922 sky2_write32(hw, B0_IMSK, 0);
1923
1924 dev->trans_start = jiffies; /* prevent tx timeout */
1925 netif_stop_queue(dev);
1926 netif_poll_disable(hw->dev[0]);
1927
1928 synchronize_irq(hw->pdev->irq);
1929
1930 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1931 if (new_mtu > ETH_DATA_LEN) {
1932 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1933 TX_JUMBO_ENA | TX_STFW_DIS);
1934 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1935 } else
1936 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1937 TX_JUMBO_DIS | TX_STFW_ENA);
1938 }
1939
1940 ctl = gma_read16(hw, port, GM_GP_CTRL);
1941 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1942 sky2_rx_stop(sky2);
1943 sky2_rx_clean(sky2);
1944
1945 dev->mtu = new_mtu;
1946
1947 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1948 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1949
1950 if (dev->mtu > ETH_DATA_LEN)
1951 mode |= GM_SMOD_JUMBO_ENA;
1952
1953 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1954
1955 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1956
1957 err = sky2_rx_start(sky2);
1958 sky2_write32(hw, B0_IMSK, imask);
1959
1960 if (err)
1961 dev_close(dev);
1962 else {
1963 gma_write16(hw, port, GM_GP_CTRL, ctl);
1964
1965 netif_poll_enable(hw->dev[0]);
1966 netif_wake_queue(dev);
1967 }
1968
1969 return err;
1970 }
1971
1972 /* For small just reuse existing skb for next receive */
1973 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1974 const struct rx_ring_info *re,
1975 unsigned length)
1976 {
1977 struct sk_buff *skb;
1978
1979 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1980 if (likely(skb)) {
1981 skb_reserve(skb, 2);
1982 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1983 length, PCI_DMA_FROMDEVICE);
1984 skb_copy_from_linear_data(re->skb, skb->data, length);
1985 skb->ip_summed = re->skb->ip_summed;
1986 skb->csum = re->skb->csum;
1987 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1988 length, PCI_DMA_FROMDEVICE);
1989 re->skb->ip_summed = CHECKSUM_NONE;
1990 skb_put(skb, length);
1991 }
1992 return skb;
1993 }
1994
1995 /* Adjust length of skb with fragments to match received data */
1996 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1997 unsigned int length)
1998 {
1999 int i, num_frags;
2000 unsigned int size;
2001
2002 /* put header into skb */
2003 size = min(length, hdr_space);
2004 skb->tail += size;
2005 skb->len += size;
2006 length -= size;
2007
2008 num_frags = skb_shinfo(skb)->nr_frags;
2009 for (i = 0; i < num_frags; i++) {
2010 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2011
2012 if (length == 0) {
2013 /* don't need this page */
2014 __free_page(frag->page);
2015 --skb_shinfo(skb)->nr_frags;
2016 } else {
2017 size = min(length, (unsigned) PAGE_SIZE);
2018
2019 frag->size = size;
2020 skb->data_len += size;
2021 skb->truesize += size;
2022 skb->len += size;
2023 length -= size;
2024 }
2025 }
2026 }
2027
2028 /* Normal packet - take skb from ring element and put in a new one */
2029 static struct sk_buff *receive_new(struct sky2_port *sky2,
2030 struct rx_ring_info *re,
2031 unsigned int length)
2032 {
2033 struct sk_buff *skb, *nskb;
2034 unsigned hdr_space = sky2->rx_data_size;
2035
2036 pr_debug(PFX "receive new length=%d\n", length);
2037
2038 /* Don't be tricky about reusing pages (yet) */
2039 nskb = sky2_rx_alloc(sky2);
2040 if (unlikely(!nskb))
2041 return NULL;
2042
2043 skb = re->skb;
2044 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2045
2046 prefetch(skb->data);
2047 re->skb = nskb;
2048 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2049
2050 if (skb_shinfo(skb)->nr_frags)
2051 skb_put_frags(skb, hdr_space, length);
2052 else
2053 skb_put(skb, length);
2054 return skb;
2055 }
2056
2057 /*
2058 * Receive one packet.
2059 * For larger packets, get new buffer.
2060 */
2061 static struct sk_buff *sky2_receive(struct net_device *dev,
2062 u16 length, u32 status)
2063 {
2064 struct sky2_port *sky2 = netdev_priv(dev);
2065 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2066 struct sk_buff *skb = NULL;
2067 u16 count;
2068
2069 if (unlikely(netif_msg_rx_status(sky2)))
2070 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2071 dev->name, sky2->rx_next, status, length);
2072
2073 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2074 prefetch(sky2->rx_ring + sky2->rx_next);
2075
2076 if (status & GMR_FS_ANY_ERR)
2077 goto error;
2078
2079 if (!(status & GMR_FS_RX_OK))
2080 goto resubmit;
2081
2082 count = (status & GMR_FS_LEN) >> 16;
2083 #ifdef SKY2_VLAN_TAG_USED
2084 /* Account for vlan tag */
2085 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2086 count -= VLAN_HLEN;
2087 #endif
2088 if (count != length)
2089 goto len_mismatch;
2090
2091 if (length < copybreak)
2092 skb = receive_copy(sky2, re, length);
2093 else
2094 skb = receive_new(sky2, re, length);
2095 resubmit:
2096 sky2_rx_submit(sky2, re);
2097
2098 return skb;
2099
2100 len_mismatch:
2101 /* Truncation of overlength packets
2102 causes PHY length to not match MAC length */
2103 ++sky2->net_stats.rx_length_errors;
2104
2105 error:
2106 ++sky2->net_stats.rx_errors;
2107 if (status & GMR_FS_RX_FF_OV) {
2108 sky2->net_stats.rx_over_errors++;
2109 goto resubmit;
2110 }
2111
2112 if (netif_msg_rx_err(sky2) && net_ratelimit())
2113 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2114 dev->name, status, length);
2115
2116 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2117 sky2->net_stats.rx_length_errors++;
2118 if (status & GMR_FS_FRAGMENT)
2119 sky2->net_stats.rx_frame_errors++;
2120 if (status & GMR_FS_CRC_ERR)
2121 sky2->net_stats.rx_crc_errors++;
2122
2123 goto resubmit;
2124 }
2125
2126 /* Transmit complete */
2127 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2128 {
2129 struct sky2_port *sky2 = netdev_priv(dev);
2130
2131 if (netif_running(dev)) {
2132 netif_tx_lock(dev);
2133 sky2_tx_complete(sky2, last);
2134 netif_tx_unlock(dev);
2135 }
2136 }
2137
2138 /* Process status response ring */
2139 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2140 {
2141 struct sky2_port *sky2;
2142 int work_done = 0;
2143 unsigned buf_write[2] = { 0, 0 };
2144 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2145
2146 rmb();
2147
2148 while (hw->st_idx != hwidx) {
2149 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2150 struct net_device *dev;
2151 struct sk_buff *skb;
2152 u32 status;
2153 u16 length;
2154
2155 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2156
2157 BUG_ON(le->link >= 2);
2158 dev = hw->dev[le->link];
2159
2160 sky2 = netdev_priv(dev);
2161 length = le16_to_cpu(le->length);
2162 status = le32_to_cpu(le->status);
2163
2164 switch (le->opcode & ~HW_OWNER) {
2165 case OP_RXSTAT:
2166 skb = sky2_receive(dev, length, status);
2167 if (unlikely(!skb)) {
2168 sky2->net_stats.rx_dropped++;
2169 goto force_update;
2170 }
2171
2172 skb->protocol = eth_type_trans(skb, dev);
2173 sky2->net_stats.rx_packets++;
2174 sky2->net_stats.rx_bytes += skb->len;
2175 dev->last_rx = jiffies;
2176
2177 #ifdef SKY2_VLAN_TAG_USED
2178 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2179 vlan_hwaccel_receive_skb(skb,
2180 sky2->vlgrp,
2181 be16_to_cpu(sky2->rx_tag));
2182 } else
2183 #endif
2184 netif_receive_skb(skb);
2185
2186 /* Update receiver after 16 frames */
2187 if (++buf_write[le->link] == RX_BUF_WRITE) {
2188 force_update:
2189 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2190 buf_write[le->link] = 0;
2191 }
2192
2193 /* Stop after net poll weight */
2194 if (++work_done >= to_do)
2195 goto exit_loop;
2196 break;
2197
2198 #ifdef SKY2_VLAN_TAG_USED
2199 case OP_RXVLAN:
2200 sky2->rx_tag = length;
2201 break;
2202
2203 case OP_RXCHKSVLAN:
2204 sky2->rx_tag = length;
2205 /* fall through */
2206 #endif
2207 case OP_RXCHKS:
2208 if (!sky2->rx_csum)
2209 break;
2210
2211 /* Both checksum counters are programmed to start at
2212 * the same offset, so unless there is a problem they
2213 * should match. This failure is an early indication that
2214 * hardware receive checksumming won't work.
2215 */
2216 if (likely(status >> 16 == (status & 0xffff))) {
2217 skb = sky2->rx_ring[sky2->rx_next].skb;
2218 skb->ip_summed = CHECKSUM_COMPLETE;
2219 skb->csum = status & 0xffff;
2220 } else {
2221 printk(KERN_NOTICE PFX "%s: hardware receive "
2222 "checksum problem (status = %#x)\n",
2223 dev->name, status);
2224 sky2->rx_csum = 0;
2225 sky2_write32(sky2->hw,
2226 Q_ADDR(rxqaddr[le->link], Q_CSR),
2227 BMU_DIS_RX_CHKSUM);
2228 }
2229 break;
2230
2231 case OP_TXINDEXLE:
2232 /* TX index reports status for both ports */
2233 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2234 sky2_tx_done(hw->dev[0], status & 0xfff);
2235 if (hw->dev[1])
2236 sky2_tx_done(hw->dev[1],
2237 ((status >> 24) & 0xff)
2238 | (u16)(length & 0xf) << 8);
2239 break;
2240
2241 default:
2242 if (net_ratelimit())
2243 printk(KERN_WARNING PFX
2244 "unknown status opcode 0x%x\n", le->opcode);
2245 goto exit_loop;
2246 }
2247 }
2248
2249 /* Fully processed status ring so clear irq */
2250 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2251 mmiowb();
2252
2253 exit_loop:
2254 if (buf_write[0]) {
2255 sky2 = netdev_priv(hw->dev[0]);
2256 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2257 }
2258
2259 if (buf_write[1]) {
2260 sky2 = netdev_priv(hw->dev[1]);
2261 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2262 }
2263
2264 return work_done;
2265 }
2266
2267 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2268 {
2269 struct net_device *dev = hw->dev[port];
2270
2271 if (net_ratelimit())
2272 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2273 dev->name, status);
2274
2275 if (status & Y2_IS_PAR_RD1) {
2276 if (net_ratelimit())
2277 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2278 dev->name);
2279 /* Clear IRQ */
2280 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2281 }
2282
2283 if (status & Y2_IS_PAR_WR1) {
2284 if (net_ratelimit())
2285 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2286 dev->name);
2287
2288 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2289 }
2290
2291 if (status & Y2_IS_PAR_MAC1) {
2292 if (net_ratelimit())
2293 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2294 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2295 }
2296
2297 if (status & Y2_IS_PAR_RX1) {
2298 if (net_ratelimit())
2299 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2300 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2301 }
2302
2303 if (status & Y2_IS_TCP_TXA1) {
2304 if (net_ratelimit())
2305 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2306 dev->name);
2307 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2308 }
2309 }
2310
2311 static void sky2_hw_intr(struct sky2_hw *hw)
2312 {
2313 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2314
2315 if (status & Y2_IS_TIST_OV)
2316 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2317
2318 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2319 u16 pci_err;
2320
2321 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2322 if (net_ratelimit())
2323 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2324 pci_err);
2325
2326 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2327 sky2_pci_write16(hw, PCI_STATUS,
2328 pci_err | PCI_STATUS_ERROR_BITS);
2329 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2330 }
2331
2332 if (status & Y2_IS_PCI_EXP) {
2333 /* PCI-Express uncorrectable Error occurred */
2334 u32 pex_err;
2335
2336 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2337
2338 if (net_ratelimit())
2339 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2340 pex_err);
2341
2342 /* clear the interrupt */
2343 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2344 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2345 0xffffffffUL);
2346 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2347
2348 if (pex_err & PEX_FATAL_ERRORS) {
2349 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2350 hwmsk &= ~Y2_IS_PCI_EXP;
2351 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2352 }
2353 }
2354
2355 if (status & Y2_HWE_L1_MASK)
2356 sky2_hw_error(hw, 0, status);
2357 status >>= 8;
2358 if (status & Y2_HWE_L1_MASK)
2359 sky2_hw_error(hw, 1, status);
2360 }
2361
2362 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2363 {
2364 struct net_device *dev = hw->dev[port];
2365 struct sky2_port *sky2 = netdev_priv(dev);
2366 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2367
2368 if (netif_msg_intr(sky2))
2369 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2370 dev->name, status);
2371
2372 if (status & GM_IS_RX_CO_OV)
2373 gma_read16(hw, port, GM_RX_IRQ_SRC);
2374
2375 if (status & GM_IS_TX_CO_OV)
2376 gma_read16(hw, port, GM_TX_IRQ_SRC);
2377
2378 if (status & GM_IS_RX_FF_OR) {
2379 ++sky2->net_stats.rx_fifo_errors;
2380 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2381 }
2382
2383 if (status & GM_IS_TX_FF_UR) {
2384 ++sky2->net_stats.tx_fifo_errors;
2385 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2386 }
2387 }
2388
2389 /* This should never happen it is a bug. */
2390 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2391 u16 q, unsigned ring_size)
2392 {
2393 struct net_device *dev = hw->dev[port];
2394 struct sky2_port *sky2 = netdev_priv(dev);
2395 unsigned idx;
2396 const u64 *le = (q == Q_R1 || q == Q_R2)
2397 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2398
2399 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2400 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2401 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2402 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2403
2404 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2405 }
2406
2407 /* Force a fake soft NAPI poll to handle lost IRQ's */
2408 static void sky2_watchdog(unsigned long arg)
2409 {
2410 struct sky2_hw *hw = (struct sky2_hw *) arg;
2411 struct net_device *dev = hw->dev[0];
2412 int i, active = 0;
2413
2414 if (__netif_rx_schedule_prep(dev))
2415 __netif_rx_schedule(dev);
2416
2417 for (i = 0; i < hw->ports; i++) {
2418 dev = hw->dev[i];
2419 if (!netif_running(dev))
2420 continue;
2421 ++active;
2422 }
2423
2424 if (active)
2425 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2426 }
2427
2428 /* Hardware/software error handling */
2429 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2430 {
2431 if (net_ratelimit())
2432 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2433
2434 if (status & Y2_IS_HW_ERR)
2435 sky2_hw_intr(hw);
2436
2437 if (status & Y2_IS_IRQ_MAC1)
2438 sky2_mac_intr(hw, 0);
2439
2440 if (status & Y2_IS_IRQ_MAC2)
2441 sky2_mac_intr(hw, 1);
2442
2443 if (status & Y2_IS_CHK_RX1)
2444 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2445
2446 if (status & Y2_IS_CHK_RX2)
2447 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2448
2449 if (status & Y2_IS_CHK_TXA1)
2450 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2451
2452 if (status & Y2_IS_CHK_TXA2)
2453 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2454 }
2455
2456 static int sky2_poll(struct net_device *dev0, int *budget)
2457 {
2458 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2459 int work_done;
2460 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2461
2462 if (unlikely(status & Y2_IS_ERROR))
2463 sky2_err_intr(hw, status);
2464
2465 if (status & Y2_IS_IRQ_PHY1)
2466 sky2_phy_intr(hw, 0);
2467
2468 if (status & Y2_IS_IRQ_PHY2)
2469 sky2_phy_intr(hw, 1);
2470
2471 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2472 *budget -= work_done;
2473 dev0->quota -= work_done;
2474
2475 /* More work? */
2476 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
2477 return 1;
2478
2479 /* Bug/Errata workaround?
2480 * Need to kick the TX irq moderation timer.
2481 */
2482 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2483 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2484 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2485 }
2486 netif_rx_complete(dev0);
2487
2488 sky2_read32(hw, B0_Y2_SP_LISR);
2489 return 0;
2490 }
2491
2492 static irqreturn_t sky2_intr(int irq, void *dev_id)
2493 {
2494 struct sky2_hw *hw = dev_id;
2495 struct net_device *dev0 = hw->dev[0];
2496 u32 status;
2497
2498 /* Reading this mask interrupts as side effect */
2499 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2500 if (status == 0 || status == ~0)
2501 return IRQ_NONE;
2502
2503 prefetch(&hw->st_le[hw->st_idx]);
2504 if (likely(__netif_rx_schedule_prep(dev0)))
2505 __netif_rx_schedule(dev0);
2506
2507 return IRQ_HANDLED;
2508 }
2509
2510 #ifdef CONFIG_NET_POLL_CONTROLLER
2511 static void sky2_netpoll(struct net_device *dev)
2512 {
2513 struct sky2_port *sky2 = netdev_priv(dev);
2514 struct net_device *dev0 = sky2->hw->dev[0];
2515
2516 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2517 __netif_rx_schedule(dev0);
2518 }
2519 #endif
2520
2521 /* Chip internal frequency for clock calculations */
2522 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2523 {
2524 switch (hw->chip_id) {
2525 case CHIP_ID_YUKON_EC:
2526 case CHIP_ID_YUKON_EC_U:
2527 case CHIP_ID_YUKON_EX:
2528 return 125; /* 125 Mhz */
2529 case CHIP_ID_YUKON_FE:
2530 return 100; /* 100 Mhz */
2531 default: /* YUKON_XL */
2532 return 156; /* 156 Mhz */
2533 }
2534 }
2535
2536 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2537 {
2538 return sky2_mhz(hw) * us;
2539 }
2540
2541 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2542 {
2543 return clk / sky2_mhz(hw);
2544 }
2545
2546
2547 static int __devinit sky2_init(struct sky2_hw *hw)
2548 {
2549 u8 t8;
2550
2551 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2552
2553 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2554 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2555 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2556 hw->chip_id);
2557 return -EOPNOTSUPP;
2558 }
2559
2560 if (hw->chip_id == CHIP_ID_YUKON_EX)
2561 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2562 "Please report success or failure to <netdev@vger.kernel.org>\n");
2563
2564 /* Make sure and enable all clocks */
2565 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2566 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2567
2568 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2569
2570 /* This rev is really old, and requires untested workarounds */
2571 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2572 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2573 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2574 hw->chip_id, hw->chip_rev);
2575 return -EOPNOTSUPP;
2576 }
2577
2578 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2579 hw->ports = 1;
2580 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2581 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2582 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2583 ++hw->ports;
2584 }
2585
2586 return 0;
2587 }
2588
2589 static void sky2_reset(struct sky2_hw *hw)
2590 {
2591 u16 status;
2592 int i;
2593
2594 /* disable ASF */
2595 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2596 status = sky2_read16(hw, HCU_CCSR);
2597 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2598 HCU_CCSR_UC_STATE_MSK);
2599 sky2_write16(hw, HCU_CCSR, status);
2600 } else
2601 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2602 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2603
2604 /* do a SW reset */
2605 sky2_write8(hw, B0_CTST, CS_RST_SET);
2606 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2607
2608 /* clear PCI errors, if any */
2609 status = sky2_pci_read16(hw, PCI_STATUS);
2610
2611 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2612 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2613
2614
2615 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2616
2617 /* clear any PEX errors */
2618 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2619 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2620
2621
2622 sky2_power_on(hw);
2623
2624 for (i = 0; i < hw->ports; i++) {
2625 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2626 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2627 }
2628
2629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2630
2631 /* Clear I2C IRQ noise */
2632 sky2_write32(hw, B2_I2C_IRQ, 1);
2633
2634 /* turn off hardware timer (unused) */
2635 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2636 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2637
2638 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2639
2640 /* Turn off descriptor polling */
2641 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2642
2643 /* Turn off receive timestamp */
2644 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2645 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2646
2647 /* enable the Tx Arbiters */
2648 for (i = 0; i < hw->ports; i++)
2649 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2650
2651 /* Initialize ram interface */
2652 for (i = 0; i < hw->ports; i++) {
2653 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2654
2655 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2656 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2657 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2658 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2659 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2660 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2661 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2662 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2663 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2664 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2665 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2666 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2667 }
2668
2669 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2670
2671 for (i = 0; i < hw->ports; i++)
2672 sky2_gmac_reset(hw, i);
2673
2674 memset(hw->st_le, 0, STATUS_LE_BYTES);
2675 hw->st_idx = 0;
2676
2677 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2678 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2679
2680 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2681 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2682
2683 /* Set the list last index */
2684 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2685
2686 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2687 sky2_write8(hw, STAT_FIFO_WM, 16);
2688
2689 /* set Status-FIFO ISR watermark */
2690 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2691 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2692 else
2693 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2694
2695 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2696 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2697 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2698
2699 /* enable status unit */
2700 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2701
2702 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2703 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2704 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2705 }
2706
2707 static void sky2_restart(struct work_struct *work)
2708 {
2709 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2710 struct net_device *dev;
2711 int i, err;
2712
2713 dev_dbg(&hw->pdev->dev, "restarting\n");
2714
2715 rtnl_lock();
2716 sky2_write32(hw, B0_IMSK, 0);
2717 sky2_read32(hw, B0_IMSK);
2718
2719 netif_poll_disable(hw->dev[0]);
2720
2721 for (i = 0; i < hw->ports; i++) {
2722 dev = hw->dev[i];
2723 if (netif_running(dev))
2724 sky2_down(dev);
2725 }
2726
2727 sky2_reset(hw);
2728 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2729 netif_poll_enable(hw->dev[0]);
2730
2731 for (i = 0; i < hw->ports; i++) {
2732 dev = hw->dev[i];
2733 if (netif_running(dev)) {
2734 err = sky2_up(dev);
2735 if (err) {
2736 printk(KERN_INFO PFX "%s: could not restart %d\n",
2737 dev->name, err);
2738 dev_close(dev);
2739 }
2740 }
2741 }
2742
2743 rtnl_unlock();
2744 }
2745
2746 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2747 {
2748 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2749 }
2750
2751 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2752 {
2753 const struct sky2_port *sky2 = netdev_priv(dev);
2754
2755 wol->supported = sky2_wol_supported(sky2->hw);
2756 wol->wolopts = sky2->wol;
2757 }
2758
2759 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2760 {
2761 struct sky2_port *sky2 = netdev_priv(dev);
2762 struct sky2_hw *hw = sky2->hw;
2763
2764 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2765 return -EOPNOTSUPP;
2766
2767 sky2->wol = wol->wolopts;
2768
2769 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2770 sky2_write32(hw, B0_CTST, sky2->wol
2771 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2772
2773 if (!netif_running(dev))
2774 sky2_wol_init(sky2);
2775 return 0;
2776 }
2777
2778 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2779 {
2780 if (sky2_is_copper(hw)) {
2781 u32 modes = SUPPORTED_10baseT_Half
2782 | SUPPORTED_10baseT_Full
2783 | SUPPORTED_100baseT_Half
2784 | SUPPORTED_100baseT_Full
2785 | SUPPORTED_Autoneg | SUPPORTED_TP;
2786
2787 if (hw->chip_id != CHIP_ID_YUKON_FE)
2788 modes |= SUPPORTED_1000baseT_Half
2789 | SUPPORTED_1000baseT_Full;
2790 return modes;
2791 } else
2792 return SUPPORTED_1000baseT_Half
2793 | SUPPORTED_1000baseT_Full
2794 | SUPPORTED_Autoneg
2795 | SUPPORTED_FIBRE;
2796 }
2797
2798 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2799 {
2800 struct sky2_port *sky2 = netdev_priv(dev);
2801 struct sky2_hw *hw = sky2->hw;
2802
2803 ecmd->transceiver = XCVR_INTERNAL;
2804 ecmd->supported = sky2_supported_modes(hw);
2805 ecmd->phy_address = PHY_ADDR_MARV;
2806 if (sky2_is_copper(hw)) {
2807 ecmd->supported = SUPPORTED_10baseT_Half
2808 | SUPPORTED_10baseT_Full
2809 | SUPPORTED_100baseT_Half
2810 | SUPPORTED_100baseT_Full
2811 | SUPPORTED_1000baseT_Half
2812 | SUPPORTED_1000baseT_Full
2813 | SUPPORTED_Autoneg | SUPPORTED_TP;
2814 ecmd->port = PORT_TP;
2815 ecmd->speed = sky2->speed;
2816 } else {
2817 ecmd->speed = SPEED_1000;
2818 ecmd->port = PORT_FIBRE;
2819 }
2820
2821 ecmd->advertising = sky2->advertising;
2822 ecmd->autoneg = sky2->autoneg;
2823 ecmd->duplex = sky2->duplex;
2824 return 0;
2825 }
2826
2827 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2828 {
2829 struct sky2_port *sky2 = netdev_priv(dev);
2830 const struct sky2_hw *hw = sky2->hw;
2831 u32 supported = sky2_supported_modes(hw);
2832
2833 if (ecmd->autoneg == AUTONEG_ENABLE) {
2834 ecmd->advertising = supported;
2835 sky2->duplex = -1;
2836 sky2->speed = -1;
2837 } else {
2838 u32 setting;
2839
2840 switch (ecmd->speed) {
2841 case SPEED_1000:
2842 if (ecmd->duplex == DUPLEX_FULL)
2843 setting = SUPPORTED_1000baseT_Full;
2844 else if (ecmd->duplex == DUPLEX_HALF)
2845 setting = SUPPORTED_1000baseT_Half;
2846 else
2847 return -EINVAL;
2848 break;
2849 case SPEED_100:
2850 if (ecmd->duplex == DUPLEX_FULL)
2851 setting = SUPPORTED_100baseT_Full;
2852 else if (ecmd->duplex == DUPLEX_HALF)
2853 setting = SUPPORTED_100baseT_Half;
2854 else
2855 return -EINVAL;
2856 break;
2857
2858 case SPEED_10:
2859 if (ecmd->duplex == DUPLEX_FULL)
2860 setting = SUPPORTED_10baseT_Full;
2861 else if (ecmd->duplex == DUPLEX_HALF)
2862 setting = SUPPORTED_10baseT_Half;
2863 else
2864 return -EINVAL;
2865 break;
2866 default:
2867 return -EINVAL;
2868 }
2869
2870 if ((setting & supported) == 0)
2871 return -EINVAL;
2872
2873 sky2->speed = ecmd->speed;
2874 sky2->duplex = ecmd->duplex;
2875 }
2876
2877 sky2->autoneg = ecmd->autoneg;
2878 sky2->advertising = ecmd->advertising;
2879
2880 if (netif_running(dev))
2881 sky2_phy_reinit(sky2);
2882
2883 return 0;
2884 }
2885
2886 static void sky2_get_drvinfo(struct net_device *dev,
2887 struct ethtool_drvinfo *info)
2888 {
2889 struct sky2_port *sky2 = netdev_priv(dev);
2890
2891 strcpy(info->driver, DRV_NAME);
2892 strcpy(info->version, DRV_VERSION);
2893 strcpy(info->fw_version, "N/A");
2894 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2895 }
2896
2897 static const struct sky2_stat {
2898 char name[ETH_GSTRING_LEN];
2899 u16 offset;
2900 } sky2_stats[] = {
2901 { "tx_bytes", GM_TXO_OK_HI },
2902 { "rx_bytes", GM_RXO_OK_HI },
2903 { "tx_broadcast", GM_TXF_BC_OK },
2904 { "rx_broadcast", GM_RXF_BC_OK },
2905 { "tx_multicast", GM_TXF_MC_OK },
2906 { "rx_multicast", GM_RXF_MC_OK },
2907 { "tx_unicast", GM_TXF_UC_OK },
2908 { "rx_unicast", GM_RXF_UC_OK },
2909 { "tx_mac_pause", GM_TXF_MPAUSE },
2910 { "rx_mac_pause", GM_RXF_MPAUSE },
2911 { "collisions", GM_TXF_COL },
2912 { "late_collision",GM_TXF_LAT_COL },
2913 { "aborted", GM_TXF_ABO_COL },
2914 { "single_collisions", GM_TXF_SNG_COL },
2915 { "multi_collisions", GM_TXF_MUL_COL },
2916
2917 { "rx_short", GM_RXF_SHT },
2918 { "rx_runt", GM_RXE_FRAG },
2919 { "rx_64_byte_packets", GM_RXF_64B },
2920 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2921 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2922 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2923 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2924 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2925 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2926 { "rx_too_long", GM_RXF_LNG_ERR },
2927 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2928 { "rx_jabber", GM_RXF_JAB_PKT },
2929 { "rx_fcs_error", GM_RXF_FCS_ERR },
2930
2931 { "tx_64_byte_packets", GM_TXF_64B },
2932 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2933 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2934 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2935 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2936 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2937 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2938 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2939 };
2940
2941 static u32 sky2_get_rx_csum(struct net_device *dev)
2942 {
2943 struct sky2_port *sky2 = netdev_priv(dev);
2944
2945 return sky2->rx_csum;
2946 }
2947
2948 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2949 {
2950 struct sky2_port *sky2 = netdev_priv(dev);
2951
2952 sky2->rx_csum = data;
2953
2954 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2955 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2956
2957 return 0;
2958 }
2959
2960 static u32 sky2_get_msglevel(struct net_device *netdev)
2961 {
2962 struct sky2_port *sky2 = netdev_priv(netdev);
2963 return sky2->msg_enable;
2964 }
2965
2966 static int sky2_nway_reset(struct net_device *dev)
2967 {
2968 struct sky2_port *sky2 = netdev_priv(dev);
2969
2970 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2971 return -EINVAL;
2972
2973 sky2_phy_reinit(sky2);
2974
2975 return 0;
2976 }
2977
2978 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2979 {
2980 struct sky2_hw *hw = sky2->hw;
2981 unsigned port = sky2->port;
2982 int i;
2983
2984 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2985 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2986 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2987 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2988
2989 for (i = 2; i < count; i++)
2990 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2991 }
2992
2993 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2994 {
2995 struct sky2_port *sky2 = netdev_priv(netdev);
2996 sky2->msg_enable = value;
2997 }
2998
2999 static int sky2_get_stats_count(struct net_device *dev)
3000 {
3001 return ARRAY_SIZE(sky2_stats);
3002 }
3003
3004 static void sky2_get_ethtool_stats(struct net_device *dev,
3005 struct ethtool_stats *stats, u64 * data)
3006 {
3007 struct sky2_port *sky2 = netdev_priv(dev);
3008
3009 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3010 }
3011
3012 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3013 {
3014 int i;
3015
3016 switch (stringset) {
3017 case ETH_SS_STATS:
3018 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3019 memcpy(data + i * ETH_GSTRING_LEN,
3020 sky2_stats[i].name, ETH_GSTRING_LEN);
3021 break;
3022 }
3023 }
3024
3025 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3026 {
3027 struct sky2_port *sky2 = netdev_priv(dev);
3028 return &sky2->net_stats;
3029 }
3030
3031 static int sky2_set_mac_address(struct net_device *dev, void *p)
3032 {
3033 struct sky2_port *sky2 = netdev_priv(dev);
3034 struct sky2_hw *hw = sky2->hw;
3035 unsigned port = sky2->port;
3036 const struct sockaddr *addr = p;
3037
3038 if (!is_valid_ether_addr(addr->sa_data))
3039 return -EADDRNOTAVAIL;
3040
3041 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3042 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3043 dev->dev_addr, ETH_ALEN);
3044 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3045 dev->dev_addr, ETH_ALEN);
3046
3047 /* virtual address for data */
3048 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3049
3050 /* physical address: used for pause frames */
3051 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3052
3053 return 0;
3054 }
3055
3056 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3057 {
3058 u32 bit;
3059
3060 bit = ether_crc(ETH_ALEN, addr) & 63;
3061 filter[bit >> 3] |= 1 << (bit & 7);
3062 }
3063
3064 static void sky2_set_multicast(struct net_device *dev)
3065 {
3066 struct sky2_port *sky2 = netdev_priv(dev);
3067 struct sky2_hw *hw = sky2->hw;
3068 unsigned port = sky2->port;
3069 struct dev_mc_list *list = dev->mc_list;
3070 u16 reg;
3071 u8 filter[8];
3072 int rx_pause;
3073 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3074
3075 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3076 memset(filter, 0, sizeof(filter));
3077
3078 reg = gma_read16(hw, port, GM_RX_CTRL);
3079 reg |= GM_RXCR_UCF_ENA;
3080
3081 if (dev->flags & IFF_PROMISC) /* promiscuous */
3082 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3083 else if (dev->flags & IFF_ALLMULTI)
3084 memset(filter, 0xff, sizeof(filter));
3085 else if (dev->mc_count == 0 && !rx_pause)
3086 reg &= ~GM_RXCR_MCF_ENA;
3087 else {
3088 int i;
3089 reg |= GM_RXCR_MCF_ENA;
3090
3091 if (rx_pause)
3092 sky2_add_filter(filter, pause_mc_addr);
3093
3094 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3095 sky2_add_filter(filter, list->dmi_addr);
3096 }
3097
3098 gma_write16(hw, port, GM_MC_ADDR_H1,
3099 (u16) filter[0] | ((u16) filter[1] << 8));
3100 gma_write16(hw, port, GM_MC_ADDR_H2,
3101 (u16) filter[2] | ((u16) filter[3] << 8));
3102 gma_write16(hw, port, GM_MC_ADDR_H3,
3103 (u16) filter[4] | ((u16) filter[5] << 8));
3104 gma_write16(hw, port, GM_MC_ADDR_H4,
3105 (u16) filter[6] | ((u16) filter[7] << 8));
3106
3107 gma_write16(hw, port, GM_RX_CTRL, reg);
3108 }
3109
3110 /* Can have one global because blinking is controlled by
3111 * ethtool and that is always under RTNL mutex
3112 */
3113 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3114 {
3115 u16 pg;
3116
3117 switch (hw->chip_id) {
3118 case CHIP_ID_YUKON_XL:
3119 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3120 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3121 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3122 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3123 PHY_M_LEDC_INIT_CTRL(7) |
3124 PHY_M_LEDC_STA1_CTRL(7) |
3125 PHY_M_LEDC_STA0_CTRL(7))
3126 : 0);
3127
3128 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3129 break;
3130
3131 default:
3132 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3133 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3134 on ? PHY_M_LED_ALL : 0);
3135 }
3136 }
3137
3138 /* blink LED's for finding board */
3139 static int sky2_phys_id(struct net_device *dev, u32 data)
3140 {
3141 struct sky2_port *sky2 = netdev_priv(dev);
3142 struct sky2_hw *hw = sky2->hw;
3143 unsigned port = sky2->port;
3144 u16 ledctrl, ledover = 0;
3145 long ms;
3146 int interrupted;
3147 int onoff = 1;
3148
3149 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3150 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3151 else
3152 ms = data * 1000;
3153
3154 /* save initial values */
3155 spin_lock_bh(&sky2->phy_lock);
3156 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3157 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3158 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3159 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3160 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3161 } else {
3162 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3163 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3164 }
3165
3166 interrupted = 0;
3167 while (!interrupted && ms > 0) {
3168 sky2_led(hw, port, onoff);
3169 onoff = !onoff;
3170
3171 spin_unlock_bh(&sky2->phy_lock);
3172 interrupted = msleep_interruptible(250);
3173 spin_lock_bh(&sky2->phy_lock);
3174
3175 ms -= 250;
3176 }
3177
3178 /* resume regularly scheduled programming */
3179 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3180 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3181 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3182 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3183 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3184 } else {
3185 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3186 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3187 }
3188 spin_unlock_bh(&sky2->phy_lock);
3189
3190 return 0;
3191 }
3192
3193 static void sky2_get_pauseparam(struct net_device *dev,
3194 struct ethtool_pauseparam *ecmd)
3195 {
3196 struct sky2_port *sky2 = netdev_priv(dev);
3197
3198 switch (sky2->flow_mode) {
3199 case FC_NONE:
3200 ecmd->tx_pause = ecmd->rx_pause = 0;
3201 break;
3202 case FC_TX:
3203 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3204 break;
3205 case FC_RX:
3206 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3207 break;
3208 case FC_BOTH:
3209 ecmd->tx_pause = ecmd->rx_pause = 1;
3210 }
3211
3212 ecmd->autoneg = sky2->autoneg;
3213 }
3214
3215 static int sky2_set_pauseparam(struct net_device *dev,
3216 struct ethtool_pauseparam *ecmd)
3217 {
3218 struct sky2_port *sky2 = netdev_priv(dev);
3219
3220 sky2->autoneg = ecmd->autoneg;
3221 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3222
3223 if (netif_running(dev))
3224 sky2_phy_reinit(sky2);
3225
3226 return 0;
3227 }
3228
3229 static int sky2_get_coalesce(struct net_device *dev,
3230 struct ethtool_coalesce *ecmd)
3231 {
3232 struct sky2_port *sky2 = netdev_priv(dev);
3233 struct sky2_hw *hw = sky2->hw;
3234
3235 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3236 ecmd->tx_coalesce_usecs = 0;
3237 else {
3238 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3239 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3240 }
3241 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3242
3243 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3244 ecmd->rx_coalesce_usecs = 0;
3245 else {
3246 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3247 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3248 }
3249 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3250
3251 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3252 ecmd->rx_coalesce_usecs_irq = 0;
3253 else {
3254 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3255 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3256 }
3257
3258 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3259
3260 return 0;
3261 }
3262
3263 /* Note: this affect both ports */
3264 static int sky2_set_coalesce(struct net_device *dev,
3265 struct ethtool_coalesce *ecmd)
3266 {
3267 struct sky2_port *sky2 = netdev_priv(dev);
3268 struct sky2_hw *hw = sky2->hw;
3269 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3270
3271 if (ecmd->tx_coalesce_usecs > tmax ||
3272 ecmd->rx_coalesce_usecs > tmax ||
3273 ecmd->rx_coalesce_usecs_irq > tmax)
3274 return -EINVAL;
3275
3276 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3277 return -EINVAL;
3278 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3279 return -EINVAL;
3280 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3281 return -EINVAL;
3282
3283 if (ecmd->tx_coalesce_usecs == 0)
3284 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3285 else {
3286 sky2_write32(hw, STAT_TX_TIMER_INI,
3287 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3288 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3289 }
3290 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3291
3292 if (ecmd->rx_coalesce_usecs == 0)
3293 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3294 else {
3295 sky2_write32(hw, STAT_LEV_TIMER_INI,
3296 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3297 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3298 }
3299 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3300
3301 if (ecmd->rx_coalesce_usecs_irq == 0)
3302 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3303 else {
3304 sky2_write32(hw, STAT_ISR_TIMER_INI,
3305 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3306 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3307 }
3308 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3309 return 0;
3310 }
3311
3312 static void sky2_get_ringparam(struct net_device *dev,
3313 struct ethtool_ringparam *ering)
3314 {
3315 struct sky2_port *sky2 = netdev_priv(dev);
3316
3317 ering->rx_max_pending = RX_MAX_PENDING;
3318 ering->rx_mini_max_pending = 0;
3319 ering->rx_jumbo_max_pending = 0;
3320 ering->tx_max_pending = TX_RING_SIZE - 1;
3321
3322 ering->rx_pending = sky2->rx_pending;
3323 ering->rx_mini_pending = 0;
3324 ering->rx_jumbo_pending = 0;
3325 ering->tx_pending = sky2->tx_pending;
3326 }
3327
3328 static int sky2_set_ringparam(struct net_device *dev,
3329 struct ethtool_ringparam *ering)
3330 {
3331 struct sky2_port *sky2 = netdev_priv(dev);
3332 int err = 0;
3333
3334 if (ering->rx_pending > RX_MAX_PENDING ||
3335 ering->rx_pending < 8 ||
3336 ering->tx_pending < MAX_SKB_TX_LE ||
3337 ering->tx_pending > TX_RING_SIZE - 1)
3338 return -EINVAL;
3339
3340 if (netif_running(dev))
3341 sky2_down(dev);
3342
3343 sky2->rx_pending = ering->rx_pending;
3344 sky2->tx_pending = ering->tx_pending;
3345
3346 if (netif_running(dev)) {
3347 err = sky2_up(dev);
3348 if (err)
3349 dev_close(dev);
3350 else
3351 sky2_set_multicast(dev);
3352 }
3353
3354 return err;
3355 }
3356
3357 static int sky2_get_regs_len(struct net_device *dev)
3358 {
3359 return 0x4000;
3360 }
3361
3362 /*
3363 * Returns copy of control register region
3364 * Note: access to the RAM address register set will cause timeouts.
3365 */
3366 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3367 void *p)
3368 {
3369 const struct sky2_port *sky2 = netdev_priv(dev);
3370 const void __iomem *io = sky2->hw->regs;
3371
3372 BUG_ON(regs->len < B3_RI_WTO_R1);
3373 regs->version = 1;
3374 memset(p, 0, regs->len);
3375
3376 memcpy_fromio(p, io, B3_RAM_ADDR);
3377
3378 memcpy_fromio(p + B3_RI_WTO_R1,
3379 io + B3_RI_WTO_R1,
3380 regs->len - B3_RI_WTO_R1);
3381 }
3382
3383 /* In order to do Jumbo packets on these chips, need to turn off the
3384 * transmit store/forward. Therefore checksum offload won't work.
3385 */
3386 static int no_tx_offload(struct net_device *dev)
3387 {
3388 const struct sky2_port *sky2 = netdev_priv(dev);
3389 const struct sky2_hw *hw = sky2->hw;
3390
3391 return dev->mtu > ETH_DATA_LEN &&
3392 (hw->chip_id == CHIP_ID_YUKON_EX
3393 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3394 }
3395
3396 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3397 {
3398 if (data && no_tx_offload(dev))
3399 return -EINVAL;
3400
3401 return ethtool_op_set_tx_csum(dev, data);
3402 }
3403
3404
3405 static int sky2_set_tso(struct net_device *dev, u32 data)
3406 {
3407 if (data && no_tx_offload(dev))
3408 return -EINVAL;
3409
3410 return ethtool_op_set_tso(dev, data);
3411 }
3412
3413 static const struct ethtool_ops sky2_ethtool_ops = {
3414 .get_settings = sky2_get_settings,
3415 .set_settings = sky2_set_settings,
3416 .get_drvinfo = sky2_get_drvinfo,
3417 .get_wol = sky2_get_wol,
3418 .set_wol = sky2_set_wol,
3419 .get_msglevel = sky2_get_msglevel,
3420 .set_msglevel = sky2_set_msglevel,
3421 .nway_reset = sky2_nway_reset,
3422 .get_regs_len = sky2_get_regs_len,
3423 .get_regs = sky2_get_regs,
3424 .get_link = ethtool_op_get_link,
3425 .get_sg = ethtool_op_get_sg,
3426 .set_sg = ethtool_op_set_sg,
3427 .get_tx_csum = ethtool_op_get_tx_csum,
3428 .set_tx_csum = sky2_set_tx_csum,
3429 .get_tso = ethtool_op_get_tso,
3430 .set_tso = sky2_set_tso,
3431 .get_rx_csum = sky2_get_rx_csum,
3432 .set_rx_csum = sky2_set_rx_csum,
3433 .get_strings = sky2_get_strings,
3434 .get_coalesce = sky2_get_coalesce,
3435 .set_coalesce = sky2_set_coalesce,
3436 .get_ringparam = sky2_get_ringparam,
3437 .set_ringparam = sky2_set_ringparam,
3438 .get_pauseparam = sky2_get_pauseparam,
3439 .set_pauseparam = sky2_set_pauseparam,
3440 .phys_id = sky2_phys_id,
3441 .get_stats_count = sky2_get_stats_count,
3442 .get_ethtool_stats = sky2_get_ethtool_stats,
3443 .get_perm_addr = ethtool_op_get_perm_addr,
3444 };
3445
3446 /* Initialize network device */
3447 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3448 unsigned port,
3449 int highmem, int wol)
3450 {
3451 struct sky2_port *sky2;
3452 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3453
3454 if (!dev) {
3455 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3456 return NULL;
3457 }
3458
3459 SET_MODULE_OWNER(dev);
3460 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3461 dev->irq = hw->pdev->irq;
3462 dev->open = sky2_up;
3463 dev->stop = sky2_down;
3464 dev->do_ioctl = sky2_ioctl;
3465 dev->hard_start_xmit = sky2_xmit_frame;
3466 dev->get_stats = sky2_get_stats;
3467 dev->set_multicast_list = sky2_set_multicast;
3468 dev->set_mac_address = sky2_set_mac_address;
3469 dev->change_mtu = sky2_change_mtu;
3470 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3471 dev->tx_timeout = sky2_tx_timeout;
3472 dev->watchdog_timeo = TX_WATCHDOG;
3473 if (port == 0)
3474 dev->poll = sky2_poll;
3475 dev->weight = NAPI_WEIGHT;
3476 #ifdef CONFIG_NET_POLL_CONTROLLER
3477 /* Network console (only works on port 0)
3478 * because netpoll makes assumptions about NAPI
3479 */
3480 if (port == 0)
3481 dev->poll_controller = sky2_netpoll;
3482 #endif
3483
3484 sky2 = netdev_priv(dev);
3485 sky2->netdev = dev;
3486 sky2->hw = hw;
3487 sky2->msg_enable = netif_msg_init(debug, default_msg);
3488
3489 /* Auto speed and flow control */
3490 sky2->autoneg = AUTONEG_ENABLE;
3491 sky2->flow_mode = FC_BOTH;
3492
3493 sky2->duplex = -1;
3494 sky2->speed = -1;
3495 sky2->advertising = sky2_supported_modes(hw);
3496 sky2->rx_csum = 1;
3497 sky2->wol = wol;
3498
3499 spin_lock_init(&sky2->phy_lock);
3500 sky2->tx_pending = TX_DEF_PENDING;
3501 sky2->rx_pending = RX_DEF_PENDING;
3502
3503 hw->dev[port] = dev;
3504
3505 sky2->port = port;
3506
3507 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3508 if (highmem)
3509 dev->features |= NETIF_F_HIGHDMA;
3510
3511 #ifdef SKY2_VLAN_TAG_USED
3512 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3513 dev->vlan_rx_register = sky2_vlan_rx_register;
3514 #endif
3515
3516 /* read the mac address */
3517 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3518 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3519
3520 return dev;
3521 }
3522
3523 static void __devinit sky2_show_addr(struct net_device *dev)
3524 {
3525 const struct sky2_port *sky2 = netdev_priv(dev);
3526
3527 if (netif_msg_probe(sky2))
3528 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3529 dev->name,
3530 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3531 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3532 }
3533
3534 /* Handle software interrupt used during MSI test */
3535 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3536 {
3537 struct sky2_hw *hw = dev_id;
3538 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3539
3540 if (status == 0)
3541 return IRQ_NONE;
3542
3543 if (status & Y2_IS_IRQ_SW) {
3544 hw->msi = 1;
3545 wake_up(&hw->msi_wait);
3546 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3547 }
3548 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3549
3550 return IRQ_HANDLED;
3551 }
3552
3553 /* Test interrupt path by forcing a a software IRQ */
3554 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3555 {
3556 struct pci_dev *pdev = hw->pdev;
3557 int err;
3558
3559 init_waitqueue_head (&hw->msi_wait);
3560
3561 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3562
3563 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3564 if (err) {
3565 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3566 return err;
3567 }
3568
3569 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3570 sky2_read8(hw, B0_CTST);
3571
3572 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3573
3574 if (!hw->msi) {
3575 /* MSI test failed, go back to INTx mode */
3576 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3577 "switching to INTx mode.\n");
3578
3579 err = -EOPNOTSUPP;
3580 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3581 }
3582
3583 sky2_write32(hw, B0_IMSK, 0);
3584 sky2_read32(hw, B0_IMSK);
3585
3586 free_irq(pdev->irq, hw);
3587
3588 return err;
3589 }
3590
3591 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3592 {
3593 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3594 u16 value;
3595
3596 if (!pm)
3597 return 0;
3598 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3599 return 0;
3600 return value & PCI_PM_CTRL_PME_ENABLE;
3601 }
3602
3603 static int __devinit sky2_probe(struct pci_dev *pdev,
3604 const struct pci_device_id *ent)
3605 {
3606 struct net_device *dev;
3607 struct sky2_hw *hw;
3608 int err, using_dac = 0, wol_default;
3609
3610 err = pci_enable_device(pdev);
3611 if (err) {
3612 dev_err(&pdev->dev, "cannot enable PCI device\n");
3613 goto err_out;
3614 }
3615
3616 err = pci_request_regions(pdev, DRV_NAME);
3617 if (err) {
3618 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3619 goto err_out_disable;
3620 }
3621
3622 pci_set_master(pdev);
3623
3624 if (sizeof(dma_addr_t) > sizeof(u32) &&
3625 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3626 using_dac = 1;
3627 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3628 if (err < 0) {
3629 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3630 "for consistent allocations\n");
3631 goto err_out_free_regions;
3632 }
3633 } else {
3634 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3635 if (err) {
3636 dev_err(&pdev->dev, "no usable DMA configuration\n");
3637 goto err_out_free_regions;
3638 }
3639 }
3640
3641 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3642
3643 err = -ENOMEM;
3644 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3645 if (!hw) {
3646 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3647 goto err_out_free_regions;
3648 }
3649
3650 hw->pdev = pdev;
3651
3652 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3653 if (!hw->regs) {
3654 dev_err(&pdev->dev, "cannot map device registers\n");
3655 goto err_out_free_hw;
3656 }
3657
3658 #ifdef __BIG_ENDIAN
3659 /* The sk98lin vendor driver uses hardware byte swapping but
3660 * this driver uses software swapping.
3661 */
3662 {
3663 u32 reg;
3664 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3665 reg &= ~PCI_REV_DESC;
3666 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3667 }
3668 #endif
3669
3670 /* ring for status responses */
3671 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3672 &hw->st_dma);
3673 if (!hw->st_le)
3674 goto err_out_iounmap;
3675
3676 err = sky2_init(hw);
3677 if (err)
3678 goto err_out_iounmap;
3679
3680 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3681 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3682 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3683 hw->chip_id, hw->chip_rev);
3684
3685 sky2_reset(hw);
3686
3687 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3688 if (!dev) {
3689 err = -ENOMEM;
3690 goto err_out_free_pci;
3691 }
3692
3693 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3694 err = sky2_test_msi(hw);
3695 if (err == -EOPNOTSUPP)
3696 pci_disable_msi(pdev);
3697 else if (err)
3698 goto err_out_free_netdev;
3699 }
3700
3701 err = register_netdev(dev);
3702 if (err) {
3703 dev_err(&pdev->dev, "cannot register net device\n");
3704 goto err_out_free_netdev;
3705 }
3706
3707 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3708 dev->name, hw);
3709 if (err) {
3710 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3711 goto err_out_unregister;
3712 }
3713 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3714
3715 sky2_show_addr(dev);
3716
3717 if (hw->ports > 1) {
3718 struct net_device *dev1;
3719
3720 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3721 if (!dev1)
3722 dev_warn(&pdev->dev, "allocation for second device failed\n");
3723 else if ((err = register_netdev(dev1))) {
3724 dev_warn(&pdev->dev,
3725 "register of second port failed (%d)\n", err);
3726 hw->dev[1] = NULL;
3727 free_netdev(dev1);
3728 } else
3729 sky2_show_addr(dev1);
3730 }
3731
3732 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
3733 INIT_WORK(&hw->restart_work, sky2_restart);
3734
3735 pci_set_drvdata(pdev, hw);
3736
3737 return 0;
3738
3739 err_out_unregister:
3740 if (hw->msi)
3741 pci_disable_msi(pdev);
3742 unregister_netdev(dev);
3743 err_out_free_netdev:
3744 free_netdev(dev);
3745 err_out_free_pci:
3746 sky2_write8(hw, B0_CTST, CS_RST_SET);
3747 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3748 err_out_iounmap:
3749 iounmap(hw->regs);
3750 err_out_free_hw:
3751 kfree(hw);
3752 err_out_free_regions:
3753 pci_release_regions(pdev);
3754 err_out_disable:
3755 pci_disable_device(pdev);
3756 err_out:
3757 pci_set_drvdata(pdev, NULL);
3758 return err;
3759 }
3760
3761 static void __devexit sky2_remove(struct pci_dev *pdev)
3762 {
3763 struct sky2_hw *hw = pci_get_drvdata(pdev);
3764 struct net_device *dev0, *dev1;
3765
3766 if (!hw)
3767 return;
3768
3769 del_timer_sync(&hw->watchdog_timer);
3770
3771 flush_scheduled_work();
3772
3773 sky2_write32(hw, B0_IMSK, 0);
3774 synchronize_irq(hw->pdev->irq);
3775
3776 dev0 = hw->dev[0];
3777 dev1 = hw->dev[1];
3778 if (dev1)
3779 unregister_netdev(dev1);
3780 unregister_netdev(dev0);
3781
3782 sky2_power_aux(hw);
3783
3784 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3785 sky2_write8(hw, B0_CTST, CS_RST_SET);
3786 sky2_read8(hw, B0_CTST);
3787
3788 free_irq(pdev->irq, hw);
3789 if (hw->msi)
3790 pci_disable_msi(pdev);
3791 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3792 pci_release_regions(pdev);
3793 pci_disable_device(pdev);
3794
3795 if (dev1)
3796 free_netdev(dev1);
3797 free_netdev(dev0);
3798 iounmap(hw->regs);
3799 kfree(hw);
3800
3801 pci_set_drvdata(pdev, NULL);
3802 }
3803
3804 #ifdef CONFIG_PM
3805 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3806 {
3807 struct sky2_hw *hw = pci_get_drvdata(pdev);
3808 int i, wol = 0;
3809
3810 if (!hw)
3811 return 0;
3812
3813 del_timer_sync(&hw->watchdog_timer);
3814 netif_poll_disable(hw->dev[0]);
3815
3816 for (i = 0; i < hw->ports; i++) {
3817 struct net_device *dev = hw->dev[i];
3818 struct sky2_port *sky2 = netdev_priv(dev);
3819
3820 if (netif_running(dev))
3821 sky2_down(dev);
3822
3823 if (sky2->wol)
3824 sky2_wol_init(sky2);
3825
3826 wol |= sky2->wol;
3827 }
3828
3829 sky2_write32(hw, B0_IMSK, 0);
3830 sky2_power_aux(hw);
3831
3832 pci_save_state(pdev);
3833 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3834 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3835
3836 return 0;
3837 }
3838
3839 static int sky2_resume(struct pci_dev *pdev)
3840 {
3841 struct sky2_hw *hw = pci_get_drvdata(pdev);
3842 int i, err;
3843
3844 if (!hw)
3845 return 0;
3846
3847 err = pci_set_power_state(pdev, PCI_D0);
3848 if (err)
3849 goto out;
3850
3851 err = pci_restore_state(pdev);
3852 if (err)
3853 goto out;
3854
3855 pci_enable_wake(pdev, PCI_D0, 0);
3856
3857 /* Re-enable all clocks */
3858 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3859 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3860
3861 sky2_reset(hw);
3862
3863 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3864
3865 for (i = 0; i < hw->ports; i++) {
3866 struct net_device *dev = hw->dev[i];
3867 if (netif_running(dev)) {
3868 err = sky2_up(dev);
3869 if (err) {
3870 printk(KERN_ERR PFX "%s: could not up: %d\n",
3871 dev->name, err);
3872 dev_close(dev);
3873 goto out;
3874 }
3875 }
3876 }
3877
3878 netif_poll_enable(hw->dev[0]);
3879
3880 return 0;
3881 out:
3882 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3883 pci_disable_device(pdev);
3884 return err;
3885 }
3886 #endif
3887
3888 static void sky2_shutdown(struct pci_dev *pdev)
3889 {
3890 struct sky2_hw *hw = pci_get_drvdata(pdev);
3891 int i, wol = 0;
3892
3893 if (!hw)
3894 return;
3895
3896 netif_poll_disable(hw->dev[0]);
3897
3898 for (i = 0; i < hw->ports; i++) {
3899 struct net_device *dev = hw->dev[i];
3900 struct sky2_port *sky2 = netdev_priv(dev);
3901
3902 if (sky2->wol) {
3903 wol = 1;
3904 sky2_wol_init(sky2);
3905 }
3906 }
3907
3908 if (wol)
3909 sky2_power_aux(hw);
3910
3911 pci_enable_wake(pdev, PCI_D3hot, wol);
3912 pci_enable_wake(pdev, PCI_D3cold, wol);
3913
3914 pci_disable_device(pdev);
3915 pci_set_power_state(pdev, PCI_D3hot);
3916
3917 }
3918
3919 static struct pci_driver sky2_driver = {
3920 .name = DRV_NAME,
3921 .id_table = sky2_id_table,
3922 .probe = sky2_probe,
3923 .remove = __devexit_p(sky2_remove),
3924 #ifdef CONFIG_PM
3925 .suspend = sky2_suspend,
3926 .resume = sky2_resume,
3927 #endif
3928 .shutdown = sky2_shutdown,
3929 };
3930
3931 static int __init sky2_init_module(void)
3932 {
3933 return pci_register_driver(&sky2_driver);
3934 }
3935
3936 static void __exit sky2_cleanup_module(void)
3937 {
3938 pci_unregister_driver(&sky2_driver);
3939 }
3940
3941 module_init(sky2_init_module);
3942 module_exit(sky2_cleanup_module);
3943
3944 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3945 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3946 MODULE_LICENSE("GPL");
3947 MODULE_VERSION(DRV_VERSION);
linux v2.6.22.y-op