drivers/mtd/nand/cs553x_nand.c

   1 /*
   2  * drivers/mtd/nand/cs553x_nand.c
   3  *
   4  * (C) 2005, 2006 Red Hat Inc.
   5  *
   6  * Author: David Woodhouse <dwmw2@infradead.org>
   7  *         Tom Sylla <tom.sylla@amd.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  *  Overview:
  14  *   This is a device driver for the NAND flash controller found on
  15  *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
  16  *
  17  */
  18
  19 #include <linux/slab.h>
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/delay.h>
  23 #include <linux/pci.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/nand_ecc.h>
  27 #include <linux/mtd/partitions.h>
  28
  29 #include <asm/msr.h>
  30 #include <asm/io.h>
  31
  32 #define NR_CS553X_CONTROLLERS   4
  33
  34 /* NAND Timing MSRs */
  35 #define MSR_NANDF_DATA          0x5140001b      /* NAND Flash Data Timing MSR */
  36 #define MSR_NANDF_CTL           0x5140001c      /* NAND Flash Control Timing */
  37 #define MSR_NANDF_RSVD          0x5140001d      /* Reserved */
  38
  39 /* NAND BAR MSRs */
  40 #define MSR_DIVIL_LBAR_FLSH0    0x51400010      /* Flash Chip Select 0 */
  41 #define MSR_DIVIL_LBAR_FLSH1    0x51400011      /* Flash Chip Select 1 */
  42 #define MSR_DIVIL_LBAR_FLSH2    0x51400012      /* Flash Chip Select 2 */
  43 #define MSR_DIVIL_LBAR_FLSH3    0x51400013      /* Flash Chip Select 3 */
  44         /* Each made up of... */
  45 #define FLSH_LBAR_EN            (1ULL<<32)
  46 #define FLSH_NOR_NAND           (1ULL<<33)      /* 1 for NAND */
  47 #define FLSH_MEM_IO             (1ULL<<34)      /* 1 for MMIO */
  48         /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
  49         /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
  50
  51 /* Pin function selection MSR (IDE vs. flash on the IDE pins) */
  52 #define MSR_DIVIL_BALL_OPTS     0x51400015
  53 #define PIN_OPT_IDE             (1<<0)          /* 0 for flash, 1 for IDE */
  54
  55 /* Registers within the NAND flash controller BAR -- memory mapped */
  56 #define MM_NAND_DATA            0x00    /* 0 to 0x7ff, in fact */
  57 #define MM_NAND_CTL             0x800   /* Any even address 0x800-0x80e */
  58 #define MM_NAND_IO              0x801   /* Any odd address 0x801-0x80f */
  59 #define MM_NAND_STS             0x810
  60 #define MM_NAND_ECC_LSB         0x811
  61 #define MM_NAND_ECC_MSB         0x812
  62 #define MM_NAND_ECC_COL         0x813
  63 #define MM_NAND_LAC             0x814
  64 #define MM_NAND_ECC_CTL         0x815
  65
  66 /* Registers within the NAND flash controller BAR -- I/O mapped */
  67 #define IO_NAND_DATA            0x00    /* 0 to 3, in fact */
  68 #define IO_NAND_CTL             0x04
  69 #define IO_NAND_IO              0x05
  70 #define IO_NAND_STS             0x06
  71 #define IO_NAND_ECC_CTL         0x08
  72 #define IO_NAND_ECC_LSB         0x09
  73 #define IO_NAND_ECC_MSB         0x0a
  74 #define IO_NAND_ECC_COL         0x0b
  75 #define IO_NAND_LAC             0x0c
  76
  77 #define CS_NAND_CTL_DIST_EN     (1<<4)  /* Enable NAND Distract interrupt */
  78 #define CS_NAND_CTL_RDY_INT_MASK        (1<<3)  /* Enable RDY/BUSY# interrupt */
  79 #define CS_NAND_CTL_ALE         (1<<2)
  80 #define CS_NAND_CTL_CLE         (1<<1)
  81 #define CS_NAND_CTL_CE          (1<<0)  /* Keep low; 1 to reset */
  82
  83 #define CS_NAND_STS_FLASH_RDY   (1<<3)
  84 #define CS_NAND_CTLR_BUSY       (1<<2)
  85 #define CS_NAND_CMD_COMP        (1<<1)
  86 #define CS_NAND_DIST_ST         (1<<0)
  87
  88 #define CS_NAND_ECC_PARITY      (1<<2)
  89 #define CS_NAND_ECC_CLRECC      (1<<1)
  90 #define CS_NAND_ECC_ENECC       (1<<0)
  91
  92 static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  93 {
  94         struct nand_chip *this = mtd->priv;
  95
  96         while (unlikely(len > 0x800)) {
  97                 memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
  98                 buf += 0x800;
  99                 len -= 0x800;
 100         }
 101         memcpy_fromio(buf, this->IO_ADDR_R, len);
 102 }
 103
 104 static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 105 {
 106         struct nand_chip *this = mtd->priv;
 107
 108         while (unlikely(len > 0x800)) {
 109                 memcpy_toio(this->IO_ADDR_R, buf, 0x800);
 110                 buf += 0x800;
 111                 len -= 0x800;
 112         }
 113         memcpy_toio(this->IO_ADDR_R, buf, len);
 114 }
 115
 116 static unsigned char cs553x_read_byte(struct mtd_info *mtd)
 117 {
 118         struct nand_chip *this = mtd->priv;
 119         return readb(this->IO_ADDR_R);
 120 }
 121
 122 static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
 123 {
 124         struct nand_chip *this = mtd->priv;
 125         int i = 100000;
 126
 127         while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
 128                 udelay(1);
 129                 i--;
 130         }
 131         writeb(byte, this->IO_ADDR_W+0x801);
 132 }
 133
 134 static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd)
 135 {
 136         struct nand_chip *this = mtd->priv;
 137         void __iomem *mmio_base = this->IO_ADDR_R;
 138         unsigned char ctl;
 139
 140         switch(cmd) {
 141         case NAND_CTL_SETCLE:
 142                 ctl = CS_NAND_CTL_CLE;
 143                 break;
 144
 145         case NAND_CTL_CLRCLE:
 146         case NAND_CTL_CLRALE:
 147         case NAND_CTL_SETNCE:
 148                 ctl = 0;
 149                 break;
 150
 151         case NAND_CTL_SETALE:
 152                 ctl = CS_NAND_CTL_ALE;
 153                 break;
 154
 155         default:
 156         case NAND_CTL_CLRNCE:
 157                 ctl = CS_NAND_CTL_CE;
 158                 break;
 159         }
 160         writeb(ctl, mmio_base + MM_NAND_CTL);
 161 }
 162
 163
 164 static int cs553x_device_ready(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *this = mtd->priv;
 167         void __iomem *mmio_base = this->IO_ADDR_R;
 168         unsigned char foo = readb(mmio_base + MM_NAND_STS);
 169
 170         return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
 171 }
 172
 173
 174 static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
 175 {
 176         struct nand_chip *this = mtd->priv;
 177         void __iomem *mmio_base = this->IO_ADDR_R;
 178
 179         writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
 180 }
 181
 182 static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 183 {
 184         uint32_t ecc;
 185         struct nand_chip *this = mtd->priv;
 186         void __iomem *mmio_base = this->IO_ADDR_R;
 187
 188         ecc = readl(mmio_base + MM_NAND_STS);
 189
 190         ecc_code[1] = ecc >> 8;
 191         ecc_code[0] = ecc >> 16;
 192         ecc_code[2] = ecc >> 24;
 193         return 0;
 194 }
 195
 196 static struct mtd_info *cs553x_mtd[4];
 197
 198 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 199 {
 200         int err = 0;
 201         struct nand_chip *this;
 202         struct mtd_info *new_mtd;
 203
 204         printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
 205
 206         if (!mmio) {
 207                 printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
 208                 return -ENXIO;
 209         }
 210
 211         /* Allocate memory for MTD device structure and private data */
 212         new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip), GFP_KERNEL);
 213         if (!new_mtd) {
 214                 printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
 215                 err = -ENOMEM;
 216                 goto out;
 217         }
 218
 219         /* Get pointer to private data */
 220         this = (struct nand_chip *) (&new_mtd[1]);
 221
 222         /* Initialize structures */
 223         memset(new_mtd, 0, sizeof(struct mtd_info));
 224         memset(this, 0, sizeof(struct nand_chip));
 225
 226         /* Link the private data with the MTD structure */
 227         new_mtd->priv = this;
 228
 229         /* map physical address */
 230         this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
 231         if (!this->IO_ADDR_R) {
 232                 printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
 233                 err = -EIO;
 234                 goto out_mtd;
 235         }
 236
 237         this->hwcontrol = cs553x_hwcontrol;
 238         this->dev_ready = cs553x_device_ready;
 239         this->read_byte = cs553x_read_byte;
 240         this->write_byte = cs553x_write_byte;
 241         this->read_buf = cs553x_read_buf;
 242         this->write_buf = cs553x_write_buf;
 243
 244         this->chip_delay = 0;
 245
 246         this->eccmode = NAND_ECC_HW3_256;
 247         this->enable_hwecc  = cs_enable_hwecc;
 248         this->calculate_ecc = cs_calculate_ecc;
 249         this->correct_data  = nand_correct_data;
 250
 251         /* Enable the following for a flash based bad block table */
 252         this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;
 253
 254         /* Scan to find existance of the device */
 255         if (nand_scan(new_mtd, 1)) {
 256                 err = -ENXIO;
 257                 goto out_ior;
 258         }
 259
 260         new_mtd->owner = THIS_MODULE;
 261         cs553x_mtd[cs] = new_mtd;
 262         goto out;
 263
 264 out_ior:
 265         iounmap((void *)this->IO_ADDR_R);
 266 out_mtd:
 267         kfree(new_mtd);
 268 out:
 269         return err;
 270 }
 271
 272 int __init cs553x_init(void)
 273 {
 274         int err = -ENXIO;
 275         int i;
 276         uint64_t val;
 277
 278         /* Check whether we actually have a CS5535 or CS5536 */
 279         if (!pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, NULL) &&
 280             !pci_find_device(PCI_VENDOR_ID_NS,  PCI_DEVICE_ID_NS_CS5535_ISA, NULL))
 281                 return -ENXIO;
 282
 283         rdmsrl(MSR_DIVIL_BALL_OPTS, val);
 284         if (val & 1) {
 285                 printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
 286                 return -ENXIO;
 287         }
 288
 289         for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
 290                 rdmsrl(MSR_DIVIL_LBAR_FLSH0+i, val);
 291
 292                 if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
 293                         err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
 294         }
 295
 296         /* Register all devices together here. This means we can easily hack it to
 297            do mtdconcat etc. if we want to. */
 298         for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
 299                 if (cs553x_mtd[i]) {
 300                         add_mtd_device(cs553x_mtd[i]);
 301
 302                         /* If any devices registered, return success. Else the last error. */
 303                         err = 0;
 304                 }
 305         }
 306
 307         return err;
 308 }
 309 module_init(cs553x_init);
 310
 311 static void __exit cs553x_cleanup (void)
 312 {
 313         int i;
 314
 315         for (i=0; i<NR_CS553X_CONTROLLERS; i++) {
 316                 struct mtd_info *mtd = cs553x_mtd[i];
 317                 struct nand_chip *this;
 318                 void __iomem *mmio_base;
 319
 320                 if (!mtd)
 321                         break;
 322
 323                 this = cs553x_mtd[i]->priv;
 324                 mmio_base = this->IO_ADDR_R;
 325
 326                 /* Release resources, unregister device */
 327                 nand_release (cs553x_mtd[i]);
 328                 cs553x_mtd[i] = NULL;
 329
 330                 /* unmap physical adress */
 331                 iounmap(mmio_base);
 332
 333                 /* Free the MTD device structure */
 334                 kfree(mtd);
 335         }
 336 }
 337 module_exit(cs553x_cleanup);
 338
 339 MODULE_LICENSE("GPL");
 340 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 341 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");