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[TG3]: Remove reset during MAC address changes.
[linux-2.6.22.y-op.git] / drivers / net / tg3.c
blob321121874c770645725fdd0ef52dbe53218c7080
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43 #include <net/ip.h>
44
45 #include <asm/system.h>
46 #include <asm/io.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
49
50 #ifdef CONFIG_SPARC
51 #include <asm/idprom.h>
52 #include <asm/prom.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #define TG3_TSO_SUPPORT 1
62
63 #include "tg3.h"
64
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.75"
68 #define DRV_MODULE_RELDATE "March 23, 2007"
69
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_IFDOWN | \
79 NETIF_MSG_IFUP | \
80 NETIF_MSG_RX_ERR | \
81 NETIF_MSG_TX_ERR)
82
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
85 */
86 #define TG3_TX_TIMEOUT (5 * HZ)
87
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
92
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
96 */
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
101
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
107 */
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
110
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
113
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
115 TG3_RX_RING_SIZE)
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
121 TG3_TX_RING_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
123
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
126
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
129
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
132
133 #define TG3_NUM_TEST 6
134
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
137
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
142
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
146
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
208 {}
209 };
210
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
212
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
216 { "rx_octets" },
217 { "rx_fragments" },
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
221 { "rx_fcs_errors" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
228 { "rx_jabbers" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
242
243 { "tx_octets" },
244 { "tx_collisions" },
245
246 { "tx_xon_sent" },
247 { "tx_xoff_sent" },
248 { "tx_flow_control" },
249 { "tx_mac_errors" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
252 { "tx_deferred" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
273 { "tx_discards" },
274 { "tx_errors" },
275
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
278 { "rxbds_empty" },
279 { "rx_discards" },
280 { "rx_errors" },
281 { "rx_threshold_hit" },
282
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
286
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
289 { "nic_irqs" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
292 };
293
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
303 };
304
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
306 {
307 writel(val, tp->regs + off);
308 }
309
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
311 {
312 return (readl(tp->regs + off));
313 }
314
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
323 }
324
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
326 {
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
329 }
330
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
332 {
333 unsigned long flags;
334 u32 val;
335
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
340 return val;
341 }
342
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
344 {
345 unsigned long flags;
346
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
350 return;
351 }
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
355 return;
356 }
357
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
362
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
365 */
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
367 (val == 0x1)) {
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
370 }
371 }
372
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
374 {
375 unsigned long flags;
376 u32 val;
377
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
382 return val;
383 }
384
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
389 */
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
391 {
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
396 else {
397 /* Posted method */
398 tg3_write32(tp, off, val);
399 if (usec_wait)
400 udelay(usec_wait);
401 tp->read32(tp, off);
402 }
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
405 */
406 if (usec_wait)
407 udelay(usec_wait);
408 }
409
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
411 {
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
416 }
417
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
419 {
420 void __iomem *mbox = tp->regs + off;
421 writel(val, mbox);
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
423 writel(val, mbox);
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
425 readl(mbox);
426 }
427
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
429 {
430 return (readl(tp->regs + off + GRCMBOX_BASE));
431 }
432
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
434 {
435 writel(val, tp->regs + off + GRCMBOX_BASE);
436 }
437
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
443
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
448
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
450 {
451 unsigned long flags;
452
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
455 return;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
461
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
464 } else {
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
467
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
470 }
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
472 }
473
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
475 {
476 unsigned long flags;
477
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
480 *val = 0;
481 return;
482 }
483
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
488
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
491 } else {
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
494
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
497 }
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
499 }
500
501 static void tg3_disable_ints(struct tg3 *tp)
502 {
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
506 }
507
508 static inline void tg3_cond_int(struct tg3 *tp)
509 {
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
513 else
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
516 }
517
518 static void tg3_enable_ints(struct tg3 *tp)
519 {
520 tp->irq_sync = 0;
521 wmb();
522
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 tg3_cond_int(tp);
531 }
532
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
534 {
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
537
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
543 work_exists = 1;
544 }
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
548 work_exists = 1;
549
550 return work_exists;
551 }
552
553 /* tg3_restart_ints
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
557 */
558 static void tg3_restart_ints(struct tg3 *tp)
559 {
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
561 tp->last_tag << 24);
562 mmiowb();
563
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
567 */
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
569 tg3_has_work(tp))
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
572 }
573
574 static inline void tg3_netif_stop(struct tg3 *tp)
575 {
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
579 }
580
581 static inline void tg3_netif_start(struct tg3 *tp)
582 {
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
587 */
588 netif_poll_enable(tp->dev);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
590 tg3_enable_ints(tp);
591 }
592
593 static void tg3_switch_clocks(struct tg3 *tp)
594 {
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
596 u32 orig_clock_ctrl;
597
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
599 return;
600
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
604 0x1f);
605 tp->pci_clock_ctrl = clock_ctrl;
606
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
611 }
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
614 clock_ctrl |
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
616 40);
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
619 40);
620 }
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
622 }
623
624 #define PHY_BUSY_LOOPS 5000
625
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
627 {
628 u32 frame_val;
629 unsigned int loops;
630 int ret;
631
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
633 tw32_f(MAC_MI_MODE,
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
635 udelay(80);
636 }
637
638 *val = 0x0;
639
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
645
646 tw32_f(MAC_MI_COM, frame_val);
647
648 loops = PHY_BUSY_LOOPS;
649 while (loops != 0) {
650 udelay(10);
651 frame_val = tr32(MAC_MI_COM);
652
653 if ((frame_val & MI_COM_BUSY) == 0) {
654 udelay(5);
655 frame_val = tr32(MAC_MI_COM);
656 break;
657 }
658 loops -= 1;
659 }
660
661 ret = -EBUSY;
662 if (loops != 0) {
663 *val = frame_val & MI_COM_DATA_MASK;
664 ret = 0;
665 }
666
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
669 udelay(80);
670 }
671
672 return ret;
673 }
674
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
676 {
677 u32 frame_val;
678 unsigned int loops;
679 int ret;
680
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
683 return 0;
684
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
686 tw32_f(MAC_MI_MODE,
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
688 udelay(80);
689 }
690
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
697
698 tw32_f(MAC_MI_COM, frame_val);
699
700 loops = PHY_BUSY_LOOPS;
701 while (loops != 0) {
702 udelay(10);
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
705 udelay(5);
706 frame_val = tr32(MAC_MI_COM);
707 break;
708 }
709 loops -= 1;
710 }
711
712 ret = -EBUSY;
713 if (loops != 0)
714 ret = 0;
715
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
718 udelay(80);
719 }
720
721 return ret;
722 }
723
724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
725 {
726 u32 val;
727
728 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
729 return;
730
731 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
732 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
733 tg3_writephy(tp, MII_TG3_AUX_CTRL,
734 (val | (1 << 15) | (1 << 4)));
735 }
736
737 static int tg3_bmcr_reset(struct tg3 *tp)
738 {
739 u32 phy_control;
740 int limit, err;
741
742 /* OK, reset it, and poll the BMCR_RESET bit until it
743 * clears or we time out.
744 */
745 phy_control = BMCR_RESET;
746 err = tg3_writephy(tp, MII_BMCR, phy_control);
747 if (err != 0)
748 return -EBUSY;
749
750 limit = 5000;
751 while (limit--) {
752 err = tg3_readphy(tp, MII_BMCR, &phy_control);
753 if (err != 0)
754 return -EBUSY;
755
756 if ((phy_control & BMCR_RESET) == 0) {
757 udelay(40);
758 break;
759 }
760 udelay(10);
761 }
762 if (limit <= 0)
763 return -EBUSY;
764
765 return 0;
766 }
767
768 static int tg3_wait_macro_done(struct tg3 *tp)
769 {
770 int limit = 100;
771
772 while (limit--) {
773 u32 tmp32;
774
775 if (!tg3_readphy(tp, 0x16, &tmp32)) {
776 if ((tmp32 & 0x1000) == 0)
777 break;
778 }
779 }
780 if (limit <= 0)
781 return -EBUSY;
782
783 return 0;
784 }
785
786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
787 {
788 static const u32 test_pat[4][6] = {
789 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
790 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
791 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
792 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
793 };
794 int chan;
795
796 for (chan = 0; chan < 4; chan++) {
797 int i;
798
799 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
800 (chan * 0x2000) | 0x0200);
801 tg3_writephy(tp, 0x16, 0x0002);
802
803 for (i = 0; i < 6; i++)
804 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
805 test_pat[chan][i]);
806
807 tg3_writephy(tp, 0x16, 0x0202);
808 if (tg3_wait_macro_done(tp)) {
809 *resetp = 1;
810 return -EBUSY;
811 }
812
813 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
814 (chan * 0x2000) | 0x0200);
815 tg3_writephy(tp, 0x16, 0x0082);
816 if (tg3_wait_macro_done(tp)) {
817 *resetp = 1;
818 return -EBUSY;
819 }
820
821 tg3_writephy(tp, 0x16, 0x0802);
822 if (tg3_wait_macro_done(tp)) {
823 *resetp = 1;
824 return -EBUSY;
825 }
826
827 for (i = 0; i < 6; i += 2) {
828 u32 low, high;
829
830 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
831 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
832 tg3_wait_macro_done(tp)) {
833 *resetp = 1;
834 return -EBUSY;
835 }
836 low &= 0x7fff;
837 high &= 0x000f;
838 if (low != test_pat[chan][i] ||
839 high != test_pat[chan][i+1]) {
840 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
841 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
843
844 return -EBUSY;
845 }
846 }
847 }
848
849 return 0;
850 }
851
852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
853 {
854 int chan;
855
856 for (chan = 0; chan < 4; chan++) {
857 int i;
858
859 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
860 (chan * 0x2000) | 0x0200);
861 tg3_writephy(tp, 0x16, 0x0002);
862 for (i = 0; i < 6; i++)
863 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
864 tg3_writephy(tp, 0x16, 0x0202);
865 if (tg3_wait_macro_done(tp))
866 return -EBUSY;
867 }
868
869 return 0;
870 }
871
872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
873 {
874 u32 reg32, phy9_orig;
875 int retries, do_phy_reset, err;
876
877 retries = 10;
878 do_phy_reset = 1;
879 do {
880 if (do_phy_reset) {
881 err = tg3_bmcr_reset(tp);
882 if (err)
883 return err;
884 do_phy_reset = 0;
885 }
886
887 /* Disable transmitter and interrupt. */
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
889 continue;
890
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
893
894 /* Set full-duplex, 1000 mbps. */
895 tg3_writephy(tp, MII_BMCR,
896 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
897
898 /* Set to master mode. */
899 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
900 continue;
901
902 tg3_writephy(tp, MII_TG3_CTRL,
903 (MII_TG3_CTRL_AS_MASTER |
904 MII_TG3_CTRL_ENABLE_AS_MASTER));
905
906 /* Enable SM_DSP_CLOCK and 6dB. */
907 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
908
909 /* Block the PHY control access. */
910 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
911 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
912
913 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
914 if (!err)
915 break;
916 } while (--retries);
917
918 err = tg3_phy_reset_chanpat(tp);
919 if (err)
920 return err;
921
922 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
923 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
926 tg3_writephy(tp, 0x16, 0x0000);
927
928 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
929 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
930 /* Set Extended packet length bit for jumbo frames */
931 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
932 }
933 else {
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
935 }
936
937 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
938
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
942 } else if (!err)
943 err = -EBUSY;
944
945 return err;
946 }
947
948 static void tg3_link_report(struct tg3 *);
949
950 /* This will reset the tigon3 PHY if there is no valid
951 * link unless the FORCE argument is non-zero.
952 */
953 static int tg3_phy_reset(struct tg3 *tp)
954 {
955 u32 phy_status;
956 int err;
957
958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
959 u32 val;
960
961 val = tr32(GRC_MISC_CFG);
962 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
963 udelay(40);
964 }
965 err = tg3_readphy(tp, MII_BMSR, &phy_status);
966 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
967 if (err != 0)
968 return -EBUSY;
969
970 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
971 netif_carrier_off(tp->dev);
972 tg3_link_report(tp);
973 }
974
975 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
976 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
978 err = tg3_phy_reset_5703_4_5(tp);
979 if (err)
980 return err;
981 goto out;
982 }
983
984 err = tg3_bmcr_reset(tp);
985 if (err)
986 return err;
987
988 out:
989 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
990 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
991 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
992 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
993 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
994 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
995 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
998 tg3_writephy(tp, 0x1c, 0x8d68);
999 tg3_writephy(tp, 0x1c, 0x8d68);
1000 }
1001 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010 }
1011 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016 tg3_writephy(tp, MII_TG3_TEST1,
1017 MII_TG3_TEST1_TRIM_EN | 0x4);
1018 } else
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021 }
1022 /* Set Extended packet length bit (bit 14) on all chips that */
1023 /* support jumbo frames */
1024 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025 /* Cannot do read-modify-write on 5401 */
1026 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028 u32 phy_reg;
1029
1030 /* Set bit 14 with read-modify-write to preserve other bits */
1031 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034 }
1035
1036 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037 * jumbo frames transmission.
1038 */
1039 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040 u32 phy_reg;
1041
1042 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045 }
1046
1047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048 u32 phy_reg;
1049
1050 /* adjust output voltage */
1051 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054 u32 phy_reg2;
1055
1056 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058 /* Enable auto-MDIX */
1059 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062 }
1063 }
1064
1065 tg3_phy_set_wirespeed(tp);
1066 return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071 struct tg3 *tp_peer = tp;
1072
1073 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074 return;
1075
1076 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078 struct net_device *dev_peer;
1079
1080 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081 /* remove_one() may have been run on the peer. */
1082 if (!dev_peer)
1083 tp_peer = tp;
1084 else
1085 tp_peer = netdev_priv(dev_peer);
1086 }
1087
1088 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE0 |
1096 GRC_LCLCTRL_GPIO_OE1 |
1097 GRC_LCLCTRL_GPIO_OE2 |
1098 GRC_LCLCTRL_GPIO_OUTPUT0 |
1099 GRC_LCLCTRL_GPIO_OUTPUT1),
1100 100);
1101 } else {
1102 u32 no_gpio2;
1103 u32 grc_local_ctrl = 0;
1104
1105 if (tp_peer != tp &&
1106 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107 return;
1108
1109 /* Workaround to prevent overdrawing Amps. */
1110 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111 ASIC_REV_5714) {
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114 grc_local_ctrl, 100);
1115 }
1116
1117 /* On 5753 and variants, GPIO2 cannot be used. */
1118 no_gpio2 = tp->nic_sram_data_cfg &
1119 NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT1 |
1125 GRC_LCLCTRL_GPIO_OUTPUT2;
1126 if (no_gpio2) {
1127 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128 GRC_LCLCTRL_GPIO_OUTPUT2);
1129 }
1130 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131 grc_local_ctrl, 100);
1132
1133 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136 grc_local_ctrl, 100);
1137
1138 if (!no_gpio2) {
1139 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141 grc_local_ctrl, 100);
1142 }
1143 }
1144 } else {
1145 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147 if (tp_peer != tp &&
1148 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149 return;
1150
1151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152 (GRC_LCLCTRL_GPIO_OE1 |
1153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156 GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159 (GRC_LCLCTRL_GPIO_OE1 |
1160 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161 }
1162 }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN 0
1168 #define RESET_KIND_INIT 1
1169 #define RESET_KIND_SUSPEND 2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183 sg_dig_ctrl |=
1184 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187 }
1188 return;
1189 }
1190
1191 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192 u32 val;
1193
1194 tg3_bmcr_reset(tp);
1195 val = tr32(GRC_MISC_CFG);
1196 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197 udelay(40);
1198 return;
1199 } else {
1200 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203 }
1204
1205 /* The PHY should not be powered down on some chips because
1206 * of bugs.
1207 */
1208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212 return;
1213 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218 u32 misc_host_ctrl;
1219 u16 power_control, power_caps;
1220 int pm = tp->pm_cap;
1221
1222 /* Make sure register accesses (indirect or otherwise)
1223 * will function correctly.
1224 */
1225 pci_write_config_dword(tp->pdev,
1226 TG3PCI_MISC_HOST_CTRL,
1227 tp->misc_host_ctrl);
1228
1229 pci_read_config_word(tp->pdev,
1230 pm + PCI_PM_CTRL,
1231 &power_control);
1232 power_control |= PCI_PM_CTRL_PME_STATUS;
1233 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234 switch (state) {
1235 case PCI_D0:
1236 power_control |= 0;
1237 pci_write_config_word(tp->pdev,
1238 pm + PCI_PM_CTRL,
1239 power_control);
1240 udelay(100); /* Delay after power state change */
1241
1242 /* Switch out of Vaux if it is a NIC */
1243 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246 return 0;
1247
1248 case PCI_D1:
1249 power_control |= 1;
1250 break;
1251
1252 case PCI_D2:
1253 power_control |= 2;
1254 break;
1255
1256 case PCI_D3hot:
1257 power_control |= 3;
1258 break;
1259
1260 default:
1261 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262 "requested.\n",
1263 tp->dev->name, state);
1264 return -EINVAL;
1265 };
1266
1267 power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270 tw32(TG3PCI_MISC_HOST_CTRL,
1271 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273 if (tp->link_config.phy_is_low_power == 0) {
1274 tp->link_config.phy_is_low_power = 1;
1275 tp->link_config.orig_speed = tp->link_config.speed;
1276 tp->link_config.orig_duplex = tp->link_config.duplex;
1277 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278 }
1279
1280 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281 tp->link_config.speed = SPEED_10;
1282 tp->link_config.duplex = DUPLEX_HALF;
1283 tp->link_config.autoneg = AUTONEG_ENABLE;
1284 tg3_setup_phy(tp, 0);
1285 }
1286
1287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288 u32 val;
1289
1290 val = tr32(GRC_VCPU_EXT_CTRL);
1291 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293 int i;
1294 u32 val;
1295
1296 for (i = 0; i < 200; i++) {
1297 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299 break;
1300 msleep(1);
1301 }
1302 }
1303 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305 WOL_DRV_STATE_SHUTDOWN |
1306 WOL_DRV_WOL |
1307 WOL_SET_MAGIC_PKT);
1308
1309 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1310
1311 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1312 u32 mac_mode;
1313
1314 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1315 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1316 udelay(40);
1317
1318 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1319 mac_mode = MAC_MODE_PORT_MODE_GMII;
1320 else
1321 mac_mode = MAC_MODE_PORT_MODE_MII;
1322
1323 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1324 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1325 mac_mode |= MAC_MODE_LINK_POLARITY;
1326 } else {
1327 mac_mode = MAC_MODE_PORT_MODE_TBI;
1328 }
1329
1330 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1331 tw32(MAC_LED_CTRL, tp->led_ctrl);
1332
1333 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1334 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1335 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1336
1337 tw32_f(MAC_MODE, mac_mode);
1338 udelay(100);
1339
1340 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1341 udelay(10);
1342 }
1343
1344 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1345 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1347 u32 base_val;
1348
1349 base_val = tp->pci_clock_ctrl;
1350 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1351 CLOCK_CTRL_TXCLK_DISABLE);
1352
1353 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1354 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1355 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1356 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1357 /* do nothing */
1358 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1359 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1360 u32 newbits1, newbits2;
1361
1362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1364 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1365 CLOCK_CTRL_TXCLK_DISABLE |
1366 CLOCK_CTRL_ALTCLK);
1367 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1368 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1369 newbits1 = CLOCK_CTRL_625_CORE;
1370 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1371 } else {
1372 newbits1 = CLOCK_CTRL_ALTCLK;
1373 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1374 }
1375
1376 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1377 40);
1378
1379 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1380 40);
1381
1382 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1383 u32 newbits3;
1384
1385 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1386 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1387 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1388 CLOCK_CTRL_TXCLK_DISABLE |
1389 CLOCK_CTRL_44MHZ_CORE);
1390 } else {
1391 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1392 }
1393
1394 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1395 tp->pci_clock_ctrl | newbits3, 40);
1396 }
1397 }
1398
1399 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1400 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1401 tg3_power_down_phy(tp);
1402
1403 tg3_frob_aux_power(tp);
1404
1405 /* Workaround for unstable PLL clock */
1406 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1407 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1408 u32 val = tr32(0x7d00);
1409
1410 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1411 tw32(0x7d00, val);
1412 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1413 int err;
1414
1415 err = tg3_nvram_lock(tp);
1416 tg3_halt_cpu(tp, RX_CPU_BASE);
1417 if (!err)
1418 tg3_nvram_unlock(tp);
1419 }
1420 }
1421
1422 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1423
1424 /* Finally, set the new power state. */
1425 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1426 udelay(100); /* Delay after power state change */
1427
1428 return 0;
1429 }
1430
1431 static void tg3_link_report(struct tg3 *tp)
1432 {
1433 if (!netif_carrier_ok(tp->dev)) {
1434 if (netif_msg_link(tp))
1435 printk(KERN_INFO PFX "%s: Link is down.\n",
1436 tp->dev->name);
1437 } else if (netif_msg_link(tp)) {
1438 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1439 tp->dev->name,
1440 (tp->link_config.active_speed == SPEED_1000 ?
1441 1000 :
1442 (tp->link_config.active_speed == SPEED_100 ?
1443 100 : 10)),
1444 (tp->link_config.active_duplex == DUPLEX_FULL ?
1445 "full" : "half"));
1446
1447 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1448 "%s for RX.\n",
1449 tp->dev->name,
1450 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1451 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1452 }
1453 }
1454
1455 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1456 {
1457 u32 new_tg3_flags = 0;
1458 u32 old_rx_mode = tp->rx_mode;
1459 u32 old_tx_mode = tp->tx_mode;
1460
1461 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1462
1463 /* Convert 1000BaseX flow control bits to 1000BaseT
1464 * bits before resolving flow control.
1465 */
1466 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1467 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1468 ADVERTISE_PAUSE_ASYM);
1469 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1470
1471 if (local_adv & ADVERTISE_1000XPAUSE)
1472 local_adv |= ADVERTISE_PAUSE_CAP;
1473 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1474 local_adv |= ADVERTISE_PAUSE_ASYM;
1475 if (remote_adv & LPA_1000XPAUSE)
1476 remote_adv |= LPA_PAUSE_CAP;
1477 if (remote_adv & LPA_1000XPAUSE_ASYM)
1478 remote_adv |= LPA_PAUSE_ASYM;
1479 }
1480
1481 if (local_adv & ADVERTISE_PAUSE_CAP) {
1482 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1483 if (remote_adv & LPA_PAUSE_CAP)
1484 new_tg3_flags |=
1485 (TG3_FLAG_RX_PAUSE |
1486 TG3_FLAG_TX_PAUSE);
1487 else if (remote_adv & LPA_PAUSE_ASYM)
1488 new_tg3_flags |=
1489 (TG3_FLAG_RX_PAUSE);
1490 } else {
1491 if (remote_adv & LPA_PAUSE_CAP)
1492 new_tg3_flags |=
1493 (TG3_FLAG_RX_PAUSE |
1494 TG3_FLAG_TX_PAUSE);
1495 }
1496 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1497 if ((remote_adv & LPA_PAUSE_CAP) &&
1498 (remote_adv & LPA_PAUSE_ASYM))
1499 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1500 }
1501
1502 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1503 tp->tg3_flags |= new_tg3_flags;
1504 } else {
1505 new_tg3_flags = tp->tg3_flags;
1506 }
1507
1508 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1509 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1510 else
1511 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1512
1513 if (old_rx_mode != tp->rx_mode) {
1514 tw32_f(MAC_RX_MODE, tp->rx_mode);
1515 }
1516
1517 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1518 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1519 else
1520 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1521
1522 if (old_tx_mode != tp->tx_mode) {
1523 tw32_f(MAC_TX_MODE, tp->tx_mode);
1524 }
1525 }
1526
1527 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1528 {
1529 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1530 case MII_TG3_AUX_STAT_10HALF:
1531 *speed = SPEED_10;
1532 *duplex = DUPLEX_HALF;
1533 break;
1534
1535 case MII_TG3_AUX_STAT_10FULL:
1536 *speed = SPEED_10;
1537 *duplex = DUPLEX_FULL;
1538 break;
1539
1540 case MII_TG3_AUX_STAT_100HALF:
1541 *speed = SPEED_100;
1542 *duplex = DUPLEX_HALF;
1543 break;
1544
1545 case MII_TG3_AUX_STAT_100FULL:
1546 *speed = SPEED_100;
1547 *duplex = DUPLEX_FULL;
1548 break;
1549
1550 case MII_TG3_AUX_STAT_1000HALF:
1551 *speed = SPEED_1000;
1552 *duplex = DUPLEX_HALF;
1553 break;
1554
1555 case MII_TG3_AUX_STAT_1000FULL:
1556 *speed = SPEED_1000;
1557 *duplex = DUPLEX_FULL;
1558 break;
1559
1560 default:
1561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1562 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1563 SPEED_10;
1564 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1565 DUPLEX_HALF;
1566 break;
1567 }
1568 *speed = SPEED_INVALID;
1569 *duplex = DUPLEX_INVALID;
1570 break;
1571 };
1572 }
1573
1574 static void tg3_phy_copper_begin(struct tg3 *tp)
1575 {
1576 u32 new_adv;
1577 int i;
1578
1579 if (tp->link_config.phy_is_low_power) {
1580 /* Entering low power mode. Disable gigabit and
1581 * 100baseT advertisements.
1582 */
1583 tg3_writephy(tp, MII_TG3_CTRL, 0);
1584
1585 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1586 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1587 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1588 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1589
1590 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1591 } else if (tp->link_config.speed == SPEED_INVALID) {
1592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1593 tp->link_config.advertising &=
1594 ~(ADVERTISED_1000baseT_Half |
1595 ADVERTISED_1000baseT_Full);
1596
1597 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1598 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1599 new_adv |= ADVERTISE_10HALF;
1600 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1601 new_adv |= ADVERTISE_10FULL;
1602 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1603 new_adv |= ADVERTISE_100HALF;
1604 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1605 new_adv |= ADVERTISE_100FULL;
1606 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1607
1608 if (tp->link_config.advertising &
1609 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1610 new_adv = 0;
1611 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1612 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1613 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1614 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1615 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1616 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1617 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1618 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1619 MII_TG3_CTRL_ENABLE_AS_MASTER);
1620 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1621 } else {
1622 tg3_writephy(tp, MII_TG3_CTRL, 0);
1623 }
1624 } else {
1625 /* Asking for a specific link mode. */
1626 if (tp->link_config.speed == SPEED_1000) {
1627 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1628 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629
1630 if (tp->link_config.duplex == DUPLEX_FULL)
1631 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1632 else
1633 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1634 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1635 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1636 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1637 MII_TG3_CTRL_ENABLE_AS_MASTER);
1638 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1639 } else {
1640 tg3_writephy(tp, MII_TG3_CTRL, 0);
1641
1642 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1643 if (tp->link_config.speed == SPEED_100) {
1644 if (tp->link_config.duplex == DUPLEX_FULL)
1645 new_adv |= ADVERTISE_100FULL;
1646 else
1647 new_adv |= ADVERTISE_100HALF;
1648 } else {
1649 if (tp->link_config.duplex == DUPLEX_FULL)
1650 new_adv |= ADVERTISE_10FULL;
1651 else
1652 new_adv |= ADVERTISE_10HALF;
1653 }
1654 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 }
1656 }
1657
1658 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1659 tp->link_config.speed != SPEED_INVALID) {
1660 u32 bmcr, orig_bmcr;
1661
1662 tp->link_config.active_speed = tp->link_config.speed;
1663 tp->link_config.active_duplex = tp->link_config.duplex;
1664
1665 bmcr = 0;
1666 switch (tp->link_config.speed) {
1667 default:
1668 case SPEED_10:
1669 break;
1670
1671 case SPEED_100:
1672 bmcr |= BMCR_SPEED100;
1673 break;
1674
1675 case SPEED_1000:
1676 bmcr |= TG3_BMCR_SPEED1000;
1677 break;
1678 };
1679
1680 if (tp->link_config.duplex == DUPLEX_FULL)
1681 bmcr |= BMCR_FULLDPLX;
1682
1683 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1684 (bmcr != orig_bmcr)) {
1685 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1686 for (i = 0; i < 1500; i++) {
1687 u32 tmp;
1688
1689 udelay(10);
1690 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1691 tg3_readphy(tp, MII_BMSR, &tmp))
1692 continue;
1693 if (!(tmp & BMSR_LSTATUS)) {
1694 udelay(40);
1695 break;
1696 }
1697 }
1698 tg3_writephy(tp, MII_BMCR, bmcr);
1699 udelay(40);
1700 }
1701 } else {
1702 tg3_writephy(tp, MII_BMCR,
1703 BMCR_ANENABLE | BMCR_ANRESTART);
1704 }
1705 }
1706
1707 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1708 {
1709 int err;
1710
1711 /* Turn off tap power management. */
1712 /* Set Extended packet length bit */
1713 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1714
1715 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1716 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1717
1718 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1719 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1720
1721 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1722 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1723
1724 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1725 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1726
1727 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1728 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1729
1730 udelay(40);
1731
1732 return err;
1733 }
1734
1735 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1736 {
1737 u32 adv_reg, all_mask = 0;
1738
1739 if (mask & ADVERTISED_10baseT_Half)
1740 all_mask |= ADVERTISE_10HALF;
1741 if (mask & ADVERTISED_10baseT_Full)
1742 all_mask |= ADVERTISE_10FULL;
1743 if (mask & ADVERTISED_100baseT_Half)
1744 all_mask |= ADVERTISE_100HALF;
1745 if (mask & ADVERTISED_100baseT_Full)
1746 all_mask |= ADVERTISE_100FULL;
1747
1748 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1749 return 0;
1750
1751 if ((adv_reg & all_mask) != all_mask)
1752 return 0;
1753 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1754 u32 tg3_ctrl;
1755
1756 all_mask = 0;
1757 if (mask & ADVERTISED_1000baseT_Half)
1758 all_mask |= ADVERTISE_1000HALF;
1759 if (mask & ADVERTISED_1000baseT_Full)
1760 all_mask |= ADVERTISE_1000FULL;
1761
1762 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1763 return 0;
1764
1765 if ((tg3_ctrl & all_mask) != all_mask)
1766 return 0;
1767 }
1768 return 1;
1769 }
1770
1771 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1772 {
1773 int current_link_up;
1774 u32 bmsr, dummy;
1775 u16 current_speed;
1776 u8 current_duplex;
1777 int i, err;
1778
1779 tw32(MAC_EVENT, 0);
1780
1781 tw32_f(MAC_STATUS,
1782 (MAC_STATUS_SYNC_CHANGED |
1783 MAC_STATUS_CFG_CHANGED |
1784 MAC_STATUS_MI_COMPLETION |
1785 MAC_STATUS_LNKSTATE_CHANGED));
1786 udelay(40);
1787
1788 tp->mi_mode = MAC_MI_MODE_BASE;
1789 tw32_f(MAC_MI_MODE, tp->mi_mode);
1790 udelay(80);
1791
1792 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1793
1794 /* Some third-party PHYs need to be reset on link going
1795 * down.
1796 */
1797 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1798 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1800 netif_carrier_ok(tp->dev)) {
1801 tg3_readphy(tp, MII_BMSR, &bmsr);
1802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1803 !(bmsr & BMSR_LSTATUS))
1804 force_reset = 1;
1805 }
1806 if (force_reset)
1807 tg3_phy_reset(tp);
1808
1809 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1810 tg3_readphy(tp, MII_BMSR, &bmsr);
1811 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1812 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1813 bmsr = 0;
1814
1815 if (!(bmsr & BMSR_LSTATUS)) {
1816 err = tg3_init_5401phy_dsp(tp);
1817 if (err)
1818 return err;
1819
1820 tg3_readphy(tp, MII_BMSR, &bmsr);
1821 for (i = 0; i < 1000; i++) {
1822 udelay(10);
1823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1824 (bmsr & BMSR_LSTATUS)) {
1825 udelay(40);
1826 break;
1827 }
1828 }
1829
1830 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1831 !(bmsr & BMSR_LSTATUS) &&
1832 tp->link_config.active_speed == SPEED_1000) {
1833 err = tg3_phy_reset(tp);
1834 if (!err)
1835 err = tg3_init_5401phy_dsp(tp);
1836 if (err)
1837 return err;
1838 }
1839 }
1840 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1841 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1842 /* 5701 {A0,B0} CRC bug workaround */
1843 tg3_writephy(tp, 0x15, 0x0a75);
1844 tg3_writephy(tp, 0x1c, 0x8c68);
1845 tg3_writephy(tp, 0x1c, 0x8d68);
1846 tg3_writephy(tp, 0x1c, 0x8c68);
1847 }
1848
1849 /* Clear pending interrupts... */
1850 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1851 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1852
1853 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1855 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1856 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1857
1858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1861 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1862 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1863 else
1864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1865 }
1866
1867 current_link_up = 0;
1868 current_speed = SPEED_INVALID;
1869 current_duplex = DUPLEX_INVALID;
1870
1871 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1872 u32 val;
1873
1874 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1875 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1876 if (!(val & (1 << 10))) {
1877 val |= (1 << 10);
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1879 goto relink;
1880 }
1881 }
1882
1883 bmsr = 0;
1884 for (i = 0; i < 100; i++) {
1885 tg3_readphy(tp, MII_BMSR, &bmsr);
1886 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1887 (bmsr & BMSR_LSTATUS))
1888 break;
1889 udelay(40);
1890 }
1891
1892 if (bmsr & BMSR_LSTATUS) {
1893 u32 aux_stat, bmcr;
1894
1895 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1896 for (i = 0; i < 2000; i++) {
1897 udelay(10);
1898 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1899 aux_stat)
1900 break;
1901 }
1902
1903 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1904 &current_speed,
1905 &current_duplex);
1906
1907 bmcr = 0;
1908 for (i = 0; i < 200; i++) {
1909 tg3_readphy(tp, MII_BMCR, &bmcr);
1910 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1911 continue;
1912 if (bmcr && bmcr != 0x7fff)
1913 break;
1914 udelay(10);
1915 }
1916
1917 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1918 if (bmcr & BMCR_ANENABLE) {
1919 current_link_up = 1;
1920
1921 /* Force autoneg restart if we are exiting
1922 * low power mode.
1923 */
1924 if (!tg3_copper_is_advertising_all(tp,
1925 tp->link_config.advertising))
1926 current_link_up = 0;
1927 } else {
1928 current_link_up = 0;
1929 }
1930 } else {
1931 if (!(bmcr & BMCR_ANENABLE) &&
1932 tp->link_config.speed == current_speed &&
1933 tp->link_config.duplex == current_duplex) {
1934 current_link_up = 1;
1935 } else {
1936 current_link_up = 0;
1937 }
1938 }
1939
1940 tp->link_config.active_speed = current_speed;
1941 tp->link_config.active_duplex = current_duplex;
1942 }
1943
1944 if (current_link_up == 1 &&
1945 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1946 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1947 u32 local_adv, remote_adv;
1948
1949 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1950 local_adv = 0;
1951 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1952
1953 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1954 remote_adv = 0;
1955
1956 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1957
1958 /* If we are not advertising full pause capability,
1959 * something is wrong. Bring the link down and reconfigure.
1960 */
1961 if (local_adv != ADVERTISE_PAUSE_CAP) {
1962 current_link_up = 0;
1963 } else {
1964 tg3_setup_flow_control(tp, local_adv, remote_adv);
1965 }
1966 }
1967 relink:
1968 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1969 u32 tmp;
1970
1971 tg3_phy_copper_begin(tp);
1972
1973 tg3_readphy(tp, MII_BMSR, &tmp);
1974 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1975 (tmp & BMSR_LSTATUS))
1976 current_link_up = 1;
1977 }
1978
1979 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1980 if (current_link_up == 1) {
1981 if (tp->link_config.active_speed == SPEED_100 ||
1982 tp->link_config.active_speed == SPEED_10)
1983 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1984 else
1985 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986 } else
1987 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1988
1989 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1990 if (tp->link_config.active_duplex == DUPLEX_HALF)
1991 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1992
1993 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1995 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1996 (current_link_up == 1 &&
1997 tp->link_config.active_speed == SPEED_10))
1998 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1999 } else {
2000 if (current_link_up == 1)
2001 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2002 }
2003
2004 /* ??? Without this setting Netgear GA302T PHY does not
2005 * ??? send/receive packets...
2006 */
2007 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2008 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2009 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2010 tw32_f(MAC_MI_MODE, tp->mi_mode);
2011 udelay(80);
2012 }
2013
2014 tw32_f(MAC_MODE, tp->mac_mode);
2015 udelay(40);
2016
2017 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2018 /* Polled via timer. */
2019 tw32_f(MAC_EVENT, 0);
2020 } else {
2021 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2022 }
2023 udelay(40);
2024
2025 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2026 current_link_up == 1 &&
2027 tp->link_config.active_speed == SPEED_1000 &&
2028 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2029 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2030 udelay(120);
2031 tw32_f(MAC_STATUS,
2032 (MAC_STATUS_SYNC_CHANGED |
2033 MAC_STATUS_CFG_CHANGED));
2034 udelay(40);
2035 tg3_write_mem(tp,
2036 NIC_SRAM_FIRMWARE_MBOX,
2037 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2038 }
2039
2040 if (current_link_up != netif_carrier_ok(tp->dev)) {
2041 if (current_link_up)
2042 netif_carrier_on(tp->dev);
2043 else
2044 netif_carrier_off(tp->dev);
2045 tg3_link_report(tp);
2046 }
2047
2048 return 0;
2049 }
2050
2051 struct tg3_fiber_aneginfo {
2052 int state;
2053 #define ANEG_STATE_UNKNOWN 0
2054 #define ANEG_STATE_AN_ENABLE 1
2055 #define ANEG_STATE_RESTART_INIT 2
2056 #define ANEG_STATE_RESTART 3
2057 #define ANEG_STATE_DISABLE_LINK_OK 4
2058 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2059 #define ANEG_STATE_ABILITY_DETECT 6
2060 #define ANEG_STATE_ACK_DETECT_INIT 7
2061 #define ANEG_STATE_ACK_DETECT 8
2062 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2063 #define ANEG_STATE_COMPLETE_ACK 10
2064 #define ANEG_STATE_IDLE_DETECT_INIT 11
2065 #define ANEG_STATE_IDLE_DETECT 12
2066 #define ANEG_STATE_LINK_OK 13
2067 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2068 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2069
2070 u32 flags;
2071 #define MR_AN_ENABLE 0x00000001
2072 #define MR_RESTART_AN 0x00000002
2073 #define MR_AN_COMPLETE 0x00000004
2074 #define MR_PAGE_RX 0x00000008
2075 #define MR_NP_LOADED 0x00000010
2076 #define MR_TOGGLE_TX 0x00000020
2077 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2078 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2079 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2080 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2081 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2082 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2083 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2084 #define MR_TOGGLE_RX 0x00002000
2085 #define MR_NP_RX 0x00004000
2086
2087 #define MR_LINK_OK 0x80000000
2088
2089 unsigned long link_time, cur_time;
2090
2091 u32 ability_match_cfg;
2092 int ability_match_count;
2093
2094 char ability_match, idle_match, ack_match;
2095
2096 u32 txconfig, rxconfig;
2097 #define ANEG_CFG_NP 0x00000080
2098 #define ANEG_CFG_ACK 0x00000040
2099 #define ANEG_CFG_RF2 0x00000020
2100 #define ANEG_CFG_RF1 0x00000010
2101 #define ANEG_CFG_PS2 0x00000001
2102 #define ANEG_CFG_PS1 0x00008000
2103 #define ANEG_CFG_HD 0x00004000
2104 #define ANEG_CFG_FD 0x00002000
2105 #define ANEG_CFG_INVAL 0x00001f06
2106
2107 };
2108 #define ANEG_OK 0
2109 #define ANEG_DONE 1
2110 #define ANEG_TIMER_ENAB 2
2111 #define ANEG_FAILED -1
2112
2113 #define ANEG_STATE_SETTLE_TIME 10000
2114
2115 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2116 struct tg3_fiber_aneginfo *ap)
2117 {
2118 unsigned long delta;
2119 u32 rx_cfg_reg;
2120 int ret;
2121
2122 if (ap->state == ANEG_STATE_UNKNOWN) {
2123 ap->rxconfig = 0;
2124 ap->link_time = 0;
2125 ap->cur_time = 0;
2126 ap->ability_match_cfg = 0;
2127 ap->ability_match_count = 0;
2128 ap->ability_match = 0;
2129 ap->idle_match = 0;
2130 ap->ack_match = 0;
2131 }
2132 ap->cur_time++;
2133
2134 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2135 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2136
2137 if (rx_cfg_reg != ap->ability_match_cfg) {
2138 ap->ability_match_cfg = rx_cfg_reg;
2139 ap->ability_match = 0;
2140 ap->ability_match_count = 0;
2141 } else {
2142 if (++ap->ability_match_count > 1) {
2143 ap->ability_match = 1;
2144 ap->ability_match_cfg = rx_cfg_reg;
2145 }
2146 }
2147 if (rx_cfg_reg & ANEG_CFG_ACK)
2148 ap->ack_match = 1;
2149 else
2150 ap->ack_match = 0;
2151
2152 ap->idle_match = 0;
2153 } else {
2154 ap->idle_match = 1;
2155 ap->ability_match_cfg = 0;
2156 ap->ability_match_count = 0;
2157 ap->ability_match = 0;
2158 ap->ack_match = 0;
2159
2160 rx_cfg_reg = 0;
2161 }
2162
2163 ap->rxconfig = rx_cfg_reg;
2164 ret = ANEG_OK;
2165
2166 switch(ap->state) {
2167 case ANEG_STATE_UNKNOWN:
2168 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2169 ap->state = ANEG_STATE_AN_ENABLE;
2170
2171 /* fallthru */
2172 case ANEG_STATE_AN_ENABLE:
2173 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2174 if (ap->flags & MR_AN_ENABLE) {
2175 ap->link_time = 0;
2176 ap->cur_time = 0;
2177 ap->ability_match_cfg = 0;
2178 ap->ability_match_count = 0;
2179 ap->ability_match = 0;
2180 ap->idle_match = 0;
2181 ap->ack_match = 0;
2182
2183 ap->state = ANEG_STATE_RESTART_INIT;
2184 } else {
2185 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2186 }
2187 break;
2188
2189 case ANEG_STATE_RESTART_INIT:
2190 ap->link_time = ap->cur_time;
2191 ap->flags &= ~(MR_NP_LOADED);
2192 ap->txconfig = 0;
2193 tw32(MAC_TX_AUTO_NEG, 0);
2194 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2195 tw32_f(MAC_MODE, tp->mac_mode);
2196 udelay(40);
2197
2198 ret = ANEG_TIMER_ENAB;
2199 ap->state = ANEG_STATE_RESTART;
2200
2201 /* fallthru */
2202 case ANEG_STATE_RESTART:
2203 delta = ap->cur_time - ap->link_time;
2204 if (delta > ANEG_STATE_SETTLE_TIME) {
2205 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2206 } else {
2207 ret = ANEG_TIMER_ENAB;
2208 }
2209 break;
2210
2211 case ANEG_STATE_DISABLE_LINK_OK:
2212 ret = ANEG_DONE;
2213 break;
2214
2215 case ANEG_STATE_ABILITY_DETECT_INIT:
2216 ap->flags &= ~(MR_TOGGLE_TX);
2217 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2218 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2219 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2220 tw32_f(MAC_MODE, tp->mac_mode);
2221 udelay(40);
2222
2223 ap->state = ANEG_STATE_ABILITY_DETECT;
2224 break;
2225
2226 case ANEG_STATE_ABILITY_DETECT:
2227 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2228 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2229 }
2230 break;
2231
2232 case ANEG_STATE_ACK_DETECT_INIT:
2233 ap->txconfig |= ANEG_CFG_ACK;
2234 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2236 tw32_f(MAC_MODE, tp->mac_mode);
2237 udelay(40);
2238
2239 ap->state = ANEG_STATE_ACK_DETECT;
2240
2241 /* fallthru */
2242 case ANEG_STATE_ACK_DETECT:
2243 if (ap->ack_match != 0) {
2244 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2245 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2246 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2247 } else {
2248 ap->state = ANEG_STATE_AN_ENABLE;
2249 }
2250 } else if (ap->ability_match != 0 &&
2251 ap->rxconfig == 0) {
2252 ap->state = ANEG_STATE_AN_ENABLE;
2253 }
2254 break;
2255
2256 case ANEG_STATE_COMPLETE_ACK_INIT:
2257 if (ap->rxconfig & ANEG_CFG_INVAL) {
2258 ret = ANEG_FAILED;
2259 break;
2260 }
2261 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2262 MR_LP_ADV_HALF_DUPLEX |
2263 MR_LP_ADV_SYM_PAUSE |
2264 MR_LP_ADV_ASYM_PAUSE |
2265 MR_LP_ADV_REMOTE_FAULT1 |
2266 MR_LP_ADV_REMOTE_FAULT2 |
2267 MR_LP_ADV_NEXT_PAGE |
2268 MR_TOGGLE_RX |
2269 MR_NP_RX);
2270 if (ap->rxconfig & ANEG_CFG_FD)
2271 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2272 if (ap->rxconfig & ANEG_CFG_HD)
2273 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2274 if (ap->rxconfig & ANEG_CFG_PS1)
2275 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2276 if (ap->rxconfig & ANEG_CFG_PS2)
2277 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2278 if (ap->rxconfig & ANEG_CFG_RF1)
2279 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2280 if (ap->rxconfig & ANEG_CFG_RF2)
2281 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2282 if (ap->rxconfig & ANEG_CFG_NP)
2283 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2284
2285 ap->link_time = ap->cur_time;
2286
2287 ap->flags ^= (MR_TOGGLE_TX);
2288 if (ap->rxconfig & 0x0008)
2289 ap->flags |= MR_TOGGLE_RX;
2290 if (ap->rxconfig & ANEG_CFG_NP)
2291 ap->flags |= MR_NP_RX;
2292 ap->flags |= MR_PAGE_RX;
2293
2294 ap->state = ANEG_STATE_COMPLETE_ACK;
2295 ret = ANEG_TIMER_ENAB;
2296 break;
2297
2298 case ANEG_STATE_COMPLETE_ACK:
2299 if (ap->ability_match != 0 &&
2300 ap->rxconfig == 0) {
2301 ap->state = ANEG_STATE_AN_ENABLE;
2302 break;
2303 }
2304 delta = ap->cur_time - ap->link_time;
2305 if (delta > ANEG_STATE_SETTLE_TIME) {
2306 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2307 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2308 } else {
2309 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2310 !(ap->flags & MR_NP_RX)) {
2311 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2312 } else {
2313 ret = ANEG_FAILED;
2314 }
2315 }
2316 }
2317 break;
2318
2319 case ANEG_STATE_IDLE_DETECT_INIT:
2320 ap->link_time = ap->cur_time;
2321 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2322 tw32_f(MAC_MODE, tp->mac_mode);
2323 udelay(40);
2324
2325 ap->state = ANEG_STATE_IDLE_DETECT;
2326 ret = ANEG_TIMER_ENAB;
2327 break;
2328
2329 case ANEG_STATE_IDLE_DETECT:
2330 if (ap->ability_match != 0 &&
2331 ap->rxconfig == 0) {
2332 ap->state = ANEG_STATE_AN_ENABLE;
2333 break;
2334 }
2335 delta = ap->cur_time - ap->link_time;
2336 if (delta > ANEG_STATE_SETTLE_TIME) {
2337 /* XXX another gem from the Broadcom driver :( */
2338 ap->state = ANEG_STATE_LINK_OK;
2339 }
2340 break;
2341
2342 case ANEG_STATE_LINK_OK:
2343 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2344 ret = ANEG_DONE;
2345 break;
2346
2347 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2348 /* ??? unimplemented */
2349 break;
2350
2351 case ANEG_STATE_NEXT_PAGE_WAIT:
2352 /* ??? unimplemented */
2353 break;
2354
2355 default:
2356 ret = ANEG_FAILED;
2357 break;
2358 };
2359
2360 return ret;
2361 }
2362
2363 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2364 {
2365 int res = 0;
2366 struct tg3_fiber_aneginfo aninfo;
2367 int status = ANEG_FAILED;
2368 unsigned int tick;
2369 u32 tmp;
2370
2371 tw32_f(MAC_TX_AUTO_NEG, 0);
2372
2373 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2374 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2375 udelay(40);
2376
2377 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2378 udelay(40);
2379
2380 memset(&aninfo, 0, sizeof(aninfo));
2381 aninfo.flags |= MR_AN_ENABLE;
2382 aninfo.state = ANEG_STATE_UNKNOWN;
2383 aninfo.cur_time = 0;
2384 tick = 0;
2385 while (++tick < 195000) {
2386 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2387 if (status == ANEG_DONE || status == ANEG_FAILED)
2388 break;
2389
2390 udelay(1);
2391 }
2392
2393 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2394 tw32_f(MAC_MODE, tp->mac_mode);
2395 udelay(40);
2396
2397 *flags = aninfo.flags;
2398
2399 if (status == ANEG_DONE &&
2400 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2401 MR_LP_ADV_FULL_DUPLEX)))
2402 res = 1;
2403
2404 return res;
2405 }
2406
2407 static void tg3_init_bcm8002(struct tg3 *tp)
2408 {
2409 u32 mac_status = tr32(MAC_STATUS);
2410 int i;
2411
2412 /* Reset when initting first time or we have a link. */
2413 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2414 !(mac_status & MAC_STATUS_PCS_SYNCED))
2415 return;
2416
2417 /* Set PLL lock range. */
2418 tg3_writephy(tp, 0x16, 0x8007);
2419
2420 /* SW reset */
2421 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2422
2423 /* Wait for reset to complete. */
2424 /* XXX schedule_timeout() ... */
2425 for (i = 0; i < 500; i++)
2426 udelay(10);
2427
2428 /* Config mode; select PMA/Ch 1 regs. */
2429 tg3_writephy(tp, 0x10, 0x8411);
2430
2431 /* Enable auto-lock and comdet, select txclk for tx. */
2432 tg3_writephy(tp, 0x11, 0x0a10);
2433
2434 tg3_writephy(tp, 0x18, 0x00a0);
2435 tg3_writephy(tp, 0x16, 0x41ff);
2436
2437 /* Assert and deassert POR. */
2438 tg3_writephy(tp, 0x13, 0x0400);
2439 udelay(40);
2440 tg3_writephy(tp, 0x13, 0x0000);
2441
2442 tg3_writephy(tp, 0x11, 0x0a50);
2443 udelay(40);
2444 tg3_writephy(tp, 0x11, 0x0a10);
2445
2446 /* Wait for signal to stabilize */
2447 /* XXX schedule_timeout() ... */
2448 for (i = 0; i < 15000; i++)
2449 udelay(10);
2450
2451 /* Deselect the channel register so we can read the PHYID
2452 * later.
2453 */
2454 tg3_writephy(tp, 0x10, 0x8011);
2455 }
2456
2457 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2458 {
2459 u32 sg_dig_ctrl, sg_dig_status;
2460 u32 serdes_cfg, expected_sg_dig_ctrl;
2461 int workaround, port_a;
2462 int current_link_up;
2463
2464 serdes_cfg = 0;
2465 expected_sg_dig_ctrl = 0;
2466 workaround = 0;
2467 port_a = 1;
2468 current_link_up = 0;
2469
2470 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2471 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2472 workaround = 1;
2473 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2474 port_a = 0;
2475
2476 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2477 /* preserve bits 20-23 for voltage regulator */
2478 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2479 }
2480
2481 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2482
2483 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2484 if (sg_dig_ctrl & (1 << 31)) {
2485 if (workaround) {
2486 u32 val = serdes_cfg;
2487
2488 if (port_a)
2489 val |= 0xc010000;
2490 else
2491 val |= 0x4010000;
2492 tw32_f(MAC_SERDES_CFG, val);
2493 }
2494 tw32_f(SG_DIG_CTRL, 0x01388400);
2495 }
2496 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2497 tg3_setup_flow_control(tp, 0, 0);
2498 current_link_up = 1;
2499 }
2500 goto out;
2501 }
2502
2503 /* Want auto-negotiation. */
2504 expected_sg_dig_ctrl = 0x81388400;
2505
2506 /* Pause capability */
2507 expected_sg_dig_ctrl |= (1 << 11);
2508
2509 /* Asymettric pause */
2510 expected_sg_dig_ctrl |= (1 << 12);
2511
2512 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2513 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2514 tp->serdes_counter &&
2515 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2516 MAC_STATUS_RCVD_CFG)) ==
2517 MAC_STATUS_PCS_SYNCED)) {
2518 tp->serdes_counter--;
2519 current_link_up = 1;
2520 goto out;
2521 }
2522 restart_autoneg:
2523 if (workaround)
2524 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2525 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2526 udelay(5);
2527 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2528
2529 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2530 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2531 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2532 MAC_STATUS_SIGNAL_DET)) {
2533 sg_dig_status = tr32(SG_DIG_STATUS);
2534 mac_status = tr32(MAC_STATUS);
2535
2536 if ((sg_dig_status & (1 << 1)) &&
2537 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2538 u32 local_adv, remote_adv;
2539
2540 local_adv = ADVERTISE_PAUSE_CAP;
2541 remote_adv = 0;
2542 if (sg_dig_status & (1 << 19))
2543 remote_adv |= LPA_PAUSE_CAP;
2544 if (sg_dig_status & (1 << 20))
2545 remote_adv |= LPA_PAUSE_ASYM;
2546
2547 tg3_setup_flow_control(tp, local_adv, remote_adv);
2548 current_link_up = 1;
2549 tp->serdes_counter = 0;
2550 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2551 } else if (!(sg_dig_status & (1 << 1))) {
2552 if (tp->serdes_counter)
2553 tp->serdes_counter--;
2554 else {
2555 if (workaround) {
2556 u32 val = serdes_cfg;
2557
2558 if (port_a)
2559 val |= 0xc010000;
2560 else
2561 val |= 0x4010000;
2562
2563 tw32_f(MAC_SERDES_CFG, val);
2564 }
2565
2566 tw32_f(SG_DIG_CTRL, 0x01388400);
2567 udelay(40);
2568
2569 /* Link parallel detection - link is up */
2570 /* only if we have PCS_SYNC and not */
2571 /* receiving config code words */
2572 mac_status = tr32(MAC_STATUS);
2573 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2574 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2575 tg3_setup_flow_control(tp, 0, 0);
2576 current_link_up = 1;
2577 tp->tg3_flags2 |=
2578 TG3_FLG2_PARALLEL_DETECT;
2579 tp->serdes_counter =
2580 SERDES_PARALLEL_DET_TIMEOUT;
2581 } else
2582 goto restart_autoneg;
2583 }
2584 }
2585 } else {
2586 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2587 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2588 }
2589
2590 out:
2591 return current_link_up;
2592 }
2593
2594 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2595 {
2596 int current_link_up = 0;
2597
2598 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2599 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2600 goto out;
2601 }
2602
2603 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2604 u32 flags;
2605 int i;
2606
2607 if (fiber_autoneg(tp, &flags)) {
2608 u32 local_adv, remote_adv;
2609
2610 local_adv = ADVERTISE_PAUSE_CAP;
2611 remote_adv = 0;
2612 if (flags & MR_LP_ADV_SYM_PAUSE)
2613 remote_adv |= LPA_PAUSE_CAP;
2614 if (flags & MR_LP_ADV_ASYM_PAUSE)
2615 remote_adv |= LPA_PAUSE_ASYM;
2616
2617 tg3_setup_flow_control(tp, local_adv, remote_adv);
2618
2619 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2620 current_link_up = 1;
2621 }
2622 for (i = 0; i < 30; i++) {
2623 udelay(20);
2624 tw32_f(MAC_STATUS,
2625 (MAC_STATUS_SYNC_CHANGED |
2626 MAC_STATUS_CFG_CHANGED));
2627 udelay(40);
2628 if ((tr32(MAC_STATUS) &
2629 (MAC_STATUS_SYNC_CHANGED |
2630 MAC_STATUS_CFG_CHANGED)) == 0)
2631 break;
2632 }
2633
2634 mac_status = tr32(MAC_STATUS);
2635 if (current_link_up == 0 &&
2636 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2637 !(mac_status & MAC_STATUS_RCVD_CFG))
2638 current_link_up = 1;
2639 } else {
2640 /* Forcing 1000FD link up. */
2641 current_link_up = 1;
2642 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2643
2644 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2645 udelay(40);
2646 }
2647
2648 out:
2649 return current_link_up;
2650 }
2651
2652 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2653 {
2654 u32 orig_pause_cfg;
2655 u16 orig_active_speed;
2656 u8 orig_active_duplex;
2657 u32 mac_status;
2658 int current_link_up;
2659 int i;
2660
2661 orig_pause_cfg =
2662 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2663 TG3_FLAG_TX_PAUSE));
2664 orig_active_speed = tp->link_config.active_speed;
2665 orig_active_duplex = tp->link_config.active_duplex;
2666
2667 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2668 netif_carrier_ok(tp->dev) &&
2669 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2670 mac_status = tr32(MAC_STATUS);
2671 mac_status &= (MAC_STATUS_PCS_SYNCED |
2672 MAC_STATUS_SIGNAL_DET |
2673 MAC_STATUS_CFG_CHANGED |
2674 MAC_STATUS_RCVD_CFG);
2675 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2676 MAC_STATUS_SIGNAL_DET)) {
2677 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2678 MAC_STATUS_CFG_CHANGED));
2679 return 0;
2680 }
2681 }
2682
2683 tw32_f(MAC_TX_AUTO_NEG, 0);
2684
2685 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2686 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2687 tw32_f(MAC_MODE, tp->mac_mode);
2688 udelay(40);
2689
2690 if (tp->phy_id == PHY_ID_BCM8002)
2691 tg3_init_bcm8002(tp);
2692
2693 /* Enable link change event even when serdes polling. */
2694 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2695 udelay(40);
2696
2697 current_link_up = 0;
2698 mac_status = tr32(MAC_STATUS);
2699
2700 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2701 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2702 else
2703 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2704
2705 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2706 tw32_f(MAC_MODE, tp->mac_mode);
2707 udelay(40);
2708
2709 tp->hw_status->status =
2710 (SD_STATUS_UPDATED |
2711 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2712
2713 for (i = 0; i < 100; i++) {
2714 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2715 MAC_STATUS_CFG_CHANGED));
2716 udelay(5);
2717 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2718 MAC_STATUS_CFG_CHANGED |
2719 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2720 break;
2721 }
2722
2723 mac_status = tr32(MAC_STATUS);
2724 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2725 current_link_up = 0;
2726 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2727 tp->serdes_counter == 0) {
2728 tw32_f(MAC_MODE, (tp->mac_mode |
2729 MAC_MODE_SEND_CONFIGS));
2730 udelay(1);
2731 tw32_f(MAC_MODE, tp->mac_mode);
2732 }
2733 }
2734
2735 if (current_link_up == 1) {
2736 tp->link_config.active_speed = SPEED_1000;
2737 tp->link_config.active_duplex = DUPLEX_FULL;
2738 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2739 LED_CTRL_LNKLED_OVERRIDE |
2740 LED_CTRL_1000MBPS_ON));
2741 } else {
2742 tp->link_config.active_speed = SPEED_INVALID;
2743 tp->link_config.active_duplex = DUPLEX_INVALID;
2744 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2745 LED_CTRL_LNKLED_OVERRIDE |
2746 LED_CTRL_TRAFFIC_OVERRIDE));
2747 }
2748
2749 if (current_link_up != netif_carrier_ok(tp->dev)) {
2750 if (current_link_up)
2751 netif_carrier_on(tp->dev);
2752 else
2753 netif_carrier_off(tp->dev);
2754 tg3_link_report(tp);
2755 } else {
2756 u32 now_pause_cfg =
2757 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2758 TG3_FLAG_TX_PAUSE);
2759 if (orig_pause_cfg != now_pause_cfg ||
2760 orig_active_speed != tp->link_config.active_speed ||
2761 orig_active_duplex != tp->link_config.active_duplex)
2762 tg3_link_report(tp);
2763 }
2764
2765 return 0;
2766 }
2767
2768 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2769 {
2770 int current_link_up, err = 0;
2771 u32 bmsr, bmcr;
2772 u16 current_speed;
2773 u8 current_duplex;
2774
2775 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2776 tw32_f(MAC_MODE, tp->mac_mode);
2777 udelay(40);
2778
2779 tw32(MAC_EVENT, 0);
2780
2781 tw32_f(MAC_STATUS,
2782 (MAC_STATUS_SYNC_CHANGED |
2783 MAC_STATUS_CFG_CHANGED |
2784 MAC_STATUS_MI_COMPLETION |
2785 MAC_STATUS_LNKSTATE_CHANGED));
2786 udelay(40);
2787
2788 if (force_reset)
2789 tg3_phy_reset(tp);
2790
2791 current_link_up = 0;
2792 current_speed = SPEED_INVALID;
2793 current_duplex = DUPLEX_INVALID;
2794
2795 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2796 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2797 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2798 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2799 bmsr |= BMSR_LSTATUS;
2800 else
2801 bmsr &= ~BMSR_LSTATUS;
2802 }
2803
2804 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2805
2806 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2807 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2808 /* do nothing, just check for link up at the end */
2809 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2810 u32 adv, new_adv;
2811
2812 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2813 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2814 ADVERTISE_1000XPAUSE |
2815 ADVERTISE_1000XPSE_ASYM |
2816 ADVERTISE_SLCT);
2817
2818 /* Always advertise symmetric PAUSE just like copper */
2819 new_adv |= ADVERTISE_1000XPAUSE;
2820
2821 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2822 new_adv |= ADVERTISE_1000XHALF;
2823 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2824 new_adv |= ADVERTISE_1000XFULL;
2825
2826 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2827 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2828 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2829 tg3_writephy(tp, MII_BMCR, bmcr);
2830
2831 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2832 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2833 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2834
2835 return err;
2836 }
2837 } else {
2838 u32 new_bmcr;
2839
2840 bmcr &= ~BMCR_SPEED1000;
2841 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2842
2843 if (tp->link_config.duplex == DUPLEX_FULL)
2844 new_bmcr |= BMCR_FULLDPLX;
2845
2846 if (new_bmcr != bmcr) {
2847 /* BMCR_SPEED1000 is a reserved bit that needs
2848 * to be set on write.
2849 */
2850 new_bmcr |= BMCR_SPEED1000;
2851
2852 /* Force a linkdown */
2853 if (netif_carrier_ok(tp->dev)) {
2854 u32 adv;
2855
2856 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2857 adv &= ~(ADVERTISE_1000XFULL |
2858 ADVERTISE_1000XHALF |
2859 ADVERTISE_SLCT);
2860 tg3_writephy(tp, MII_ADVERTISE, adv);
2861 tg3_writephy(tp, MII_BMCR, bmcr |
2862 BMCR_ANRESTART |
2863 BMCR_ANENABLE);
2864 udelay(10);
2865 netif_carrier_off(tp->dev);
2866 }
2867 tg3_writephy(tp, MII_BMCR, new_bmcr);
2868 bmcr = new_bmcr;
2869 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2871 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2872 ASIC_REV_5714) {
2873 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2874 bmsr |= BMSR_LSTATUS;
2875 else
2876 bmsr &= ~BMSR_LSTATUS;
2877 }
2878 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2879 }
2880 }
2881
2882 if (bmsr & BMSR_LSTATUS) {
2883 current_speed = SPEED_1000;
2884 current_link_up = 1;
2885 if (bmcr & BMCR_FULLDPLX)
2886 current_duplex = DUPLEX_FULL;
2887 else
2888 current_duplex = DUPLEX_HALF;
2889
2890 if (bmcr & BMCR_ANENABLE) {
2891 u32 local_adv, remote_adv, common;
2892
2893 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2894 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2895 common = local_adv & remote_adv;
2896 if (common & (ADVERTISE_1000XHALF |
2897 ADVERTISE_1000XFULL)) {
2898 if (common & ADVERTISE_1000XFULL)
2899 current_duplex = DUPLEX_FULL;
2900 else
2901 current_duplex = DUPLEX_HALF;
2902
2903 tg3_setup_flow_control(tp, local_adv,
2904 remote_adv);
2905 }
2906 else
2907 current_link_up = 0;
2908 }
2909 }
2910
2911 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2912 if (tp->link_config.active_duplex == DUPLEX_HALF)
2913 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2914
2915 tw32_f(MAC_MODE, tp->mac_mode);
2916 udelay(40);
2917
2918 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2919
2920 tp->link_config.active_speed = current_speed;
2921 tp->link_config.active_duplex = current_duplex;
2922
2923 if (current_link_up != netif_carrier_ok(tp->dev)) {
2924 if (current_link_up)
2925 netif_carrier_on(tp->dev);
2926 else {
2927 netif_carrier_off(tp->dev);
2928 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2929 }
2930 tg3_link_report(tp);
2931 }
2932 return err;
2933 }
2934
2935 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2936 {
2937 if (tp->serdes_counter) {
2938 /* Give autoneg time to complete. */
2939 tp->serdes_counter--;
2940 return;
2941 }
2942 if (!netif_carrier_ok(tp->dev) &&
2943 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2944 u32 bmcr;
2945
2946 tg3_readphy(tp, MII_BMCR, &bmcr);
2947 if (bmcr & BMCR_ANENABLE) {
2948 u32 phy1, phy2;
2949
2950 /* Select shadow register 0x1f */
2951 tg3_writephy(tp, 0x1c, 0x7c00);
2952 tg3_readphy(tp, 0x1c, &phy1);
2953
2954 /* Select expansion interrupt status register */
2955 tg3_writephy(tp, 0x17, 0x0f01);
2956 tg3_readphy(tp, 0x15, &phy2);
2957 tg3_readphy(tp, 0x15, &phy2);
2958
2959 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2960 /* We have signal detect and not receiving
2961 * config code words, link is up by parallel
2962 * detection.
2963 */
2964
2965 bmcr &= ~BMCR_ANENABLE;
2966 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2967 tg3_writephy(tp, MII_BMCR, bmcr);
2968 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2969 }
2970 }
2971 }
2972 else if (netif_carrier_ok(tp->dev) &&
2973 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2974 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2975 u32 phy2;
2976
2977 /* Select expansion interrupt status register */
2978 tg3_writephy(tp, 0x17, 0x0f01);
2979 tg3_readphy(tp, 0x15, &phy2);
2980 if (phy2 & 0x20) {
2981 u32 bmcr;
2982
2983 /* Config code words received, turn on autoneg. */
2984 tg3_readphy(tp, MII_BMCR, &bmcr);
2985 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2986
2987 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2988
2989 }
2990 }
2991 }
2992
2993 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2994 {
2995 int err;
2996
2997 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2998 err = tg3_setup_fiber_phy(tp, force_reset);
2999 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3000 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3001 } else {
3002 err = tg3_setup_copper_phy(tp, force_reset);
3003 }
3004
3005 if (tp->link_config.active_speed == SPEED_1000 &&
3006 tp->link_config.active_duplex == DUPLEX_HALF)
3007 tw32(MAC_TX_LENGTHS,
3008 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3009 (6 << TX_LENGTHS_IPG_SHIFT) |
3010 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3011 else
3012 tw32(MAC_TX_LENGTHS,
3013 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3014 (6 << TX_LENGTHS_IPG_SHIFT) |
3015 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3016
3017 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3018 if (netif_carrier_ok(tp->dev)) {
3019 tw32(HOSTCC_STAT_COAL_TICKS,
3020 tp->coal.stats_block_coalesce_usecs);
3021 } else {
3022 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3023 }
3024 }
3025
3026 return err;
3027 }
3028
3029 /* This is called whenever we suspect that the system chipset is re-
3030 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3031 * is bogus tx completions. We try to recover by setting the
3032 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3033 * in the workqueue.
3034 */
3035 static void tg3_tx_recover(struct tg3 *tp)
3036 {
3037 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3038 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3039
3040 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3041 "mapped I/O cycles to the network device, attempting to "
3042 "recover. Please report the problem to the driver maintainer "
3043 "and include system chipset information.\n", tp->dev->name);
3044
3045 spin_lock(&tp->lock);
3046 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3047 spin_unlock(&tp->lock);
3048 }
3049
3050 static inline u32 tg3_tx_avail(struct tg3 *tp)
3051 {
3052 smp_mb();
3053 return (tp->tx_pending -
3054 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3055 }
3056
3057 /* Tigon3 never reports partial packet sends. So we do not
3058 * need special logic to handle SKBs that have not had all
3059 * of their frags sent yet, like SunGEM does.
3060 */
3061 static void tg3_tx(struct tg3 *tp)
3062 {
3063 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3064 u32 sw_idx = tp->tx_cons;
3065
3066 while (sw_idx != hw_idx) {
3067 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3068 struct sk_buff *skb = ri->skb;
3069 int i, tx_bug = 0;
3070
3071 if (unlikely(skb == NULL)) {
3072 tg3_tx_recover(tp);
3073 return;
3074 }
3075
3076 pci_unmap_single(tp->pdev,
3077 pci_unmap_addr(ri, mapping),
3078 skb_headlen(skb),
3079 PCI_DMA_TODEVICE);
3080
3081 ri->skb = NULL;
3082
3083 sw_idx = NEXT_TX(sw_idx);
3084
3085 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3086 ri = &tp->tx_buffers[sw_idx];
3087 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3088 tx_bug = 1;
3089
3090 pci_unmap_page(tp->pdev,
3091 pci_unmap_addr(ri, mapping),
3092 skb_shinfo(skb)->frags[i].size,
3093 PCI_DMA_TODEVICE);
3094
3095 sw_idx = NEXT_TX(sw_idx);
3096 }
3097
3098 dev_kfree_skb(skb);
3099
3100 if (unlikely(tx_bug)) {
3101 tg3_tx_recover(tp);
3102 return;
3103 }
3104 }
3105
3106 tp->tx_cons = sw_idx;
3107
3108 /* Need to make the tx_cons update visible to tg3_start_xmit()
3109 * before checking for netif_queue_stopped(). Without the
3110 * memory barrier, there is a small possibility that tg3_start_xmit()
3111 * will miss it and cause the queue to be stopped forever.
3112 */
3113 smp_mb();
3114
3115 if (unlikely(netif_queue_stopped(tp->dev) &&
3116 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3117 netif_tx_lock(tp->dev);
3118 if (netif_queue_stopped(tp->dev) &&
3119 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3120 netif_wake_queue(tp->dev);
3121 netif_tx_unlock(tp->dev);
3122 }
3123 }
3124
3125 /* Returns size of skb allocated or < 0 on error.
3126 *
3127 * We only need to fill in the address because the other members
3128 * of the RX descriptor are invariant, see tg3_init_rings.
3129 *
3130 * Note the purposeful assymetry of cpu vs. chip accesses. For
3131 * posting buffers we only dirty the first cache line of the RX
3132 * descriptor (containing the address). Whereas for the RX status
3133 * buffers the cpu only reads the last cacheline of the RX descriptor
3134 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3135 */
3136 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3137 int src_idx, u32 dest_idx_unmasked)
3138 {
3139 struct tg3_rx_buffer_desc *desc;
3140 struct ring_info *map, *src_map;
3141 struct sk_buff *skb;
3142 dma_addr_t mapping;
3143 int skb_size, dest_idx;
3144
3145 src_map = NULL;
3146 switch (opaque_key) {
3147 case RXD_OPAQUE_RING_STD:
3148 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3149 desc = &tp->rx_std[dest_idx];
3150 map = &tp->rx_std_buffers[dest_idx];
3151 if (src_idx >= 0)
3152 src_map = &tp->rx_std_buffers[src_idx];
3153 skb_size = tp->rx_pkt_buf_sz;
3154 break;
3155
3156 case RXD_OPAQUE_RING_JUMBO:
3157 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3158 desc = &tp->rx_jumbo[dest_idx];
3159 map = &tp->rx_jumbo_buffers[dest_idx];
3160 if (src_idx >= 0)
3161 src_map = &tp->rx_jumbo_buffers[src_idx];
3162 skb_size = RX_JUMBO_PKT_BUF_SZ;
3163 break;
3164
3165 default:
3166 return -EINVAL;
3167 };
3168
3169 /* Do not overwrite any of the map or rp information
3170 * until we are sure we can commit to a new buffer.
3171 *
3172 * Callers depend upon this behavior and assume that
3173 * we leave everything unchanged if we fail.
3174 */
3175 skb = netdev_alloc_skb(tp->dev, skb_size);
3176 if (skb == NULL)
3177 return -ENOMEM;
3178
3179 skb_reserve(skb, tp->rx_offset);
3180
3181 mapping = pci_map_single(tp->pdev, skb->data,
3182 skb_size - tp->rx_offset,
3183 PCI_DMA_FROMDEVICE);
3184
3185 map->skb = skb;
3186 pci_unmap_addr_set(map, mapping, mapping);
3187
3188 if (src_map != NULL)
3189 src_map->skb = NULL;
3190
3191 desc->addr_hi = ((u64)mapping >> 32);
3192 desc->addr_lo = ((u64)mapping & 0xffffffff);
3193
3194 return skb_size;
3195 }
3196
3197 /* We only need to move over in the address because the other
3198 * members of the RX descriptor are invariant. See notes above
3199 * tg3_alloc_rx_skb for full details.
3200 */
3201 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3202 int src_idx, u32 dest_idx_unmasked)
3203 {
3204 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3205 struct ring_info *src_map, *dest_map;
3206 int dest_idx;
3207
3208 switch (opaque_key) {
3209 case RXD_OPAQUE_RING_STD:
3210 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3211 dest_desc = &tp->rx_std[dest_idx];
3212 dest_map = &tp->rx_std_buffers[dest_idx];
3213 src_desc = &tp->rx_std[src_idx];
3214 src_map = &tp->rx_std_buffers[src_idx];
3215 break;
3216
3217 case RXD_OPAQUE_RING_JUMBO:
3218 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3219 dest_desc = &tp->rx_jumbo[dest_idx];
3220 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3221 src_desc = &tp->rx_jumbo[src_idx];
3222 src_map = &tp->rx_jumbo_buffers[src_idx];
3223 break;
3224
3225 default:
3226 return;
3227 };
3228
3229 dest_map->skb = src_map->skb;
3230 pci_unmap_addr_set(dest_map, mapping,
3231 pci_unmap_addr(src_map, mapping));
3232 dest_desc->addr_hi = src_desc->addr_hi;
3233 dest_desc->addr_lo = src_desc->addr_lo;
3234
3235 src_map->skb = NULL;
3236 }
3237
3238 #if TG3_VLAN_TAG_USED
3239 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3240 {
3241 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3242 }
3243 #endif
3244
3245 /* The RX ring scheme is composed of multiple rings which post fresh
3246 * buffers to the chip, and one special ring the chip uses to report
3247 * status back to the host.
3248 *
3249 * The special ring reports the status of received packets to the
3250 * host. The chip does not write into the original descriptor the
3251 * RX buffer was obtained from. The chip simply takes the original
3252 * descriptor as provided by the host, updates the status and length
3253 * field, then writes this into the next status ring entry.
3254 *
3255 * Each ring the host uses to post buffers to the chip is described
3256 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3257 * it is first placed into the on-chip ram. When the packet's length
3258 * is known, it walks down the TG3_BDINFO entries to select the ring.
3259 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3260 * which is within the range of the new packet's length is chosen.
3261 *
3262 * The "separate ring for rx status" scheme may sound queer, but it makes
3263 * sense from a cache coherency perspective. If only the host writes
3264 * to the buffer post rings, and only the chip writes to the rx status
3265 * rings, then cache lines never move beyond shared-modified state.
3266 * If both the host and chip were to write into the same ring, cache line
3267 * eviction could occur since both entities want it in an exclusive state.
3268 */
3269 static int tg3_rx(struct tg3 *tp, int budget)
3270 {
3271 u32 work_mask, rx_std_posted = 0;
3272 u32 sw_idx = tp->rx_rcb_ptr;
3273 u16 hw_idx;
3274 int received;
3275
3276 hw_idx = tp->hw_status->idx[0].rx_producer;
3277 /*
3278 * We need to order the read of hw_idx and the read of
3279 * the opaque cookie.
3280 */
3281 rmb();
3282 work_mask = 0;
3283 received = 0;
3284 while (sw_idx != hw_idx && budget > 0) {
3285 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3286 unsigned int len;
3287 struct sk_buff *skb;
3288 dma_addr_t dma_addr;
3289 u32 opaque_key, desc_idx, *post_ptr;
3290
3291 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3292 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3293 if (opaque_key == RXD_OPAQUE_RING_STD) {
3294 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3295 mapping);
3296 skb = tp->rx_std_buffers[desc_idx].skb;
3297 post_ptr = &tp->rx_std_ptr;
3298 rx_std_posted++;
3299 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3300 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3301 mapping);
3302 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3303 post_ptr = &tp->rx_jumbo_ptr;
3304 }
3305 else {
3306 goto next_pkt_nopost;
3307 }
3308
3309 work_mask |= opaque_key;
3310
3311 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3312 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3313 drop_it:
3314 tg3_recycle_rx(tp, opaque_key,
3315 desc_idx, *post_ptr);
3316 drop_it_no_recycle:
3317 /* Other statistics kept track of by card. */
3318 tp->net_stats.rx_dropped++;
3319 goto next_pkt;
3320 }
3321
3322 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3323
3324 if (len > RX_COPY_THRESHOLD
3325 && tp->rx_offset == 2
3326 /* rx_offset != 2 iff this is a 5701 card running
3327 * in PCI-X mode [see tg3_get_invariants()] */
3328 ) {
3329 int skb_size;
3330
3331 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3332 desc_idx, *post_ptr);
3333 if (skb_size < 0)
3334 goto drop_it;
3335
3336 pci_unmap_single(tp->pdev, dma_addr,
3337 skb_size - tp->rx_offset,
3338 PCI_DMA_FROMDEVICE);
3339
3340 skb_put(skb, len);
3341 } else {
3342 struct sk_buff *copy_skb;
3343
3344 tg3_recycle_rx(tp, opaque_key,
3345 desc_idx, *post_ptr);
3346
3347 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3348 if (copy_skb == NULL)
3349 goto drop_it_no_recycle;
3350
3351 skb_reserve(copy_skb, 2);
3352 skb_put(copy_skb, len);
3353 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354 skb_copy_from_linear_data(skb, copy_skb->data, len);
3355 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3356
3357 /* We'll reuse the original ring buffer. */
3358 skb = copy_skb;
3359 }
3360
3361 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3362 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3363 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3364 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3365 skb->ip_summed = CHECKSUM_UNNECESSARY;
3366 else
3367 skb->ip_summed = CHECKSUM_NONE;
3368
3369 skb->protocol = eth_type_trans(skb, tp->dev);
3370 #if TG3_VLAN_TAG_USED
3371 if (tp->vlgrp != NULL &&
3372 desc->type_flags & RXD_FLAG_VLAN) {
3373 tg3_vlan_rx(tp, skb,
3374 desc->err_vlan & RXD_VLAN_MASK);
3375 } else
3376 #endif
3377 netif_receive_skb(skb);
3378
3379 tp->dev->last_rx = jiffies;
3380 received++;
3381 budget--;
3382
3383 next_pkt:
3384 (*post_ptr)++;
3385
3386 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3387 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3388
3389 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3390 TG3_64BIT_REG_LOW, idx);
3391 work_mask &= ~RXD_OPAQUE_RING_STD;
3392 rx_std_posted = 0;
3393 }
3394 next_pkt_nopost:
3395 sw_idx++;
3396 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3397
3398 /* Refresh hw_idx to see if there is new work */
3399 if (sw_idx == hw_idx) {
3400 hw_idx = tp->hw_status->idx[0].rx_producer;
3401 rmb();
3402 }
3403 }
3404
3405 /* ACK the status ring. */
3406 tp->rx_rcb_ptr = sw_idx;
3407 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3408
3409 /* Refill RX ring(s). */
3410 if (work_mask & RXD_OPAQUE_RING_STD) {
3411 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3412 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3413 sw_idx);
3414 }
3415 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3416 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3417 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3418 sw_idx);
3419 }
3420 mmiowb();
3421
3422 return received;
3423 }
3424
3425 static int tg3_poll(struct net_device *netdev, int *budget)
3426 {
3427 struct tg3 *tp = netdev_priv(netdev);
3428 struct tg3_hw_status *sblk = tp->hw_status;
3429 int done;
3430
3431 /* handle link change and other phy events */
3432 if (!(tp->tg3_flags &
3433 (TG3_FLAG_USE_LINKCHG_REG |
3434 TG3_FLAG_POLL_SERDES))) {
3435 if (sblk->status & SD_STATUS_LINK_CHG) {
3436 sblk->status = SD_STATUS_UPDATED |
3437 (sblk->status & ~SD_STATUS_LINK_CHG);
3438 spin_lock(&tp->lock);
3439 tg3_setup_phy(tp, 0);
3440 spin_unlock(&tp->lock);
3441 }
3442 }
3443
3444 /* run TX completion thread */
3445 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3446 tg3_tx(tp);
3447 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3448 netif_rx_complete(netdev);
3449 schedule_work(&tp->reset_task);
3450 return 0;
3451 }
3452 }
3453
3454 /* run RX thread, within the bounds set by NAPI.
3455 * All RX "locking" is done by ensuring outside
3456 * code synchronizes with dev->poll()
3457 */
3458 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3459 int orig_budget = *budget;
3460 int work_done;
3461
3462 if (orig_budget > netdev->quota)
3463 orig_budget = netdev->quota;
3464
3465 work_done = tg3_rx(tp, orig_budget);
3466
3467 *budget -= work_done;
3468 netdev->quota -= work_done;
3469 }
3470
3471 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3472 tp->last_tag = sblk->status_tag;
3473 rmb();
3474 } else
3475 sblk->status &= ~SD_STATUS_UPDATED;
3476
3477 /* if no more work, tell net stack and NIC we're done */
3478 done = !tg3_has_work(tp);
3479 if (done) {
3480 netif_rx_complete(netdev);
3481 tg3_restart_ints(tp);
3482 }
3483
3484 return (done ? 0 : 1);
3485 }
3486
3487 static void tg3_irq_quiesce(struct tg3 *tp)
3488 {
3489 BUG_ON(tp->irq_sync);
3490
3491 tp->irq_sync = 1;
3492 smp_mb();
3493
3494 synchronize_irq(tp->pdev->irq);
3495 }
3496
3497 static inline int tg3_irq_sync(struct tg3 *tp)
3498 {
3499 return tp->irq_sync;
3500 }
3501
3502 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3503 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3504 * with as well. Most of the time, this is not necessary except when
3505 * shutting down the device.
3506 */
3507 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3508 {
3509 if (irq_sync)
3510 tg3_irq_quiesce(tp);
3511 spin_lock_bh(&tp->lock);
3512 }
3513
3514 static inline void tg3_full_unlock(struct tg3 *tp)
3515 {
3516 spin_unlock_bh(&tp->lock);
3517 }
3518
3519 /* One-shot MSI handler - Chip automatically disables interrupt
3520 * after sending MSI so driver doesn't have to do it.
3521 */
3522 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3523 {
3524 struct net_device *dev = dev_id;
3525 struct tg3 *tp = netdev_priv(dev);
3526
3527 prefetch(tp->hw_status);
3528 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3529
3530 if (likely(!tg3_irq_sync(tp)))
3531 netif_rx_schedule(dev); /* schedule NAPI poll */
3532
3533 return IRQ_HANDLED;
3534 }
3535
3536 /* MSI ISR - No need to check for interrupt sharing and no need to
3537 * flush status block and interrupt mailbox. PCI ordering rules
3538 * guarantee that MSI will arrive after the status block.
3539 */
3540 static irqreturn_t tg3_msi(int irq, void *dev_id)
3541 {
3542 struct net_device *dev = dev_id;
3543 struct tg3 *tp = netdev_priv(dev);
3544
3545 prefetch(tp->hw_status);
3546 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3547 /*
3548 * Writing any value to intr-mbox-0 clears PCI INTA# and
3549 * chip-internal interrupt pending events.
3550 * Writing non-zero to intr-mbox-0 additional tells the
3551 * NIC to stop sending us irqs, engaging "in-intr-handler"
3552 * event coalescing.
3553 */
3554 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3555 if (likely(!tg3_irq_sync(tp)))
3556 netif_rx_schedule(dev); /* schedule NAPI poll */
3557
3558 return IRQ_RETVAL(1);
3559 }
3560
3561 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3562 {
3563 struct net_device *dev = dev_id;
3564 struct tg3 *tp = netdev_priv(dev);
3565 struct tg3_hw_status *sblk = tp->hw_status;
3566 unsigned int handled = 1;
3567
3568 /* In INTx mode, it is possible for the interrupt to arrive at
3569 * the CPU before the status block posted prior to the interrupt.
3570 * Reading the PCI State register will confirm whether the
3571 * interrupt is ours and will flush the status block.
3572 */
3573 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3574 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3575 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3576 handled = 0;
3577 goto out;
3578 }
3579 }
3580
3581 /*
3582 * Writing any value to intr-mbox-0 clears PCI INTA# and
3583 * chip-internal interrupt pending events.
3584 * Writing non-zero to intr-mbox-0 additional tells the
3585 * NIC to stop sending us irqs, engaging "in-intr-handler"
3586 * event coalescing.
3587 */
3588 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3589 if (tg3_irq_sync(tp))
3590 goto out;
3591 sblk->status &= ~SD_STATUS_UPDATED;
3592 if (likely(tg3_has_work(tp))) {
3593 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3594 netif_rx_schedule(dev); /* schedule NAPI poll */
3595 } else {
3596 /* No work, shared interrupt perhaps? re-enable
3597 * interrupts, and flush that PCI write
3598 */
3599 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3600 0x00000000);
3601 }
3602 out:
3603 return IRQ_RETVAL(handled);
3604 }
3605
3606 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3607 {
3608 struct net_device *dev = dev_id;
3609 struct tg3 *tp = netdev_priv(dev);
3610 struct tg3_hw_status *sblk = tp->hw_status;
3611 unsigned int handled = 1;
3612
3613 /* In INTx mode, it is possible for the interrupt to arrive at
3614 * the CPU before the status block posted prior to the interrupt.
3615 * Reading the PCI State register will confirm whether the
3616 * interrupt is ours and will flush the status block.
3617 */
3618 if (unlikely(sblk->status_tag == tp->last_tag)) {
3619 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3620 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3621 handled = 0;
3622 goto out;
3623 }
3624 }
3625
3626 /*
3627 * writing any value to intr-mbox-0 clears PCI INTA# and
3628 * chip-internal interrupt pending events.
3629 * writing non-zero to intr-mbox-0 additional tells the
3630 * NIC to stop sending us irqs, engaging "in-intr-handler"
3631 * event coalescing.
3632 */
3633 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3634 if (tg3_irq_sync(tp))
3635 goto out;
3636 if (netif_rx_schedule_prep(dev)) {
3637 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3638 /* Update last_tag to mark that this status has been
3639 * seen. Because interrupt may be shared, we may be
3640 * racing with tg3_poll(), so only update last_tag
3641 * if tg3_poll() is not scheduled.
3642 */
3643 tp->last_tag = sblk->status_tag;
3644 __netif_rx_schedule(dev);
3645 }
3646 out:
3647 return IRQ_RETVAL(handled);
3648 }
3649
3650 /* ISR for interrupt test */
3651 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3652 {
3653 struct net_device *dev = dev_id;
3654 struct tg3 *tp = netdev_priv(dev);
3655 struct tg3_hw_status *sblk = tp->hw_status;
3656
3657 if ((sblk->status & SD_STATUS_UPDATED) ||
3658 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3659 tg3_disable_ints(tp);
3660 return IRQ_RETVAL(1);
3661 }
3662 return IRQ_RETVAL(0);
3663 }
3664
3665 static int tg3_init_hw(struct tg3 *, int);
3666 static int tg3_halt(struct tg3 *, int, int);
3667
3668 /* Restart hardware after configuration changes, self-test, etc.
3669 * Invoked with tp->lock held.
3670 */
3671 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3672 {
3673 int err;
3674
3675 err = tg3_init_hw(tp, reset_phy);
3676 if (err) {
3677 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3678 "aborting.\n", tp->dev->name);
3679 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3680 tg3_full_unlock(tp);
3681 del_timer_sync(&tp->timer);
3682 tp->irq_sync = 0;
3683 netif_poll_enable(tp->dev);
3684 dev_close(tp->dev);
3685 tg3_full_lock(tp, 0);
3686 }
3687 return err;
3688 }
3689
3690 #ifdef CONFIG_NET_POLL_CONTROLLER
3691 static void tg3_poll_controller(struct net_device *dev)
3692 {
3693 struct tg3 *tp = netdev_priv(dev);
3694
3695 tg3_interrupt(tp->pdev->irq, dev);
3696 }
3697 #endif
3698
3699 static void tg3_reset_task(struct work_struct *work)
3700 {
3701 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3702 unsigned int restart_timer;
3703
3704 tg3_full_lock(tp, 0);
3705 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3706
3707 if (!netif_running(tp->dev)) {
3708 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3709 tg3_full_unlock(tp);
3710 return;
3711 }
3712
3713 tg3_full_unlock(tp);
3714
3715 tg3_netif_stop(tp);
3716
3717 tg3_full_lock(tp, 1);
3718
3719 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3720 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3721
3722 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3723 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3724 tp->write32_rx_mbox = tg3_write_flush_reg32;
3725 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3726 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3727 }
3728
3729 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3730 if (tg3_init_hw(tp, 1))
3731 goto out;
3732
3733 tg3_netif_start(tp);
3734
3735 if (restart_timer)
3736 mod_timer(&tp->timer, jiffies + 1);
3737
3738 out:
3739 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3740
3741 tg3_full_unlock(tp);
3742 }
3743
3744 static void tg3_dump_short_state(struct tg3 *tp)
3745 {
3746 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3747 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3748 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3749 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3750 }
3751
3752 static void tg3_tx_timeout(struct net_device *dev)
3753 {
3754 struct tg3 *tp = netdev_priv(dev);
3755
3756 if (netif_msg_tx_err(tp)) {
3757 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3758 dev->name);
3759 tg3_dump_short_state(tp);
3760 }
3761
3762 schedule_work(&tp->reset_task);
3763 }
3764
3765 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3766 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3767 {
3768 u32 base = (u32) mapping & 0xffffffff;
3769
3770 return ((base > 0xffffdcc0) &&
3771 (base + len + 8 < base));
3772 }
3773
3774 /* Test for DMA addresses > 40-bit */
3775 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3776 int len)
3777 {
3778 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3779 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3780 return (((u64) mapping + len) > DMA_40BIT_MASK);
3781 return 0;
3782 #else
3783 return 0;
3784 #endif
3785 }
3786
3787 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3788
3789 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3790 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3791 u32 last_plus_one, u32 *start,
3792 u32 base_flags, u32 mss)
3793 {
3794 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3795 dma_addr_t new_addr = 0;
3796 u32 entry = *start;
3797 int i, ret = 0;
3798
3799 if (!new_skb) {
3800 ret = -1;
3801 } else {
3802 /* New SKB is guaranteed to be linear. */
3803 entry = *start;
3804 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3805 PCI_DMA_TODEVICE);
3806 /* Make sure new skb does not cross any 4G boundaries.
3807 * Drop the packet if it does.
3808 */
3809 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3810 ret = -1;
3811 dev_kfree_skb(new_skb);
3812 new_skb = NULL;
3813 } else {
3814 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3815 base_flags, 1 | (mss << 1));
3816 *start = NEXT_TX(entry);
3817 }
3818 }
3819
3820 /* Now clean up the sw ring entries. */
3821 i = 0;
3822 while (entry != last_plus_one) {
3823 int len;
3824
3825 if (i == 0)
3826 len = skb_headlen(skb);
3827 else
3828 len = skb_shinfo(skb)->frags[i-1].size;
3829 pci_unmap_single(tp->pdev,
3830 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3831 len, PCI_DMA_TODEVICE);
3832 if (i == 0) {
3833 tp->tx_buffers[entry].skb = new_skb;
3834 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3835 } else {
3836 tp->tx_buffers[entry].skb = NULL;
3837 }
3838 entry = NEXT_TX(entry);
3839 i++;
3840 }
3841
3842 dev_kfree_skb(skb);
3843
3844 return ret;
3845 }
3846
3847 static void tg3_set_txd(struct tg3 *tp, int entry,
3848 dma_addr_t mapping, int len, u32 flags,
3849 u32 mss_and_is_end)
3850 {
3851 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3852 int is_end = (mss_and_is_end & 0x1);
3853 u32 mss = (mss_and_is_end >> 1);
3854 u32 vlan_tag = 0;
3855
3856 if (is_end)
3857 flags |= TXD_FLAG_END;
3858 if (flags & TXD_FLAG_VLAN) {
3859 vlan_tag = flags >> 16;
3860 flags &= 0xffff;
3861 }
3862 vlan_tag |= (mss << TXD_MSS_SHIFT);
3863
3864 txd->addr_hi = ((u64) mapping >> 32);
3865 txd->addr_lo = ((u64) mapping & 0xffffffff);
3866 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3867 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3868 }
3869
3870 /* hard_start_xmit for devices that don't have any bugs and
3871 * support TG3_FLG2_HW_TSO_2 only.
3872 */
3873 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3874 {
3875 struct tg3 *tp = netdev_priv(dev);
3876 dma_addr_t mapping;
3877 u32 len, entry, base_flags, mss;
3878
3879 len = skb_headlen(skb);
3880
3881 /* We are running in BH disabled context with netif_tx_lock
3882 * and TX reclaim runs via tp->poll inside of a software
3883 * interrupt. Furthermore, IRQ processing runs lockless so we have
3884 * no IRQ context deadlocks to worry about either. Rejoice!
3885 */
3886 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3887 if (!netif_queue_stopped(dev)) {
3888 netif_stop_queue(dev);
3889
3890 /* This is a hard error, log it. */
3891 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3892 "queue awake!\n", dev->name);
3893 }
3894 return NETDEV_TX_BUSY;
3895 }
3896
3897 entry = tp->tx_prod;
3898 base_flags = 0;
3899 mss = 0;
3900 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3901 int tcp_opt_len, ip_tcp_len;
3902
3903 if (skb_header_cloned(skb) &&
3904 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3905 dev_kfree_skb(skb);
3906 goto out_unlock;
3907 }
3908
3909 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3910 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3911 else {
3912 struct iphdr *iph = ip_hdr(skb);
3913
3914 tcp_opt_len = tcp_optlen(skb);
3915 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3916
3917 iph->check = 0;
3918 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3919 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3920 }
3921
3922 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3923 TXD_FLAG_CPU_POST_DMA);
3924
3925 tcp_hdr(skb)->check = 0;
3926
3927 }
3928 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3929 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3930 #if TG3_VLAN_TAG_USED
3931 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3932 base_flags |= (TXD_FLAG_VLAN |
3933 (vlan_tx_tag_get(skb) << 16));
3934 #endif
3935
3936 /* Queue skb data, a.k.a. the main skb fragment. */
3937 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3938
3939 tp->tx_buffers[entry].skb = skb;
3940 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3941
3942 tg3_set_txd(tp, entry, mapping, len, base_flags,
3943 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3944
3945 entry = NEXT_TX(entry);
3946
3947 /* Now loop through additional data fragments, and queue them. */
3948 if (skb_shinfo(skb)->nr_frags > 0) {
3949 unsigned int i, last;
3950
3951 last = skb_shinfo(skb)->nr_frags - 1;
3952 for (i = 0; i <= last; i++) {
3953 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3954
3955 len = frag->size;
3956 mapping = pci_map_page(tp->pdev,
3957 frag->page,
3958 frag->page_offset,
3959 len, PCI_DMA_TODEVICE);
3960
3961 tp->tx_buffers[entry].skb = NULL;
3962 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3963
3964 tg3_set_txd(tp, entry, mapping, len,
3965 base_flags, (i == last) | (mss << 1));
3966
3967 entry = NEXT_TX(entry);
3968 }
3969 }
3970
3971 /* Packets are ready, update Tx producer idx local and on card. */
3972 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3973
3974 tp->tx_prod = entry;
3975 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3976 netif_stop_queue(dev);
3977 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3978 netif_wake_queue(tp->dev);
3979 }
3980
3981 out_unlock:
3982 mmiowb();
3983
3984 dev->trans_start = jiffies;
3985
3986 return NETDEV_TX_OK;
3987 }
3988
3989 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3990
3991 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3992 * TSO header is greater than 80 bytes.
3993 */
3994 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3995 {
3996 struct sk_buff *segs, *nskb;
3997
3998 /* Estimate the number of fragments in the worst case */
3999 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4000 netif_stop_queue(tp->dev);
4001 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4002 return NETDEV_TX_BUSY;
4003
4004 netif_wake_queue(tp->dev);
4005 }
4006
4007 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4008 if (unlikely(IS_ERR(segs)))
4009 goto tg3_tso_bug_end;
4010
4011 do {
4012 nskb = segs;
4013 segs = segs->next;
4014 nskb->next = NULL;
4015 tg3_start_xmit_dma_bug(nskb, tp->dev);
4016 } while (segs);
4017
4018 tg3_tso_bug_end:
4019 dev_kfree_skb(skb);
4020
4021 return NETDEV_TX_OK;
4022 }
4023
4024 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4025 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4026 */
4027 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4028 {
4029 struct tg3 *tp = netdev_priv(dev);
4030 dma_addr_t mapping;
4031 u32 len, entry, base_flags, mss;
4032 int would_hit_hwbug;
4033
4034 len = skb_headlen(skb);
4035
4036 /* We are running in BH disabled context with netif_tx_lock
4037 * and TX reclaim runs via tp->poll inside of a software
4038 * interrupt. Furthermore, IRQ processing runs lockless so we have
4039 * no IRQ context deadlocks to worry about either. Rejoice!
4040 */
4041 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4042 if (!netif_queue_stopped(dev)) {
4043 netif_stop_queue(dev);
4044
4045 /* This is a hard error, log it. */
4046 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4047 "queue awake!\n", dev->name);
4048 }
4049 return NETDEV_TX_BUSY;
4050 }
4051
4052 entry = tp->tx_prod;
4053 base_flags = 0;
4054 if (skb->ip_summed == CHECKSUM_PARTIAL)
4055 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4056 mss = 0;
4057 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4058 struct iphdr *iph;
4059 int tcp_opt_len, ip_tcp_len, hdr_len;
4060
4061 if (skb_header_cloned(skb) &&
4062 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4063 dev_kfree_skb(skb);
4064 goto out_unlock;
4065 }
4066
4067 tcp_opt_len = tcp_optlen(skb);
4068 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4069
4070 hdr_len = ip_tcp_len + tcp_opt_len;
4071 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4072 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4073 return (tg3_tso_bug(tp, skb));
4074
4075 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4076 TXD_FLAG_CPU_POST_DMA);
4077
4078 iph = ip_hdr(skb);
4079 iph->check = 0;
4080 iph->tot_len = htons(mss + hdr_len);
4081 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4082 tcp_hdr(skb)->check = 0;
4083 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4084 } else
4085 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4086 iph->daddr, 0,
4087 IPPROTO_TCP,
4088 0);
4089
4090 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4091 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4092 if (tcp_opt_len || iph->ihl > 5) {
4093 int tsflags;
4094
4095 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4096 mss |= (tsflags << 11);
4097 }
4098 } else {
4099 if (tcp_opt_len || iph->ihl > 5) {
4100 int tsflags;
4101
4102 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4103 base_flags |= tsflags << 12;
4104 }
4105 }
4106 }
4107 #if TG3_VLAN_TAG_USED
4108 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4109 base_flags |= (TXD_FLAG_VLAN |
4110 (vlan_tx_tag_get(skb) << 16));
4111 #endif
4112
4113 /* Queue skb data, a.k.a. the main skb fragment. */
4114 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4115
4116 tp->tx_buffers[entry].skb = skb;
4117 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4118
4119 would_hit_hwbug = 0;
4120
4121 if (tg3_4g_overflow_test(mapping, len))
4122 would_hit_hwbug = 1;
4123
4124 tg3_set_txd(tp, entry, mapping, len, base_flags,
4125 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4126
4127 entry = NEXT_TX(entry);
4128
4129 /* Now loop through additional data fragments, and queue them. */
4130 if (skb_shinfo(skb)->nr_frags > 0) {
4131 unsigned int i, last;
4132
4133 last = skb_shinfo(skb)->nr_frags - 1;
4134 for (i = 0; i <= last; i++) {
4135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4136
4137 len = frag->size;
4138 mapping = pci_map_page(tp->pdev,
4139 frag->page,
4140 frag->page_offset,
4141 len, PCI_DMA_TODEVICE);
4142
4143 tp->tx_buffers[entry].skb = NULL;
4144 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4145
4146 if (tg3_4g_overflow_test(mapping, len))
4147 would_hit_hwbug = 1;
4148
4149 if (tg3_40bit_overflow_test(tp, mapping, len))
4150 would_hit_hwbug = 1;
4151
4152 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4153 tg3_set_txd(tp, entry, mapping, len,
4154 base_flags, (i == last)|(mss << 1));
4155 else
4156 tg3_set_txd(tp, entry, mapping, len,
4157 base_flags, (i == last));
4158
4159 entry = NEXT_TX(entry);
4160 }
4161 }
4162
4163 if (would_hit_hwbug) {
4164 u32 last_plus_one = entry;
4165 u32 start;
4166
4167 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4168 start &= (TG3_TX_RING_SIZE - 1);
4169
4170 /* If the workaround fails due to memory/mapping
4171 * failure, silently drop this packet.
4172 */
4173 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4174 &start, base_flags, mss))
4175 goto out_unlock;
4176
4177 entry = start;
4178 }
4179
4180 /* Packets are ready, update Tx producer idx local and on card. */
4181 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4182
4183 tp->tx_prod = entry;
4184 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4185 netif_stop_queue(dev);
4186 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4187 netif_wake_queue(tp->dev);
4188 }
4189
4190 out_unlock:
4191 mmiowb();
4192
4193 dev->trans_start = jiffies;
4194
4195 return NETDEV_TX_OK;
4196 }
4197
4198 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4199 int new_mtu)
4200 {
4201 dev->mtu = new_mtu;
4202
4203 if (new_mtu > ETH_DATA_LEN) {
4204 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4205 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4206 ethtool_op_set_tso(dev, 0);
4207 }
4208 else
4209 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4210 } else {
4211 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4212 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4213 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4214 }
4215 }
4216
4217 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4218 {
4219 struct tg3 *tp = netdev_priv(dev);
4220 int err;
4221
4222 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4223 return -EINVAL;
4224
4225 if (!netif_running(dev)) {
4226 /* We'll just catch it later when the
4227 * device is up'd.
4228 */
4229 tg3_set_mtu(dev, tp, new_mtu);
4230 return 0;
4231 }
4232
4233 tg3_netif_stop(tp);
4234
4235 tg3_full_lock(tp, 1);
4236
4237 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4238
4239 tg3_set_mtu(dev, tp, new_mtu);
4240
4241 err = tg3_restart_hw(tp, 0);
4242
4243 if (!err)
4244 tg3_netif_start(tp);
4245
4246 tg3_full_unlock(tp);
4247
4248 return err;
4249 }
4250
4251 /* Free up pending packets in all rx/tx rings.
4252 *
4253 * The chip has been shut down and the driver detached from
4254 * the networking, so no interrupts or new tx packets will
4255 * end up in the driver. tp->{tx,}lock is not held and we are not
4256 * in an interrupt context and thus may sleep.
4257 */
4258 static void tg3_free_rings(struct tg3 *tp)
4259 {
4260 struct ring_info *rxp;
4261 int i;
4262
4263 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4264 rxp = &tp->rx_std_buffers[i];
4265
4266 if (rxp->skb == NULL)
4267 continue;
4268 pci_unmap_single(tp->pdev,
4269 pci_unmap_addr(rxp, mapping),
4270 tp->rx_pkt_buf_sz - tp->rx_offset,
4271 PCI_DMA_FROMDEVICE);
4272 dev_kfree_skb_any(rxp->skb);
4273 rxp->skb = NULL;
4274 }
4275
4276 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4277 rxp = &tp->rx_jumbo_buffers[i];
4278
4279 if (rxp->skb == NULL)
4280 continue;
4281 pci_unmap_single(tp->pdev,
4282 pci_unmap_addr(rxp, mapping),
4283 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4284 PCI_DMA_FROMDEVICE);
4285 dev_kfree_skb_any(rxp->skb);
4286 rxp->skb = NULL;
4287 }
4288
4289 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4290 struct tx_ring_info *txp;
4291 struct sk_buff *skb;
4292 int j;
4293
4294 txp = &tp->tx_buffers[i];
4295 skb = txp->skb;
4296
4297 if (skb == NULL) {
4298 i++;
4299 continue;
4300 }
4301
4302 pci_unmap_single(tp->pdev,
4303 pci_unmap_addr(txp, mapping),
4304 skb_headlen(skb),
4305 PCI_DMA_TODEVICE);
4306 txp->skb = NULL;
4307
4308 i++;
4309
4310 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4311 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4312 pci_unmap_page(tp->pdev,
4313 pci_unmap_addr(txp, mapping),
4314 skb_shinfo(skb)->frags[j].size,
4315 PCI_DMA_TODEVICE);
4316 i++;
4317 }
4318
4319 dev_kfree_skb_any(skb);
4320 }
4321 }
4322
4323 /* Initialize tx/rx rings for packet processing.
4324 *
4325 * The chip has been shut down and the driver detached from
4326 * the networking, so no interrupts or new tx packets will
4327 * end up in the driver. tp->{tx,}lock are held and thus
4328 * we may not sleep.
4329 */
4330 static int tg3_init_rings(struct tg3 *tp)
4331 {
4332 u32 i;
4333
4334 /* Free up all the SKBs. */
4335 tg3_free_rings(tp);
4336
4337 /* Zero out all descriptors. */
4338 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4339 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4340 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4341 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4342
4343 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4344 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4345 (tp->dev->mtu > ETH_DATA_LEN))
4346 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4347
4348 /* Initialize invariants of the rings, we only set this
4349 * stuff once. This works because the card does not
4350 * write into the rx buffer posting rings.
4351 */
4352 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4353 struct tg3_rx_buffer_desc *rxd;
4354
4355 rxd = &tp->rx_std[i];
4356 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4357 << RXD_LEN_SHIFT;
4358 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4359 rxd->opaque = (RXD_OPAQUE_RING_STD |
4360 (i << RXD_OPAQUE_INDEX_SHIFT));
4361 }
4362
4363 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4364 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4365 struct tg3_rx_buffer_desc *rxd;
4366
4367 rxd = &tp->rx_jumbo[i];
4368 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4369 << RXD_LEN_SHIFT;
4370 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4371 RXD_FLAG_JUMBO;
4372 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4373 (i << RXD_OPAQUE_INDEX_SHIFT));
4374 }
4375 }
4376
4377 /* Now allocate fresh SKBs for each rx ring. */
4378 for (i = 0; i < tp->rx_pending; i++) {
4379 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4380 printk(KERN_WARNING PFX
4381 "%s: Using a smaller RX standard ring, "
4382 "only %d out of %d buffers were allocated "
4383 "successfully.\n",
4384 tp->dev->name, i, tp->rx_pending);
4385 if (i == 0)
4386 return -ENOMEM;
4387 tp->rx_pending = i;
4388 break;
4389 }
4390 }
4391
4392 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4393 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4394 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4395 -1, i) < 0) {
4396 printk(KERN_WARNING PFX
4397 "%s: Using a smaller RX jumbo ring, "
4398 "only %d out of %d buffers were "
4399 "allocated successfully.\n",
4400 tp->dev->name, i, tp->rx_jumbo_pending);
4401 if (i == 0) {
4402 tg3_free_rings(tp);
4403 return -ENOMEM;
4404 }
4405 tp->rx_jumbo_pending = i;
4406 break;
4407 }
4408 }
4409 }
4410 return 0;
4411 }
4412
4413 /*
4414 * Must not be invoked with interrupt sources disabled and
4415 * the hardware shutdown down.
4416 */
4417 static void tg3_free_consistent(struct tg3 *tp)
4418 {
4419 kfree(tp->rx_std_buffers);
4420 tp->rx_std_buffers = NULL;
4421 if (tp->rx_std) {
4422 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4423 tp->rx_std, tp->rx_std_mapping);
4424 tp->rx_std = NULL;
4425 }
4426 if (tp->rx_jumbo) {
4427 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4428 tp->rx_jumbo, tp->rx_jumbo_mapping);
4429 tp->rx_jumbo = NULL;
4430 }
4431 if (tp->rx_rcb) {
4432 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4433 tp->rx_rcb, tp->rx_rcb_mapping);
4434 tp->rx_rcb = NULL;
4435 }
4436 if (tp->tx_ring) {
4437 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4438 tp->tx_ring, tp->tx_desc_mapping);
4439 tp->tx_ring = NULL;
4440 }
4441 if (tp->hw_status) {
4442 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4443 tp->hw_status, tp->status_mapping);
4444 tp->hw_status = NULL;
4445 }
4446 if (tp->hw_stats) {
4447 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4448 tp->hw_stats, tp->stats_mapping);
4449 tp->hw_stats = NULL;
4450 }
4451 }
4452
4453 /*
4454 * Must not be invoked with interrupt sources disabled and
4455 * the hardware shutdown down. Can sleep.
4456 */
4457 static int tg3_alloc_consistent(struct tg3 *tp)
4458 {
4459 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4460 (TG3_RX_RING_SIZE +
4461 TG3_RX_JUMBO_RING_SIZE)) +
4462 (sizeof(struct tx_ring_info) *
4463 TG3_TX_RING_SIZE),
4464 GFP_KERNEL);
4465 if (!tp->rx_std_buffers)
4466 return -ENOMEM;
4467
4468 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4469 tp->tx_buffers = (struct tx_ring_info *)
4470 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4471
4472 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4473 &tp->rx_std_mapping);
4474 if (!tp->rx_std)
4475 goto err_out;
4476
4477 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4478 &tp->rx_jumbo_mapping);
4479
4480 if (!tp->rx_jumbo)
4481 goto err_out;
4482
4483 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4484 &tp->rx_rcb_mapping);
4485 if (!tp->rx_rcb)
4486 goto err_out;
4487
4488 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4489 &tp->tx_desc_mapping);
4490 if (!tp->tx_ring)
4491 goto err_out;
4492
4493 tp->hw_status = pci_alloc_consistent(tp->pdev,
4494 TG3_HW_STATUS_SIZE,
4495 &tp->status_mapping);
4496 if (!tp->hw_status)
4497 goto err_out;
4498
4499 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4500 sizeof(struct tg3_hw_stats),
4501 &tp->stats_mapping);
4502 if (!tp->hw_stats)
4503 goto err_out;
4504
4505 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4506 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4507
4508 return 0;
4509
4510 err_out:
4511 tg3_free_consistent(tp);
4512 return -ENOMEM;
4513 }
4514
4515 #define MAX_WAIT_CNT 1000
4516
4517 /* To stop a block, clear the enable bit and poll till it
4518 * clears. tp->lock is held.
4519 */
4520 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4521 {
4522 unsigned int i;
4523 u32 val;
4524
4525 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4526 switch (ofs) {
4527 case RCVLSC_MODE:
4528 case DMAC_MODE:
4529 case MBFREE_MODE:
4530 case BUFMGR_MODE:
4531 case MEMARB_MODE:
4532 /* We can't enable/disable these bits of the
4533 * 5705/5750, just say success.
4534 */
4535 return 0;
4536
4537 default:
4538 break;
4539 };
4540 }
4541
4542 val = tr32(ofs);
4543 val &= ~enable_bit;
4544 tw32_f(ofs, val);
4545
4546 for (i = 0; i < MAX_WAIT_CNT; i++) {
4547 udelay(100);
4548 val = tr32(ofs);
4549 if ((val & enable_bit) == 0)
4550 break;
4551 }
4552
4553 if (i == MAX_WAIT_CNT && !silent) {
4554 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4555 "ofs=%lx enable_bit=%x\n",
4556 ofs, enable_bit);
4557 return -ENODEV;
4558 }
4559
4560 return 0;
4561 }
4562
4563 /* tp->lock is held. */
4564 static int tg3_abort_hw(struct tg3 *tp, int silent)
4565 {
4566 int i, err;
4567
4568 tg3_disable_ints(tp);
4569
4570 tp->rx_mode &= ~RX_MODE_ENABLE;
4571 tw32_f(MAC_RX_MODE, tp->rx_mode);
4572 udelay(10);
4573
4574 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4575 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4576 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4577 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4578 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4579 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4580
4581 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4582 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4583 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4584 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4585 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4586 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4587 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4588
4589 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4590 tw32_f(MAC_MODE, tp->mac_mode);
4591 udelay(40);
4592
4593 tp->tx_mode &= ~TX_MODE_ENABLE;
4594 tw32_f(MAC_TX_MODE, tp->tx_mode);
4595
4596 for (i = 0; i < MAX_WAIT_CNT; i++) {
4597 udelay(100);
4598 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4599 break;
4600 }
4601 if (i >= MAX_WAIT_CNT) {
4602 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4603 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4604 tp->dev->name, tr32(MAC_TX_MODE));
4605 err |= -ENODEV;
4606 }
4607
4608 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4609 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4610 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4611
4612 tw32(FTQ_RESET, 0xffffffff);
4613 tw32(FTQ_RESET, 0x00000000);
4614
4615 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4616 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4617
4618 if (tp->hw_status)
4619 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4620 if (tp->hw_stats)
4621 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4622
4623 return err;
4624 }
4625
4626 /* tp->lock is held. */
4627 static int tg3_nvram_lock(struct tg3 *tp)
4628 {
4629 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4630 int i;
4631
4632 if (tp->nvram_lock_cnt == 0) {
4633 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4634 for (i = 0; i < 8000; i++) {
4635 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4636 break;
4637 udelay(20);
4638 }
4639 if (i == 8000) {
4640 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4641 return -ENODEV;
4642 }
4643 }
4644 tp->nvram_lock_cnt++;
4645 }
4646 return 0;
4647 }
4648
4649 /* tp->lock is held. */
4650 static void tg3_nvram_unlock(struct tg3 *tp)
4651 {
4652 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4653 if (tp->nvram_lock_cnt > 0)
4654 tp->nvram_lock_cnt--;
4655 if (tp->nvram_lock_cnt == 0)
4656 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4657 }
4658 }
4659
4660 /* tp->lock is held. */
4661 static void tg3_enable_nvram_access(struct tg3 *tp)
4662 {
4663 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4664 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4665 u32 nvaccess = tr32(NVRAM_ACCESS);
4666
4667 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4668 }
4669 }
4670
4671 /* tp->lock is held. */
4672 static void tg3_disable_nvram_access(struct tg3 *tp)
4673 {
4674 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4675 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4676 u32 nvaccess = tr32(NVRAM_ACCESS);
4677
4678 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4679 }
4680 }
4681
4682 /* tp->lock is held. */
4683 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4684 {
4685 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4686 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4687
4688 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4689 switch (kind) {
4690 case RESET_KIND_INIT:
4691 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4692 DRV_STATE_START);
4693 break;
4694
4695 case RESET_KIND_SHUTDOWN:
4696 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4697 DRV_STATE_UNLOAD);
4698 break;
4699
4700 case RESET_KIND_SUSPEND:
4701 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4702 DRV_STATE_SUSPEND);
4703 break;
4704
4705 default:
4706 break;
4707 };
4708 }
4709 }
4710
4711 /* tp->lock is held. */
4712 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4713 {
4714 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4715 switch (kind) {
4716 case RESET_KIND_INIT:
4717 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4718 DRV_STATE_START_DONE);
4719 break;
4720
4721 case RESET_KIND_SHUTDOWN:
4722 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4723 DRV_STATE_UNLOAD_DONE);
4724 break;
4725
4726 default:
4727 break;
4728 };
4729 }
4730 }
4731
4732 /* tp->lock is held. */
4733 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4734 {
4735 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4736 switch (kind) {
4737 case RESET_KIND_INIT:
4738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4739 DRV_STATE_START);
4740 break;
4741
4742 case RESET_KIND_SHUTDOWN:
4743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4744 DRV_STATE_UNLOAD);
4745 break;
4746
4747 case RESET_KIND_SUSPEND:
4748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4749 DRV_STATE_SUSPEND);
4750 break;
4751
4752 default:
4753 break;
4754 };
4755 }
4756 }
4757
4758 static int tg3_poll_fw(struct tg3 *tp)
4759 {
4760 int i;
4761 u32 val;
4762
4763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4764 /* Wait up to 20ms for init done. */
4765 for (i = 0; i < 200; i++) {
4766 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4767 return 0;
4768 udelay(100);
4769 }
4770 return -ENODEV;
4771 }
4772
4773 /* Wait for firmware initialization to complete. */
4774 for (i = 0; i < 100000; i++) {
4775 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4776 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4777 break;
4778 udelay(10);
4779 }
4780
4781 /* Chip might not be fitted with firmware. Some Sun onboard
4782 * parts are configured like that. So don't signal the timeout
4783 * of the above loop as an error, but do report the lack of
4784 * running firmware once.
4785 */
4786 if (i >= 100000 &&
4787 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4788 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4789
4790 printk(KERN_INFO PFX "%s: No firmware running.\n",
4791 tp->dev->name);
4792 }
4793
4794 return 0;
4795 }
4796
4797 static void tg3_stop_fw(struct tg3 *);
4798
4799 /* tp->lock is held. */
4800 static int tg3_chip_reset(struct tg3 *tp)
4801 {
4802 u32 val;
4803 void (*write_op)(struct tg3 *, u32, u32);
4804 int err;
4805
4806 tg3_nvram_lock(tp);
4807
4808 /* No matching tg3_nvram_unlock() after this because
4809 * chip reset below will undo the nvram lock.
4810 */
4811 tp->nvram_lock_cnt = 0;
4812
4813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4816 tw32(GRC_FASTBOOT_PC, 0);
4817
4818 /*
4819 * We must avoid the readl() that normally takes place.
4820 * It locks machines, causes machine checks, and other
4821 * fun things. So, temporarily disable the 5701
4822 * hardware workaround, while we do the reset.
4823 */
4824 write_op = tp->write32;
4825 if (write_op == tg3_write_flush_reg32)
4826 tp->write32 = tg3_write32;
4827
4828 /* Prevent the irq handler from reading or writing PCI registers
4829 * during chip reset when the memory enable bit in the PCI command
4830 * register may be cleared. The chip does not generate interrupt
4831 * at this time, but the irq handler may still be called due to irq
4832 * sharing or irqpoll.
4833 */
4834 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4835 if (tp->hw_status) {
4836 tp->hw_status->status = 0;
4837 tp->hw_status->status_tag = 0;
4838 }
4839 tp->last_tag = 0;
4840 smp_mb();
4841 synchronize_irq(tp->pdev->irq);
4842
4843 /* do the reset */
4844 val = GRC_MISC_CFG_CORECLK_RESET;
4845
4846 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4847 if (tr32(0x7e2c) == 0x60) {
4848 tw32(0x7e2c, 0x20);
4849 }
4850 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4851 tw32(GRC_MISC_CFG, (1 << 29));
4852 val |= (1 << 29);
4853 }
4854 }
4855
4856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4857 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4858 tw32(GRC_VCPU_EXT_CTRL,
4859 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4860 }
4861
4862 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4863 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4864 tw32(GRC_MISC_CFG, val);
4865
4866 /* restore 5701 hardware bug workaround write method */
4867 tp->write32 = write_op;
4868
4869 /* Unfortunately, we have to delay before the PCI read back.
4870 * Some 575X chips even will not respond to a PCI cfg access
4871 * when the reset command is given to the chip.
4872 *
4873 * How do these hardware designers expect things to work
4874 * properly if the PCI write is posted for a long period
4875 * of time? It is always necessary to have some method by
4876 * which a register read back can occur to push the write
4877 * out which does the reset.
4878 *
4879 * For most tg3 variants the trick below was working.
4880 * Ho hum...
4881 */
4882 udelay(120);
4883
4884 /* Flush PCI posted writes. The normal MMIO registers
4885 * are inaccessible at this time so this is the only
4886 * way to make this reliably (actually, this is no longer
4887 * the case, see above). I tried to use indirect
4888 * register read/write but this upset some 5701 variants.
4889 */
4890 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4891
4892 udelay(120);
4893
4894 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4895 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4896 int i;
4897 u32 cfg_val;
4898
4899 /* Wait for link training to complete. */
4900 for (i = 0; i < 5000; i++)
4901 udelay(100);
4902
4903 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4904 pci_write_config_dword(tp->pdev, 0xc4,
4905 cfg_val | (1 << 15));
4906 }
4907 /* Set PCIE max payload size and clear error status. */
4908 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4909 }
4910
4911 /* Re-enable indirect register accesses. */
4912 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4913 tp->misc_host_ctrl);
4914
4915 /* Set MAX PCI retry to zero. */
4916 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4917 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4918 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4919 val |= PCISTATE_RETRY_SAME_DMA;
4920 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4921
4922 pci_restore_state(tp->pdev);
4923
4924 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4925
4926 /* Make sure PCI-X relaxed ordering bit is clear. */
4927 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4928 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4929 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4930
4931 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4932 u32 val;
4933
4934 /* Chip reset on 5780 will reset MSI enable bit,
4935 * so need to restore it.
4936 */
4937 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4938 u16 ctrl;
4939
4940 pci_read_config_word(tp->pdev,
4941 tp->msi_cap + PCI_MSI_FLAGS,
4942 &ctrl);
4943 pci_write_config_word(tp->pdev,
4944 tp->msi_cap + PCI_MSI_FLAGS,
4945 ctrl | PCI_MSI_FLAGS_ENABLE);
4946 val = tr32(MSGINT_MODE);
4947 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4948 }
4949
4950 val = tr32(MEMARB_MODE);
4951 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4952
4953 } else
4954 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4955
4956 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4957 tg3_stop_fw(tp);
4958 tw32(0x5000, 0x400);
4959 }
4960
4961 tw32(GRC_MODE, tp->grc_mode);
4962
4963 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4964 u32 val = tr32(0xc4);
4965
4966 tw32(0xc4, val | (1 << 15));
4967 }
4968
4969 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4971 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4972 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4973 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4974 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4975 }
4976
4977 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4978 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4979 tw32_f(MAC_MODE, tp->mac_mode);
4980 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4981 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4982 tw32_f(MAC_MODE, tp->mac_mode);
4983 } else
4984 tw32_f(MAC_MODE, 0);
4985 udelay(40);
4986
4987 err = tg3_poll_fw(tp);
4988 if (err)
4989 return err;
4990
4991 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4992 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4993 u32 val = tr32(0x7c00);
4994
4995 tw32(0x7c00, val | (1 << 25));
4996 }
4997
4998 /* Reprobe ASF enable state. */
4999 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5000 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5001 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5002 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5003 u32 nic_cfg;
5004
5005 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5006 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5007 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5008 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5009 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5010 }
5011 }
5012
5013 return 0;
5014 }
5015
5016 /* tp->lock is held. */
5017 static void tg3_stop_fw(struct tg3 *tp)
5018 {
5019 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5020 u32 val;
5021 int i;
5022
5023 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5024 val = tr32(GRC_RX_CPU_EVENT);
5025 val |= (1 << 14);
5026 tw32(GRC_RX_CPU_EVENT, val);
5027
5028 /* Wait for RX cpu to ACK the event. */
5029 for (i = 0; i < 100; i++) {
5030 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5031 break;
5032 udelay(1);
5033 }
5034 }
5035 }
5036
5037 /* tp->lock is held. */
5038 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5039 {
5040 int err;
5041
5042 tg3_stop_fw(tp);
5043
5044 tg3_write_sig_pre_reset(tp, kind);
5045
5046 tg3_abort_hw(tp, silent);
5047 err = tg3_chip_reset(tp);
5048
5049 tg3_write_sig_legacy(tp, kind);
5050 tg3_write_sig_post_reset(tp, kind);
5051
5052 if (err)
5053 return err;
5054
5055 return 0;
5056 }
5057
5058 #define TG3_FW_RELEASE_MAJOR 0x0
5059 #define TG3_FW_RELASE_MINOR 0x0
5060 #define TG3_FW_RELEASE_FIX 0x0
5061 #define TG3_FW_START_ADDR 0x08000000
5062 #define TG3_FW_TEXT_ADDR 0x08000000
5063 #define TG3_FW_TEXT_LEN 0x9c0
5064 #define TG3_FW_RODATA_ADDR 0x080009c0
5065 #define TG3_FW_RODATA_LEN 0x60
5066 #define TG3_FW_DATA_ADDR 0x08000a40
5067 #define TG3_FW_DATA_LEN 0x20
5068 #define TG3_FW_SBSS_ADDR 0x08000a60
5069 #define TG3_FW_SBSS_LEN 0xc
5070 #define TG3_FW_BSS_ADDR 0x08000a70
5071 #define TG3_FW_BSS_LEN 0x10
5072
5073 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5074 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5075 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5076 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5077 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5078 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5079 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5080 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5081 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5082 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5083 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5084 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5085 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5086 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5087 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5088 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5089 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5090 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5091 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5092 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5093 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5094 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5095 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5096 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5097 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5098 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5099 0, 0, 0, 0, 0, 0,
5100 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5101 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5102 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5103 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5104 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5105 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5106 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5107 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5108 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5109 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5110 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5111 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5112 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5114 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5115 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5116 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5117 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5118 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5119 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5120 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5121 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5122 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5123 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5124 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5125 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5126 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5127 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5128 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5129 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5130 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5131 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5132 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5133 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5134 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5135 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5136 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5137 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5138 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5139 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5140 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5141 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5142 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5143 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5144 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5145 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5146 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5147 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5148 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5149 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5150 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5151 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5152 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5153 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5154 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5155 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5156 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5157 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5158 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5159 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5160 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5161 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5162 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5163 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5164 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5165 };
5166
5167 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5168 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5169 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5170 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5171 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5172 0x00000000
5173 };
5174
5175 #if 0 /* All zeros, don't eat up space with it. */
5176 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5177 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5178 0x00000000, 0x00000000, 0x00000000, 0x00000000
5179 };
5180 #endif
5181
5182 #define RX_CPU_SCRATCH_BASE 0x30000
5183 #define RX_CPU_SCRATCH_SIZE 0x04000
5184 #define TX_CPU_SCRATCH_BASE 0x34000
5185 #define TX_CPU_SCRATCH_SIZE 0x04000
5186
5187 /* tp->lock is held. */
5188 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5189 {
5190 int i;
5191
5192 BUG_ON(offset == TX_CPU_BASE &&
5193 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5194
5195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5196 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5197
5198 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5199 return 0;
5200 }
5201 if (offset == RX_CPU_BASE) {
5202 for (i = 0; i < 10000; i++) {
5203 tw32(offset + CPU_STATE, 0xffffffff);
5204 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5205 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5206 break;
5207 }
5208
5209 tw32(offset + CPU_STATE, 0xffffffff);
5210 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5211 udelay(10);
5212 } else {
5213 for (i = 0; i < 10000; i++) {
5214 tw32(offset + CPU_STATE, 0xffffffff);
5215 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5216 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5217 break;
5218 }
5219 }
5220
5221 if (i >= 10000) {
5222 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5223 "and %s CPU\n",
5224 tp->dev->name,
5225 (offset == RX_CPU_BASE ? "RX" : "TX"));
5226 return -ENODEV;
5227 }
5228
5229 /* Clear firmware's nvram arbitration. */
5230 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5231 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5232 return 0;
5233 }
5234
5235 struct fw_info {
5236 unsigned int text_base;
5237 unsigned int text_len;
5238 const u32 *text_data;
5239 unsigned int rodata_base;
5240 unsigned int rodata_len;
5241 const u32 *rodata_data;
5242 unsigned int data_base;
5243 unsigned int data_len;
5244 const u32 *data_data;
5245 };
5246
5247 /* tp->lock is held. */
5248 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5249 int cpu_scratch_size, struct fw_info *info)
5250 {
5251 int err, lock_err, i;
5252 void (*write_op)(struct tg3 *, u32, u32);
5253
5254 if (cpu_base == TX_CPU_BASE &&
5255 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5256 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5257 "TX cpu firmware on %s which is 5705.\n",
5258 tp->dev->name);
5259 return -EINVAL;
5260 }
5261
5262 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5263 write_op = tg3_write_mem;
5264 else
5265 write_op = tg3_write_indirect_reg32;
5266
5267 /* It is possible that bootcode is still loading at this point.
5268 * Get the nvram lock first before halting the cpu.
5269 */
5270 lock_err = tg3_nvram_lock(tp);
5271 err = tg3_halt_cpu(tp, cpu_base);
5272 if (!lock_err)
5273 tg3_nvram_unlock(tp);
5274 if (err)
5275 goto out;
5276
5277 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5278 write_op(tp, cpu_scratch_base + i, 0);
5279 tw32(cpu_base + CPU_STATE, 0xffffffff);
5280 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5281 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5282 write_op(tp, (cpu_scratch_base +
5283 (info->text_base & 0xffff) +
5284 (i * sizeof(u32))),
5285 (info->text_data ?
5286 info->text_data[i] : 0));
5287 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5288 write_op(tp, (cpu_scratch_base +
5289 (info->rodata_base & 0xffff) +
5290 (i * sizeof(u32))),
5291 (info->rodata_data ?
5292 info->rodata_data[i] : 0));
5293 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5294 write_op(tp, (cpu_scratch_base +
5295 (info->data_base & 0xffff) +
5296 (i * sizeof(u32))),
5297 (info->data_data ?
5298 info->data_data[i] : 0));
5299
5300 err = 0;
5301
5302 out:
5303 return err;
5304 }
5305
5306 /* tp->lock is held. */
5307 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5308 {
5309 struct fw_info info;
5310 int err, i;
5311
5312 info.text_base = TG3_FW_TEXT_ADDR;
5313 info.text_len = TG3_FW_TEXT_LEN;
5314 info.text_data = &tg3FwText[0];
5315 info.rodata_base = TG3_FW_RODATA_ADDR;
5316 info.rodata_len = TG3_FW_RODATA_LEN;
5317 info.rodata_data = &tg3FwRodata[0];
5318 info.data_base = TG3_FW_DATA_ADDR;
5319 info.data_len = TG3_FW_DATA_LEN;
5320 info.data_data = NULL;
5321
5322 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5323 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5324 &info);
5325 if (err)
5326 return err;
5327
5328 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5329 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5330 &info);
5331 if (err)
5332 return err;
5333
5334 /* Now startup only the RX cpu. */
5335 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5336 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5337
5338 for (i = 0; i < 5; i++) {
5339 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5340 break;
5341 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5342 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5343 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5344 udelay(1000);
5345 }
5346 if (i >= 5) {
5347 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5348 "to set RX CPU PC, is %08x should be %08x\n",
5349 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5350 TG3_FW_TEXT_ADDR);
5351 return -ENODEV;
5352 }
5353 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5354 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5355
5356 return 0;
5357 }
5358
5359
5360 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5361 #define TG3_TSO_FW_RELASE_MINOR 0x6
5362 #define TG3_TSO_FW_RELEASE_FIX 0x0
5363 #define TG3_TSO_FW_START_ADDR 0x08000000
5364 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5365 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5366 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5367 #define TG3_TSO_FW_RODATA_LEN 0x60
5368 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5369 #define TG3_TSO_FW_DATA_LEN 0x30
5370 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5371 #define TG3_TSO_FW_SBSS_LEN 0x2c
5372 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5373 #define TG3_TSO_FW_BSS_LEN 0x894
5374
5375 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5376 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5377 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5378 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5379 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5380 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5381 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5382 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5383 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5384 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5385 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5386 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5387 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5388 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5389 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5390 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5391 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5392 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5393 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5394 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5395 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5396 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5397 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5398 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5399 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5400 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5401 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5402 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5403 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5404 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5405 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5406 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5407 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5408 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5409 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5410 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5411 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5412 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5413 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5414 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5415 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5416 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5417 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5418 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5419 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5420 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5421 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5422 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5423 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5424 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5425 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5426 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5427 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5428 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5429 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5430 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5431 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5432 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5433 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5434 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5435 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5436 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5437 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5438 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5439 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5440 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5441 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5442 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5443 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5444 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5445 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5446 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5447 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5448 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5449 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5450 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5451 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5452 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5453 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5454 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5455 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5456 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5457 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5458 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5459 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5460 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5461 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5462 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5463 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5464 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5465 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5466 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5467 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5468 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5469 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5470 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5471 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5472 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5473 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5474 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5475 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5476 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5477 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5478 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5479 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5480 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5481 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5482 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5483 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5484 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5485 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5486 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5487 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5488 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5489 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5490 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5491 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5492 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5493 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5494 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5495 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5496 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5497 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5498 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5499 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5500 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5501 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5502 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5503 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5504 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5505 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5506 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5507 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5508 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5509 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5510 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5511 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5512 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5513 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5514 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5515 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5516 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5517 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5518 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5519 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5520 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5521 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5522 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5523 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5524 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5525 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5526 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5527 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5528 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5529 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5530 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5531 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5532 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5533 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5534 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5535 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5536 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5537 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5538 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5539 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5540 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5541 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5542 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5543 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5544 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5545 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5546 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5547 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5548 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5549 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5550 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5551 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5552 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5553 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5554 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5555 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5556 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5557 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5558 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5559 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5560 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5561 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5562 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5563 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5564 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5565 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5566 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5567 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5568 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5569 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5570 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5571 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5572 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5573 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5574 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5575 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5576 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5577 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5578 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5579 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5580 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5581 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5582 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5583 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5584 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5585 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5586 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5587 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5588 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5589 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5590 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5591 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5592 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5593 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5594 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5595 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5596 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5597 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5598 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5599 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5600 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5601 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5602 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5603 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5604 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5605 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5606 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5607 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5608 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5609 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5610 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5611 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5612 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5613 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5614 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5615 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5616 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5617 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5618 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5619 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5620 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5621 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5622 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5623 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5624 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5625 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5626 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5627 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5628 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5629 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5630 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5631 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5632 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5633 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5634 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5635 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5636 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5637 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5638 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5639 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5640 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5641 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5642 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5643 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5644 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5645 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5646 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5647 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5648 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5649 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5650 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5651 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5652 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5653 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5654 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5655 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5656 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5657 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5658 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5659 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5660 };
5661
5662 static const u32 tg3TsoFwRodata[] = {
5663 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5664 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5665 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5666 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5667 0x00000000,
5668 };
5669
5670 static const u32 tg3TsoFwData[] = {
5671 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5672 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5673 0x00000000,
5674 };
5675
5676 /* 5705 needs a special version of the TSO firmware. */
5677 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5678 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5679 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5680 #define TG3_TSO5_FW_START_ADDR 0x00010000
5681 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5682 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5683 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5684 #define TG3_TSO5_FW_RODATA_LEN 0x50
5685 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5686 #define TG3_TSO5_FW_DATA_LEN 0x20
5687 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5688 #define TG3_TSO5_FW_SBSS_LEN 0x28
5689 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5690 #define TG3_TSO5_FW_BSS_LEN 0x88
5691
5692 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5693 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5694 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5695 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5696 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5697 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5698 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5699 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5700 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5701 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5702 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5703 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5704 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5705 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5706 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5707 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5708 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5709 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5710 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5711 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5712 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5713 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5714 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5715 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5716 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5717 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5718 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5719 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5720 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5721 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5722 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5723 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5724 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5725 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5726 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5727 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5728 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5729 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5730 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5731 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5732 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5733 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5734 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5735 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5736 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5737 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5738 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5739 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5740 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5741 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5742 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5743 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5744 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5745 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5746 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5747 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5748 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5749 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5750 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5751 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5752 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5753 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5754 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5755 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5756 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5757 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5758 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5759 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5760 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5761 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5762 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5763 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5764 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5765 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5766 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5767 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5768 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5769 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5770 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5771 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5772 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5773 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5774 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5775 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5776 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5777 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5778 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5779 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5780 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5781 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5782 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5783 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5784 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5785 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5786 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5787 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5788 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5789 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5790 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5791 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5792 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5793 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5794 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5795 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5796 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5797 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5798 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5799 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5800 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5801 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5802 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5803 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5804 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5805 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5806 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5807 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5808 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5809 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5810 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5811 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5812 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5813 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5814 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5815 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5816 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5817 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5818 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5819 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5820 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5821 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5822 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5823 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5824 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5825 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5826 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5827 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5828 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5829 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5830 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5831 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5832 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5833 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5834 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5835 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5836 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5837 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5838 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5839 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5840 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5841 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5842 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5843 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5844 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5845 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5846 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5847 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5848 0x00000000, 0x00000000, 0x00000000,
5849 };
5850
5851 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5852 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5853 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5854 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5855 0x00000000, 0x00000000, 0x00000000,
5856 };
5857
5858 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5859 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5860 0x00000000, 0x00000000, 0x00000000,
5861 };
5862
5863 /* tp->lock is held. */
5864 static int tg3_load_tso_firmware(struct tg3 *tp)
5865 {
5866 struct fw_info info;
5867 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5868 int err, i;
5869
5870 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5871 return 0;
5872
5873 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5874 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5875 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5876 info.text_data = &tg3Tso5FwText[0];
5877 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5878 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5879 info.rodata_data = &tg3Tso5FwRodata[0];
5880 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5881 info.data_len = TG3_TSO5_FW_DATA_LEN;
5882 info.data_data = &tg3Tso5FwData[0];
5883 cpu_base = RX_CPU_BASE;
5884 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5885 cpu_scratch_size = (info.text_len +
5886 info.rodata_len +
5887 info.data_len +
5888 TG3_TSO5_FW_SBSS_LEN +
5889 TG3_TSO5_FW_BSS_LEN);
5890 } else {
5891 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5892 info.text_len = TG3_TSO_FW_TEXT_LEN;
5893 info.text_data = &tg3TsoFwText[0];
5894 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5895 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5896 info.rodata_data = &tg3TsoFwRodata[0];
5897 info.data_base = TG3_TSO_FW_DATA_ADDR;
5898 info.data_len = TG3_TSO_FW_DATA_LEN;
5899 info.data_data = &tg3TsoFwData[0];
5900 cpu_base = TX_CPU_BASE;
5901 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5902 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5903 }
5904
5905 err = tg3_load_firmware_cpu(tp, cpu_base,
5906 cpu_scratch_base, cpu_scratch_size,
5907 &info);
5908 if (err)
5909 return err;
5910
5911 /* Now startup the cpu. */
5912 tw32(cpu_base + CPU_STATE, 0xffffffff);
5913 tw32_f(cpu_base + CPU_PC, info.text_base);
5914
5915 for (i = 0; i < 5; i++) {
5916 if (tr32(cpu_base + CPU_PC) == info.text_base)
5917 break;
5918 tw32(cpu_base + CPU_STATE, 0xffffffff);
5919 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5920 tw32_f(cpu_base + CPU_PC, info.text_base);
5921 udelay(1000);
5922 }
5923 if (i >= 5) {
5924 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5925 "to set CPU PC, is %08x should be %08x\n",
5926 tp->dev->name, tr32(cpu_base + CPU_PC),
5927 info.text_base);
5928 return -ENODEV;
5929 }
5930 tw32(cpu_base + CPU_STATE, 0xffffffff);
5931 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5932 return 0;
5933 }
5934
5935
5936 /* tp->lock is held. */
5937 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
5938 {
5939 u32 addr_high, addr_low;
5940 int i;
5941
5942 addr_high = ((tp->dev->dev_addr[0] << 8) |
5943 tp->dev->dev_addr[1]);
5944 addr_low = ((tp->dev->dev_addr[2] << 24) |
5945 (tp->dev->dev_addr[3] << 16) |
5946 (tp->dev->dev_addr[4] << 8) |
5947 (tp->dev->dev_addr[5] << 0));
5948 for (i = 0; i < 4; i++) {
5949 if (i == 1 && skip_mac_1)
5950 continue;
5951 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5952 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5953 }
5954
5955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5957 for (i = 0; i < 12; i++) {
5958 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5959 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5960 }
5961 }
5962
5963 addr_high = (tp->dev->dev_addr[0] +
5964 tp->dev->dev_addr[1] +
5965 tp->dev->dev_addr[2] +
5966 tp->dev->dev_addr[3] +
5967 tp->dev->dev_addr[4] +
5968 tp->dev->dev_addr[5]) &
5969 TX_BACKOFF_SEED_MASK;
5970 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5971 }
5972
5973 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5974 {
5975 struct tg3 *tp = netdev_priv(dev);
5976 struct sockaddr *addr = p;
5977 int err = 0, skip_mac_1 = 0;
5978
5979 if (!is_valid_ether_addr(addr->sa_data))
5980 return -EINVAL;
5981
5982 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5983
5984 if (!netif_running(dev))
5985 return 0;
5986
5987 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5988 u32 addr0_high, addr0_low, addr1_high, addr1_low;
5989
5990 addr0_high = tr32(MAC_ADDR_0_HIGH);
5991 addr0_low = tr32(MAC_ADDR_0_LOW);
5992 addr1_high = tr32(MAC_ADDR_1_HIGH);
5993 addr1_low = tr32(MAC_ADDR_1_LOW);
5994
5995 /* Skip MAC addr 1 if ASF is using it. */
5996 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
5997 !(addr1_high == 0 && addr1_low == 0))
5998 skip_mac_1 = 1;
5999 }
6000 spin_lock_bh(&tp->lock);
6001 __tg3_set_mac_addr(tp, skip_mac_1);
6002 spin_unlock_bh(&tp->lock);
6003
6004 return err;
6005 }
6006
6007 /* tp->lock is held. */
6008 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6009 dma_addr_t mapping, u32 maxlen_flags,
6010 u32 nic_addr)
6011 {
6012 tg3_write_mem(tp,
6013 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6014 ((u64) mapping >> 32));
6015 tg3_write_mem(tp,
6016 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6017 ((u64) mapping & 0xffffffff));
6018 tg3_write_mem(tp,
6019 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6020 maxlen_flags);
6021
6022 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6023 tg3_write_mem(tp,
6024 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6025 nic_addr);
6026 }
6027
6028 static void __tg3_set_rx_mode(struct net_device *);
6029 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6030 {
6031 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6032 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6033 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6034 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6035 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6036 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6037 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6038 }
6039 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6040 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6041 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6042 u32 val = ec->stats_block_coalesce_usecs;
6043
6044 if (!netif_carrier_ok(tp->dev))
6045 val = 0;
6046
6047 tw32(HOSTCC_STAT_COAL_TICKS, val);
6048 }
6049 }
6050
6051 /* tp->lock is held. */
6052 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6053 {
6054 u32 val, rdmac_mode;
6055 int i, err, limit;
6056
6057 tg3_disable_ints(tp);
6058
6059 tg3_stop_fw(tp);
6060
6061 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6062
6063 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6064 tg3_abort_hw(tp, 1);
6065 }
6066
6067 if (reset_phy)
6068 tg3_phy_reset(tp);
6069
6070 err = tg3_chip_reset(tp);
6071 if (err)
6072 return err;
6073
6074 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6075
6076 /* This works around an issue with Athlon chipsets on
6077 * B3 tigon3 silicon. This bit has no effect on any
6078 * other revision. But do not set this on PCI Express
6079 * chips.
6080 */
6081 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6082 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6083 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6084
6085 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6086 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6087 val = tr32(TG3PCI_PCISTATE);
6088 val |= PCISTATE_RETRY_SAME_DMA;
6089 tw32(TG3PCI_PCISTATE, val);
6090 }
6091
6092 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6093 /* Enable some hw fixes. */
6094 val = tr32(TG3PCI_MSI_DATA);
6095 val |= (1 << 26) | (1 << 28) | (1 << 29);
6096 tw32(TG3PCI_MSI_DATA, val);
6097 }
6098
6099 /* Descriptor ring init may make accesses to the
6100 * NIC SRAM area to setup the TX descriptors, so we
6101 * can only do this after the hardware has been
6102 * successfully reset.
6103 */
6104 err = tg3_init_rings(tp);
6105 if (err)
6106 return err;
6107
6108 /* This value is determined during the probe time DMA
6109 * engine test, tg3_test_dma.
6110 */
6111 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6112
6113 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6114 GRC_MODE_4X_NIC_SEND_RINGS |
6115 GRC_MODE_NO_TX_PHDR_CSUM |
6116 GRC_MODE_NO_RX_PHDR_CSUM);
6117 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6118
6119 /* Pseudo-header checksum is done by hardware logic and not
6120 * the offload processers, so make the chip do the pseudo-
6121 * header checksums on receive. For transmit it is more
6122 * convenient to do the pseudo-header checksum in software
6123 * as Linux does that on transmit for us in all cases.
6124 */
6125 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6126
6127 tw32(GRC_MODE,
6128 tp->grc_mode |
6129 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6130
6131 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6132 val = tr32(GRC_MISC_CFG);
6133 val &= ~0xff;
6134 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6135 tw32(GRC_MISC_CFG, val);
6136
6137 /* Initialize MBUF/DESC pool. */
6138 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6139 /* Do nothing. */
6140 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6141 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6143 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6144 else
6145 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6146 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6147 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6148 }
6149 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6150 int fw_len;
6151
6152 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6153 TG3_TSO5_FW_RODATA_LEN +
6154 TG3_TSO5_FW_DATA_LEN +
6155 TG3_TSO5_FW_SBSS_LEN +
6156 TG3_TSO5_FW_BSS_LEN);
6157 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6158 tw32(BUFMGR_MB_POOL_ADDR,
6159 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6160 tw32(BUFMGR_MB_POOL_SIZE,
6161 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6162 }
6163
6164 if (tp->dev->mtu <= ETH_DATA_LEN) {
6165 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6166 tp->bufmgr_config.mbuf_read_dma_low_water);
6167 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6168 tp->bufmgr_config.mbuf_mac_rx_low_water);
6169 tw32(BUFMGR_MB_HIGH_WATER,
6170 tp->bufmgr_config.mbuf_high_water);
6171 } else {
6172 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6173 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6174 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6175 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6176 tw32(BUFMGR_MB_HIGH_WATER,
6177 tp->bufmgr_config.mbuf_high_water_jumbo);
6178 }
6179 tw32(BUFMGR_DMA_LOW_WATER,
6180 tp->bufmgr_config.dma_low_water);
6181 tw32(BUFMGR_DMA_HIGH_WATER,
6182 tp->bufmgr_config.dma_high_water);
6183
6184 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6185 for (i = 0; i < 2000; i++) {
6186 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6187 break;
6188 udelay(10);
6189 }
6190 if (i >= 2000) {
6191 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6192 tp->dev->name);
6193 return -ENODEV;
6194 }
6195
6196 /* Setup replenish threshold. */
6197 val = tp->rx_pending / 8;
6198 if (val == 0)
6199 val = 1;
6200 else if (val > tp->rx_std_max_post)
6201 val = tp->rx_std_max_post;
6202 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6203 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6204 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6205
6206 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6207 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6208 }
6209
6210 tw32(RCVBDI_STD_THRESH, val);
6211
6212 /* Initialize TG3_BDINFO's at:
6213 * RCVDBDI_STD_BD: standard eth size rx ring
6214 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6215 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6216 *
6217 * like so:
6218 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6219 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6220 * ring attribute flags
6221 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6222 *
6223 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6224 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6225 *
6226 * The size of each ring is fixed in the firmware, but the location is
6227 * configurable.
6228 */
6229 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6230 ((u64) tp->rx_std_mapping >> 32));
6231 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6232 ((u64) tp->rx_std_mapping & 0xffffffff));
6233 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6234 NIC_SRAM_RX_BUFFER_DESC);
6235
6236 /* Don't even try to program the JUMBO/MINI buffer descriptor
6237 * configs on 5705.
6238 */
6239 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6240 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6241 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6242 } else {
6243 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6244 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6245
6246 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6247 BDINFO_FLAGS_DISABLED);
6248
6249 /* Setup replenish threshold. */
6250 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6251
6252 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6253 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6254 ((u64) tp->rx_jumbo_mapping >> 32));
6255 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6256 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6257 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6258 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6259 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6260 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6261 } else {
6262 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6263 BDINFO_FLAGS_DISABLED);
6264 }
6265
6266 }
6267
6268 /* There is only one send ring on 5705/5750, no need to explicitly
6269 * disable the others.
6270 */
6271 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6272 /* Clear out send RCB ring in SRAM. */
6273 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6274 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6275 BDINFO_FLAGS_DISABLED);
6276 }
6277
6278 tp->tx_prod = 0;
6279 tp->tx_cons = 0;
6280 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6281 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6282
6283 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6284 tp->tx_desc_mapping,
6285 (TG3_TX_RING_SIZE <<
6286 BDINFO_FLAGS_MAXLEN_SHIFT),
6287 NIC_SRAM_TX_BUFFER_DESC);
6288
6289 /* There is only one receive return ring on 5705/5750, no need
6290 * to explicitly disable the others.
6291 */
6292 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6293 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6294 i += TG3_BDINFO_SIZE) {
6295 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6296 BDINFO_FLAGS_DISABLED);
6297 }
6298 }
6299
6300 tp->rx_rcb_ptr = 0;
6301 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6302
6303 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6304 tp->rx_rcb_mapping,
6305 (TG3_RX_RCB_RING_SIZE(tp) <<
6306 BDINFO_FLAGS_MAXLEN_SHIFT),
6307 0);
6308
6309 tp->rx_std_ptr = tp->rx_pending;
6310 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6311 tp->rx_std_ptr);
6312
6313 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6314 tp->rx_jumbo_pending : 0;
6315 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6316 tp->rx_jumbo_ptr);
6317
6318 /* Initialize MAC address and backoff seed. */
6319 __tg3_set_mac_addr(tp, 0);
6320
6321 /* MTU + ethernet header + FCS + optional VLAN tag */
6322 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6323
6324 /* The slot time is changed by tg3_setup_phy if we
6325 * run at gigabit with half duplex.
6326 */
6327 tw32(MAC_TX_LENGTHS,
6328 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6329 (6 << TX_LENGTHS_IPG_SHIFT) |
6330 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6331
6332 /* Receive rules. */
6333 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6334 tw32(RCVLPC_CONFIG, 0x0181);
6335
6336 /* Calculate RDMAC_MODE setting early, we need it to determine
6337 * the RCVLPC_STATE_ENABLE mask.
6338 */
6339 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6340 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6341 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6342 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6343 RDMAC_MODE_LNGREAD_ENAB);
6344
6345 /* If statement applies to 5705 and 5750 PCI devices only */
6346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6347 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6348 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6349 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6350 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6351 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6352 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6353 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6354 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6355 }
6356 }
6357
6358 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6359 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6360
6361 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6362 rdmac_mode |= (1 << 27);
6363
6364 /* Receive/send statistics. */
6365 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6366 val = tr32(RCVLPC_STATS_ENABLE);
6367 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6368 tw32(RCVLPC_STATS_ENABLE, val);
6369 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6370 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6371 val = tr32(RCVLPC_STATS_ENABLE);
6372 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6373 tw32(RCVLPC_STATS_ENABLE, val);
6374 } else {
6375 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6376 }
6377 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6378 tw32(SNDDATAI_STATSENAB, 0xffffff);
6379 tw32(SNDDATAI_STATSCTRL,
6380 (SNDDATAI_SCTRL_ENABLE |
6381 SNDDATAI_SCTRL_FASTUPD));
6382
6383 /* Setup host coalescing engine. */
6384 tw32(HOSTCC_MODE, 0);
6385 for (i = 0; i < 2000; i++) {
6386 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6387 break;
6388 udelay(10);
6389 }
6390
6391 __tg3_set_coalesce(tp, &tp->coal);
6392
6393 /* set status block DMA address */
6394 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6395 ((u64) tp->status_mapping >> 32));
6396 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6397 ((u64) tp->status_mapping & 0xffffffff));
6398
6399 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6400 /* Status/statistics block address. See tg3_timer,
6401 * the tg3_periodic_fetch_stats call there, and
6402 * tg3_get_stats to see how this works for 5705/5750 chips.
6403 */
6404 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6405 ((u64) tp->stats_mapping >> 32));
6406 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6407 ((u64) tp->stats_mapping & 0xffffffff));
6408 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6409 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6410 }
6411
6412 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6413
6414 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6415 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6416 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6417 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6418
6419 /* Clear statistics/status block in chip, and status block in ram. */
6420 for (i = NIC_SRAM_STATS_BLK;
6421 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6422 i += sizeof(u32)) {
6423 tg3_write_mem(tp, i, 0);
6424 udelay(40);
6425 }
6426 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6427
6428 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6429 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6430 /* reset to prevent losing 1st rx packet intermittently */
6431 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6432 udelay(10);
6433 }
6434
6435 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6436 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6437 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6438 udelay(40);
6439
6440 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6441 * If TG3_FLG2_IS_NIC is zero, we should read the
6442 * register to preserve the GPIO settings for LOMs. The GPIOs,
6443 * whether used as inputs or outputs, are set by boot code after
6444 * reset.
6445 */
6446 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6447 u32 gpio_mask;
6448
6449 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6450 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6451 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6452
6453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6454 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6455 GRC_LCLCTRL_GPIO_OUTPUT3;
6456
6457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6458 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6459
6460 tp->grc_local_ctrl &= ~gpio_mask;
6461 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6462
6463 /* GPIO1 must be driven high for eeprom write protect */
6464 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6465 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6466 GRC_LCLCTRL_GPIO_OUTPUT1);
6467 }
6468 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6469 udelay(100);
6470
6471 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6472 tp->last_tag = 0;
6473
6474 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6475 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6476 udelay(40);
6477 }
6478
6479 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6480 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6481 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6482 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6483 WDMAC_MODE_LNGREAD_ENAB);
6484
6485 /* If statement applies to 5705 and 5750 PCI devices only */
6486 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6487 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6488 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6489 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6490 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6491 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6492 /* nothing */
6493 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6494 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6495 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6496 val |= WDMAC_MODE_RX_ACCEL;
6497 }
6498 }
6499
6500 /* Enable host coalescing bug fix */
6501 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6502 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6503 val |= (1 << 29);
6504
6505 tw32_f(WDMAC_MODE, val);
6506 udelay(40);
6507
6508 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6509 val = tr32(TG3PCI_X_CAPS);
6510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6511 val &= ~PCIX_CAPS_BURST_MASK;
6512 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6513 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6514 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6515 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6516 }
6517 tw32(TG3PCI_X_CAPS, val);
6518 }
6519
6520 tw32_f(RDMAC_MODE, rdmac_mode);
6521 udelay(40);
6522
6523 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6524 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6525 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6526 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6527 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6528 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6529 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6530 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6531 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6532 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6533 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6534 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6535
6536 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6537 err = tg3_load_5701_a0_firmware_fix(tp);
6538 if (err)
6539 return err;
6540 }
6541
6542 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6543 err = tg3_load_tso_firmware(tp);
6544 if (err)
6545 return err;
6546 }
6547
6548 tp->tx_mode = TX_MODE_ENABLE;
6549 tw32_f(MAC_TX_MODE, tp->tx_mode);
6550 udelay(100);
6551
6552 tp->rx_mode = RX_MODE_ENABLE;
6553 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6554 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6555
6556 tw32_f(MAC_RX_MODE, tp->rx_mode);
6557 udelay(10);
6558
6559 if (tp->link_config.phy_is_low_power) {
6560 tp->link_config.phy_is_low_power = 0;
6561 tp->link_config.speed = tp->link_config.orig_speed;
6562 tp->link_config.duplex = tp->link_config.orig_duplex;
6563 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6564 }
6565
6566 tp->mi_mode = MAC_MI_MODE_BASE;
6567 tw32_f(MAC_MI_MODE, tp->mi_mode);
6568 udelay(80);
6569
6570 tw32(MAC_LED_CTRL, tp->led_ctrl);
6571
6572 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6573 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6574 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6575 udelay(10);
6576 }
6577 tw32_f(MAC_RX_MODE, tp->rx_mode);
6578 udelay(10);
6579
6580 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6581 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6582 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6583 /* Set drive transmission level to 1.2V */
6584 /* only if the signal pre-emphasis bit is not set */
6585 val = tr32(MAC_SERDES_CFG);
6586 val &= 0xfffff000;
6587 val |= 0x880;
6588 tw32(MAC_SERDES_CFG, val);
6589 }
6590 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6591 tw32(MAC_SERDES_CFG, 0x616000);
6592 }
6593
6594 /* Prevent chip from dropping frames when flow control
6595 * is enabled.
6596 */
6597 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6598
6599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6600 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6601 /* Use hardware link auto-negotiation */
6602 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6603 }
6604
6605 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6606 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6607 u32 tmp;
6608
6609 tmp = tr32(SERDES_RX_CTRL);
6610 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6611 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6612 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6613 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6614 }
6615
6616 err = tg3_setup_phy(tp, 0);
6617 if (err)
6618 return err;
6619
6620 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6621 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6622 u32 tmp;
6623
6624 /* Clear CRC stats. */
6625 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6626 tg3_writephy(tp, MII_TG3_TEST1,
6627 tmp | MII_TG3_TEST1_CRC_EN);
6628 tg3_readphy(tp, 0x14, &tmp);
6629 }
6630 }
6631
6632 __tg3_set_rx_mode(tp->dev);
6633
6634 /* Initialize receive rules. */
6635 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6636 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6637 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6638 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6639
6640 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6641 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6642 limit = 8;
6643 else
6644 limit = 16;
6645 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6646 limit -= 4;
6647 switch (limit) {
6648 case 16:
6649 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6650 case 15:
6651 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6652 case 14:
6653 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6654 case 13:
6655 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6656 case 12:
6657 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6658 case 11:
6659 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6660 case 10:
6661 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6662 case 9:
6663 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6664 case 8:
6665 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6666 case 7:
6667 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6668 case 6:
6669 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6670 case 5:
6671 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6672 case 4:
6673 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6674 case 3:
6675 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6676 case 2:
6677 case 1:
6678
6679 default:
6680 break;
6681 };
6682
6683 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6684
6685 return 0;
6686 }
6687
6688 /* Called at device open time to get the chip ready for
6689 * packet processing. Invoked with tp->lock held.
6690 */
6691 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6692 {
6693 int err;
6694
6695 /* Force the chip into D0. */
6696 err = tg3_set_power_state(tp, PCI_D0);
6697 if (err)
6698 goto out;
6699
6700 tg3_switch_clocks(tp);
6701
6702 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6703
6704 err = tg3_reset_hw(tp, reset_phy);
6705
6706 out:
6707 return err;
6708 }
6709
6710 #define TG3_STAT_ADD32(PSTAT, REG) \
6711 do { u32 __val = tr32(REG); \
6712 (PSTAT)->low += __val; \
6713 if ((PSTAT)->low < __val) \
6714 (PSTAT)->high += 1; \
6715 } while (0)
6716
6717 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6718 {
6719 struct tg3_hw_stats *sp = tp->hw_stats;
6720
6721 if (!netif_carrier_ok(tp->dev))
6722 return;
6723
6724 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6725 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6726 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6727 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6728 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6729 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6730 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6731 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6732 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6733 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6734 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6735 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6736 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6737
6738 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6739 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6740 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6741 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6742 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6743 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6744 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6745 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6746 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6747 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6748 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6749 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6750 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6751 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6752
6753 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6754 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6755 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6756 }
6757
6758 static void tg3_timer(unsigned long __opaque)
6759 {
6760 struct tg3 *tp = (struct tg3 *) __opaque;
6761
6762 if (tp->irq_sync)
6763 goto restart_timer;
6764
6765 spin_lock(&tp->lock);
6766
6767 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6768 /* All of this garbage is because when using non-tagged
6769 * IRQ status the mailbox/status_block protocol the chip
6770 * uses with the cpu is race prone.
6771 */
6772 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6773 tw32(GRC_LOCAL_CTRL,
6774 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6775 } else {
6776 tw32(HOSTCC_MODE, tp->coalesce_mode |
6777 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6778 }
6779
6780 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6781 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6782 spin_unlock(&tp->lock);
6783 schedule_work(&tp->reset_task);
6784 return;
6785 }
6786 }
6787
6788 /* This part only runs once per second. */
6789 if (!--tp->timer_counter) {
6790 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6791 tg3_periodic_fetch_stats(tp);
6792
6793 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6794 u32 mac_stat;
6795 int phy_event;
6796
6797 mac_stat = tr32(MAC_STATUS);
6798
6799 phy_event = 0;
6800 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6801 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6802 phy_event = 1;
6803 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6804 phy_event = 1;
6805
6806 if (phy_event)
6807 tg3_setup_phy(tp, 0);
6808 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6809 u32 mac_stat = tr32(MAC_STATUS);
6810 int need_setup = 0;
6811
6812 if (netif_carrier_ok(tp->dev) &&
6813 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6814 need_setup = 1;
6815 }
6816 if (! netif_carrier_ok(tp->dev) &&
6817 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6818 MAC_STATUS_SIGNAL_DET))) {
6819 need_setup = 1;
6820 }
6821 if (need_setup) {
6822 if (!tp->serdes_counter) {
6823 tw32_f(MAC_MODE,
6824 (tp->mac_mode &
6825 ~MAC_MODE_PORT_MODE_MASK));
6826 udelay(40);
6827 tw32_f(MAC_MODE, tp->mac_mode);
6828 udelay(40);
6829 }
6830 tg3_setup_phy(tp, 0);
6831 }
6832 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6833 tg3_serdes_parallel_detect(tp);
6834
6835 tp->timer_counter = tp->timer_multiplier;
6836 }
6837
6838 /* Heartbeat is only sent once every 2 seconds.
6839 *
6840 * The heartbeat is to tell the ASF firmware that the host
6841 * driver is still alive. In the event that the OS crashes,
6842 * ASF needs to reset the hardware to free up the FIFO space
6843 * that may be filled with rx packets destined for the host.
6844 * If the FIFO is full, ASF will no longer function properly.
6845 *
6846 * Unintended resets have been reported on real time kernels
6847 * where the timer doesn't run on time. Netpoll will also have
6848 * same problem.
6849 *
6850 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6851 * to check the ring condition when the heartbeat is expiring
6852 * before doing the reset. This will prevent most unintended
6853 * resets.
6854 */
6855 if (!--tp->asf_counter) {
6856 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6857 u32 val;
6858
6859 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6860 FWCMD_NICDRV_ALIVE3);
6861 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6862 /* 5 seconds timeout */
6863 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6864 val = tr32(GRC_RX_CPU_EVENT);
6865 val |= (1 << 14);
6866 tw32(GRC_RX_CPU_EVENT, val);
6867 }
6868 tp->asf_counter = tp->asf_multiplier;
6869 }
6870
6871 spin_unlock(&tp->lock);
6872
6873 restart_timer:
6874 tp->timer.expires = jiffies + tp->timer_offset;
6875 add_timer(&tp->timer);
6876 }
6877
6878 static int tg3_request_irq(struct tg3 *tp)
6879 {
6880 irq_handler_t fn;
6881 unsigned long flags;
6882 struct net_device *dev = tp->dev;
6883
6884 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6885 fn = tg3_msi;
6886 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6887 fn = tg3_msi_1shot;
6888 flags = IRQF_SAMPLE_RANDOM;
6889 } else {
6890 fn = tg3_interrupt;
6891 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6892 fn = tg3_interrupt_tagged;
6893 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6894 }
6895 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6896 }
6897
6898 static int tg3_test_interrupt(struct tg3 *tp)
6899 {
6900 struct net_device *dev = tp->dev;
6901 int err, i, intr_ok = 0;
6902
6903 if (!netif_running(dev))
6904 return -ENODEV;
6905
6906 tg3_disable_ints(tp);
6907
6908 free_irq(tp->pdev->irq, dev);
6909
6910 err = request_irq(tp->pdev->irq, tg3_test_isr,
6911 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6912 if (err)
6913 return err;
6914
6915 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6916 tg3_enable_ints(tp);
6917
6918 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6919 HOSTCC_MODE_NOW);
6920
6921 for (i = 0; i < 5; i++) {
6922 u32 int_mbox, misc_host_ctrl;
6923
6924 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6925 TG3_64BIT_REG_LOW);
6926 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6927
6928 if ((int_mbox != 0) ||
6929 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6930 intr_ok = 1;
6931 break;
6932 }
6933
6934 msleep(10);
6935 }
6936
6937 tg3_disable_ints(tp);
6938
6939 free_irq(tp->pdev->irq, dev);
6940
6941 err = tg3_request_irq(tp);
6942
6943 if (err)
6944 return err;
6945
6946 if (intr_ok)
6947 return 0;
6948
6949 return -EIO;
6950 }
6951
6952 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6953 * successfully restored
6954 */
6955 static int tg3_test_msi(struct tg3 *tp)
6956 {
6957 struct net_device *dev = tp->dev;
6958 int err;
6959 u16 pci_cmd;
6960
6961 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6962 return 0;
6963
6964 /* Turn off SERR reporting in case MSI terminates with Master
6965 * Abort.
6966 */
6967 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6968 pci_write_config_word(tp->pdev, PCI_COMMAND,
6969 pci_cmd & ~PCI_COMMAND_SERR);
6970
6971 err = tg3_test_interrupt(tp);
6972
6973 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6974
6975 if (!err)
6976 return 0;
6977
6978 /* other failures */
6979 if (err != -EIO)
6980 return err;
6981
6982 /* MSI test failed, go back to INTx mode */
6983 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6984 "switching to INTx mode. Please report this failure to "
6985 "the PCI maintainer and include system chipset information.\n",
6986 tp->dev->name);
6987
6988 free_irq(tp->pdev->irq, dev);
6989 pci_disable_msi(tp->pdev);
6990
6991 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6992
6993 err = tg3_request_irq(tp);
6994 if (err)
6995 return err;
6996
6997 /* Need to reset the chip because the MSI cycle may have terminated
6998 * with Master Abort.
6999 */
7000 tg3_full_lock(tp, 1);
7001
7002 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7003 err = tg3_init_hw(tp, 1);
7004
7005 tg3_full_unlock(tp);
7006
7007 if (err)
7008 free_irq(tp->pdev->irq, dev);
7009
7010 return err;
7011 }
7012
7013 static int tg3_open(struct net_device *dev)
7014 {
7015 struct tg3 *tp = netdev_priv(dev);
7016 int err;
7017
7018 netif_carrier_off(tp->dev);
7019
7020 tg3_full_lock(tp, 0);
7021
7022 err = tg3_set_power_state(tp, PCI_D0);
7023 if (err) {
7024 tg3_full_unlock(tp);
7025 return err;
7026 }
7027
7028 tg3_disable_ints(tp);
7029 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7030
7031 tg3_full_unlock(tp);
7032
7033 /* The placement of this call is tied
7034 * to the setup and use of Host TX descriptors.
7035 */
7036 err = tg3_alloc_consistent(tp);
7037 if (err)
7038 return err;
7039
7040 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7041 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7042 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7043 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7044 (tp->pdev_peer == tp->pdev))) {
7045 /* All MSI supporting chips should support tagged
7046 * status. Assert that this is the case.
7047 */
7048 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7049 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7050 "Not using MSI.\n", tp->dev->name);
7051 } else if (pci_enable_msi(tp->pdev) == 0) {
7052 u32 msi_mode;
7053
7054 msi_mode = tr32(MSGINT_MODE);
7055 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7056 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7057 }
7058 }
7059 err = tg3_request_irq(tp);
7060
7061 if (err) {
7062 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7063 pci_disable_msi(tp->pdev);
7064 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7065 }
7066 tg3_free_consistent(tp);
7067 return err;
7068 }
7069
7070 tg3_full_lock(tp, 0);
7071
7072 err = tg3_init_hw(tp, 1);
7073 if (err) {
7074 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7075 tg3_free_rings(tp);
7076 } else {
7077 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7078 tp->timer_offset = HZ;
7079 else
7080 tp->timer_offset = HZ / 10;
7081
7082 BUG_ON(tp->timer_offset > HZ);
7083 tp->timer_counter = tp->timer_multiplier =
7084 (HZ / tp->timer_offset);
7085 tp->asf_counter = tp->asf_multiplier =
7086 ((HZ / tp->timer_offset) * 2);
7087
7088 init_timer(&tp->timer);
7089 tp->timer.expires = jiffies + tp->timer_offset;
7090 tp->timer.data = (unsigned long) tp;
7091 tp->timer.function = tg3_timer;
7092 }
7093
7094 tg3_full_unlock(tp);
7095
7096 if (err) {
7097 free_irq(tp->pdev->irq, dev);
7098 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7099 pci_disable_msi(tp->pdev);
7100 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7101 }
7102 tg3_free_consistent(tp);
7103 return err;
7104 }
7105
7106 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7107 err = tg3_test_msi(tp);
7108
7109 if (err) {
7110 tg3_full_lock(tp, 0);
7111
7112 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7113 pci_disable_msi(tp->pdev);
7114 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7115 }
7116 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7117 tg3_free_rings(tp);
7118 tg3_free_consistent(tp);
7119
7120 tg3_full_unlock(tp);
7121
7122 return err;
7123 }
7124
7125 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7126 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7127 u32 val = tr32(PCIE_TRANSACTION_CFG);
7128
7129 tw32(PCIE_TRANSACTION_CFG,
7130 val | PCIE_TRANS_CFG_1SHOT_MSI);
7131 }
7132 }
7133 }
7134
7135 tg3_full_lock(tp, 0);
7136
7137 add_timer(&tp->timer);
7138 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7139 tg3_enable_ints(tp);
7140
7141 tg3_full_unlock(tp);
7142
7143 netif_start_queue(dev);
7144
7145 return 0;
7146 }
7147
7148 #if 0
7149 /*static*/ void tg3_dump_state(struct tg3 *tp)
7150 {
7151 u32 val32, val32_2, val32_3, val32_4, val32_5;
7152 u16 val16;
7153 int i;
7154
7155 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7156 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7157 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7158 val16, val32);
7159
7160 /* MAC block */
7161 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7162 tr32(MAC_MODE), tr32(MAC_STATUS));
7163 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7164 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7165 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7166 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7167 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7168 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7169
7170 /* Send data initiator control block */
7171 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7172 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7173 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7174 tr32(SNDDATAI_STATSCTRL));
7175
7176 /* Send data completion control block */
7177 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7178
7179 /* Send BD ring selector block */
7180 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7181 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7182
7183 /* Send BD initiator control block */
7184 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7185 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7186
7187 /* Send BD completion control block */
7188 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7189
7190 /* Receive list placement control block */
7191 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7192 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7193 printk(" RCVLPC_STATSCTRL[%08x]\n",
7194 tr32(RCVLPC_STATSCTRL));
7195
7196 /* Receive data and receive BD initiator control block */
7197 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7198 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7199
7200 /* Receive data completion control block */
7201 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7202 tr32(RCVDCC_MODE));
7203
7204 /* Receive BD initiator control block */
7205 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7206 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7207
7208 /* Receive BD completion control block */
7209 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7210 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7211
7212 /* Receive list selector control block */
7213 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7214 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7215
7216 /* Mbuf cluster free block */
7217 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7218 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7219
7220 /* Host coalescing control block */
7221 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7222 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7223 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7224 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7225 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7226 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7227 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7228 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7229 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7230 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7231 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7232 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7233
7234 /* Memory arbiter control block */
7235 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7236 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7237
7238 /* Buffer manager control block */
7239 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7240 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7241 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7242 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7243 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7244 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7245 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7246 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7247
7248 /* Read DMA control block */
7249 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7250 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7251
7252 /* Write DMA control block */
7253 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7254 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7255
7256 /* DMA completion block */
7257 printk("DEBUG: DMAC_MODE[%08x]\n",
7258 tr32(DMAC_MODE));
7259
7260 /* GRC block */
7261 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7262 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7263 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7264 tr32(GRC_LOCAL_CTRL));
7265
7266 /* TG3_BDINFOs */
7267 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7268 tr32(RCVDBDI_JUMBO_BD + 0x0),
7269 tr32(RCVDBDI_JUMBO_BD + 0x4),
7270 tr32(RCVDBDI_JUMBO_BD + 0x8),
7271 tr32(RCVDBDI_JUMBO_BD + 0xc));
7272 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7273 tr32(RCVDBDI_STD_BD + 0x0),
7274 tr32(RCVDBDI_STD_BD + 0x4),
7275 tr32(RCVDBDI_STD_BD + 0x8),
7276 tr32(RCVDBDI_STD_BD + 0xc));
7277 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7278 tr32(RCVDBDI_MINI_BD + 0x0),
7279 tr32(RCVDBDI_MINI_BD + 0x4),
7280 tr32(RCVDBDI_MINI_BD + 0x8),
7281 tr32(RCVDBDI_MINI_BD + 0xc));
7282
7283 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7284 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7285 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7286 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7287 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7288 val32, val32_2, val32_3, val32_4);
7289
7290 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7291 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7292 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7293 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7294 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7295 val32, val32_2, val32_3, val32_4);
7296
7297 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7298 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7299 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7300 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7301 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7302 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7303 val32, val32_2, val32_3, val32_4, val32_5);
7304
7305 /* SW status block */
7306 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7307 tp->hw_status->status,
7308 tp->hw_status->status_tag,
7309 tp->hw_status->rx_jumbo_consumer,
7310 tp->hw_status->rx_consumer,
7311 tp->hw_status->rx_mini_consumer,
7312 tp->hw_status->idx[0].rx_producer,
7313 tp->hw_status->idx[0].tx_consumer);
7314
7315 /* SW statistics block */
7316 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7317 ((u32 *)tp->hw_stats)[0],
7318 ((u32 *)tp->hw_stats)[1],
7319 ((u32 *)tp->hw_stats)[2],
7320 ((u32 *)tp->hw_stats)[3]);
7321
7322 /* Mailboxes */
7323 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7324 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7325 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7326 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7327 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7328
7329 /* NIC side send descriptors. */
7330 for (i = 0; i < 6; i++) {
7331 unsigned long txd;
7332
7333 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7334 + (i * sizeof(struct tg3_tx_buffer_desc));
7335 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7336 i,
7337 readl(txd + 0x0), readl(txd + 0x4),
7338 readl(txd + 0x8), readl(txd + 0xc));
7339 }
7340
7341 /* NIC side RX descriptors. */
7342 for (i = 0; i < 6; i++) {
7343 unsigned long rxd;
7344
7345 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7346 + (i * sizeof(struct tg3_rx_buffer_desc));
7347 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7348 i,
7349 readl(rxd + 0x0), readl(rxd + 0x4),
7350 readl(rxd + 0x8), readl(rxd + 0xc));
7351 rxd += (4 * sizeof(u32));
7352 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7353 i,
7354 readl(rxd + 0x0), readl(rxd + 0x4),
7355 readl(rxd + 0x8), readl(rxd + 0xc));
7356 }
7357
7358 for (i = 0; i < 6; i++) {
7359 unsigned long rxd;
7360
7361 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7362 + (i * sizeof(struct tg3_rx_buffer_desc));
7363 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7364 i,
7365 readl(rxd + 0x0), readl(rxd + 0x4),
7366 readl(rxd + 0x8), readl(rxd + 0xc));
7367 rxd += (4 * sizeof(u32));
7368 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7369 i,
7370 readl(rxd + 0x0), readl(rxd + 0x4),
7371 readl(rxd + 0x8), readl(rxd + 0xc));
7372 }
7373 }
7374 #endif
7375
7376 static struct net_device_stats *tg3_get_stats(struct net_device *);
7377 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7378
7379 static int tg3_close(struct net_device *dev)
7380 {
7381 struct tg3 *tp = netdev_priv(dev);
7382
7383 /* Calling flush_scheduled_work() may deadlock because
7384 * linkwatch_event() may be on the workqueue and it will try to get
7385 * the rtnl_lock which we are holding.
7386 */
7387 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7388 msleep(1);
7389
7390 netif_stop_queue(dev);
7391
7392 del_timer_sync(&tp->timer);
7393
7394 tg3_full_lock(tp, 1);
7395 #if 0
7396 tg3_dump_state(tp);
7397 #endif
7398
7399 tg3_disable_ints(tp);
7400
7401 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7402 tg3_free_rings(tp);
7403 tp->tg3_flags &=
7404 ~(TG3_FLAG_INIT_COMPLETE |
7405 TG3_FLAG_GOT_SERDES_FLOWCTL);
7406
7407 tg3_full_unlock(tp);
7408
7409 free_irq(tp->pdev->irq, dev);
7410 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7411 pci_disable_msi(tp->pdev);
7412 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7413 }
7414
7415 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7416 sizeof(tp->net_stats_prev));
7417 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7418 sizeof(tp->estats_prev));
7419
7420 tg3_free_consistent(tp);
7421
7422 tg3_set_power_state(tp, PCI_D3hot);
7423
7424 netif_carrier_off(tp->dev);
7425
7426 return 0;
7427 }
7428
7429 static inline unsigned long get_stat64(tg3_stat64_t *val)
7430 {
7431 unsigned long ret;
7432
7433 #if (BITS_PER_LONG == 32)
7434 ret = val->low;
7435 #else
7436 ret = ((u64)val->high << 32) | ((u64)val->low);
7437 #endif
7438 return ret;
7439 }
7440
7441 static unsigned long calc_crc_errors(struct tg3 *tp)
7442 {
7443 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7444
7445 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7446 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7447 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7448 u32 val;
7449
7450 spin_lock_bh(&tp->lock);
7451 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7452 tg3_writephy(tp, MII_TG3_TEST1,
7453 val | MII_TG3_TEST1_CRC_EN);
7454 tg3_readphy(tp, 0x14, &val);
7455 } else
7456 val = 0;
7457 spin_unlock_bh(&tp->lock);
7458
7459 tp->phy_crc_errors += val;
7460
7461 return tp->phy_crc_errors;
7462 }
7463
7464 return get_stat64(&hw_stats->rx_fcs_errors);
7465 }
7466
7467 #define ESTAT_ADD(member) \
7468 estats->member = old_estats->member + \
7469 get_stat64(&hw_stats->member)
7470
7471 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7472 {
7473 struct tg3_ethtool_stats *estats = &tp->estats;
7474 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7475 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7476
7477 if (!hw_stats)
7478 return old_estats;
7479
7480 ESTAT_ADD(rx_octets);
7481 ESTAT_ADD(rx_fragments);
7482 ESTAT_ADD(rx_ucast_packets);
7483 ESTAT_ADD(rx_mcast_packets);
7484 ESTAT_ADD(rx_bcast_packets);
7485 ESTAT_ADD(rx_fcs_errors);
7486 ESTAT_ADD(rx_align_errors);
7487 ESTAT_ADD(rx_xon_pause_rcvd);
7488 ESTAT_ADD(rx_xoff_pause_rcvd);
7489 ESTAT_ADD(rx_mac_ctrl_rcvd);
7490 ESTAT_ADD(rx_xoff_entered);
7491 ESTAT_ADD(rx_frame_too_long_errors);
7492 ESTAT_ADD(rx_jabbers);
7493 ESTAT_ADD(rx_undersize_packets);
7494 ESTAT_ADD(rx_in_length_errors);
7495 ESTAT_ADD(rx_out_length_errors);
7496 ESTAT_ADD(rx_64_or_less_octet_packets);
7497 ESTAT_ADD(rx_65_to_127_octet_packets);
7498 ESTAT_ADD(rx_128_to_255_octet_packets);
7499 ESTAT_ADD(rx_256_to_511_octet_packets);
7500 ESTAT_ADD(rx_512_to_1023_octet_packets);
7501 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7502 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7503 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7504 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7505 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7506
7507 ESTAT_ADD(tx_octets);
7508 ESTAT_ADD(tx_collisions);
7509 ESTAT_ADD(tx_xon_sent);
7510 ESTAT_ADD(tx_xoff_sent);
7511 ESTAT_ADD(tx_flow_control);
7512 ESTAT_ADD(tx_mac_errors);
7513 ESTAT_ADD(tx_single_collisions);
7514 ESTAT_ADD(tx_mult_collisions);
7515 ESTAT_ADD(tx_deferred);
7516 ESTAT_ADD(tx_excessive_collisions);
7517 ESTAT_ADD(tx_late_collisions);
7518 ESTAT_ADD(tx_collide_2times);
7519 ESTAT_ADD(tx_collide_3times);
7520 ESTAT_ADD(tx_collide_4times);
7521 ESTAT_ADD(tx_collide_5times);
7522 ESTAT_ADD(tx_collide_6times);
7523 ESTAT_ADD(tx_collide_7times);
7524 ESTAT_ADD(tx_collide_8times);
7525 ESTAT_ADD(tx_collide_9times);
7526 ESTAT_ADD(tx_collide_10times);
7527 ESTAT_ADD(tx_collide_11times);
7528 ESTAT_ADD(tx_collide_12times);
7529 ESTAT_ADD(tx_collide_13times);
7530 ESTAT_ADD(tx_collide_14times);
7531 ESTAT_ADD(tx_collide_15times);
7532 ESTAT_ADD(tx_ucast_packets);
7533 ESTAT_ADD(tx_mcast_packets);
7534 ESTAT_ADD(tx_bcast_packets);
7535 ESTAT_ADD(tx_carrier_sense_errors);
7536 ESTAT_ADD(tx_discards);
7537 ESTAT_ADD(tx_errors);
7538
7539 ESTAT_ADD(dma_writeq_full);
7540 ESTAT_ADD(dma_write_prioq_full);
7541 ESTAT_ADD(rxbds_empty);
7542 ESTAT_ADD(rx_discards);
7543 ESTAT_ADD(rx_errors);
7544 ESTAT_ADD(rx_threshold_hit);
7545
7546 ESTAT_ADD(dma_readq_full);
7547 ESTAT_ADD(dma_read_prioq_full);
7548 ESTAT_ADD(tx_comp_queue_full);
7549
7550 ESTAT_ADD(ring_set_send_prod_index);
7551 ESTAT_ADD(ring_status_update);
7552 ESTAT_ADD(nic_irqs);
7553 ESTAT_ADD(nic_avoided_irqs);
7554 ESTAT_ADD(nic_tx_threshold_hit);
7555
7556 return estats;
7557 }
7558
7559 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7560 {
7561 struct tg3 *tp = netdev_priv(dev);
7562 struct net_device_stats *stats = &tp->net_stats;
7563 struct net_device_stats *old_stats = &tp->net_stats_prev;
7564 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7565
7566 if (!hw_stats)
7567 return old_stats;
7568
7569 stats->rx_packets = old_stats->rx_packets +
7570 get_stat64(&hw_stats->rx_ucast_packets) +
7571 get_stat64(&hw_stats->rx_mcast_packets) +
7572 get_stat64(&hw_stats->rx_bcast_packets);
7573
7574 stats->tx_packets = old_stats->tx_packets +
7575 get_stat64(&hw_stats->tx_ucast_packets) +
7576 get_stat64(&hw_stats->tx_mcast_packets) +
7577 get_stat64(&hw_stats->tx_bcast_packets);
7578
7579 stats->rx_bytes = old_stats->rx_bytes +
7580 get_stat64(&hw_stats->rx_octets);
7581 stats->tx_bytes = old_stats->tx_bytes +
7582 get_stat64(&hw_stats->tx_octets);
7583
7584 stats->rx_errors = old_stats->rx_errors +
7585 get_stat64(&hw_stats->rx_errors);
7586 stats->tx_errors = old_stats->tx_errors +
7587 get_stat64(&hw_stats->tx_errors) +
7588 get_stat64(&hw_stats->tx_mac_errors) +
7589 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7590 get_stat64(&hw_stats->tx_discards);
7591
7592 stats->multicast = old_stats->multicast +
7593 get_stat64(&hw_stats->rx_mcast_packets);
7594 stats->collisions = old_stats->collisions +
7595 get_stat64(&hw_stats->tx_collisions);
7596
7597 stats->rx_length_errors = old_stats->rx_length_errors +
7598 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7599 get_stat64(&hw_stats->rx_undersize_packets);
7600
7601 stats->rx_over_errors = old_stats->rx_over_errors +
7602 get_stat64(&hw_stats->rxbds_empty);
7603 stats->rx_frame_errors = old_stats->rx_frame_errors +
7604 get_stat64(&hw_stats->rx_align_errors);
7605 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7606 get_stat64(&hw_stats->tx_discards);
7607 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7608 get_stat64(&hw_stats->tx_carrier_sense_errors);
7609
7610 stats->rx_crc_errors = old_stats->rx_crc_errors +
7611 calc_crc_errors(tp);
7612
7613 stats->rx_missed_errors = old_stats->rx_missed_errors +
7614 get_stat64(&hw_stats->rx_discards);
7615
7616 return stats;
7617 }
7618
7619 static inline u32 calc_crc(unsigned char *buf, int len)
7620 {
7621 u32 reg;
7622 u32 tmp;
7623 int j, k;
7624
7625 reg = 0xffffffff;
7626
7627 for (j = 0; j < len; j++) {
7628 reg ^= buf[j];
7629
7630 for (k = 0; k < 8; k++) {
7631 tmp = reg & 0x01;
7632
7633 reg >>= 1;
7634
7635 if (tmp) {
7636 reg ^= 0xedb88320;
7637 }
7638 }
7639 }
7640
7641 return ~reg;
7642 }
7643
7644 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7645 {
7646 /* accept or reject all multicast frames */
7647 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7648 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7649 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7650 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7651 }
7652
7653 static void __tg3_set_rx_mode(struct net_device *dev)
7654 {
7655 struct tg3 *tp = netdev_priv(dev);
7656 u32 rx_mode;
7657
7658 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7659 RX_MODE_KEEP_VLAN_TAG);
7660
7661 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7662 * flag clear.
7663 */
7664 #if TG3_VLAN_TAG_USED
7665 if (!tp->vlgrp &&
7666 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7667 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7668 #else
7669 /* By definition, VLAN is disabled always in this
7670 * case.
7671 */
7672 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7673 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7674 #endif
7675
7676 if (dev->flags & IFF_PROMISC) {
7677 /* Promiscuous mode. */
7678 rx_mode |= RX_MODE_PROMISC;
7679 } else if (dev->flags & IFF_ALLMULTI) {
7680 /* Accept all multicast. */
7681 tg3_set_multi (tp, 1);
7682 } else if (dev->mc_count < 1) {
7683 /* Reject all multicast. */
7684 tg3_set_multi (tp, 0);
7685 } else {
7686 /* Accept one or more multicast(s). */
7687 struct dev_mc_list *mclist;
7688 unsigned int i;
7689 u32 mc_filter[4] = { 0, };
7690 u32 regidx;
7691 u32 bit;
7692 u32 crc;
7693
7694 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7695 i++, mclist = mclist->next) {
7696
7697 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7698 bit = ~crc & 0x7f;
7699 regidx = (bit & 0x60) >> 5;
7700 bit &= 0x1f;
7701 mc_filter[regidx] |= (1 << bit);
7702 }
7703
7704 tw32(MAC_HASH_REG_0, mc_filter[0]);
7705 tw32(MAC_HASH_REG_1, mc_filter[1]);
7706 tw32(MAC_HASH_REG_2, mc_filter[2]);
7707 tw32(MAC_HASH_REG_3, mc_filter[3]);
7708 }
7709
7710 if (rx_mode != tp->rx_mode) {
7711 tp->rx_mode = rx_mode;
7712 tw32_f(MAC_RX_MODE, rx_mode);
7713 udelay(10);
7714 }
7715 }
7716
7717 static void tg3_set_rx_mode(struct net_device *dev)
7718 {
7719 struct tg3 *tp = netdev_priv(dev);
7720
7721 if (!netif_running(dev))
7722 return;
7723
7724 tg3_full_lock(tp, 0);
7725 __tg3_set_rx_mode(dev);
7726 tg3_full_unlock(tp);
7727 }
7728
7729 #define TG3_REGDUMP_LEN (32 * 1024)
7730
7731 static int tg3_get_regs_len(struct net_device *dev)
7732 {
7733 return TG3_REGDUMP_LEN;
7734 }
7735
7736 static void tg3_get_regs(struct net_device *dev,
7737 struct ethtool_regs *regs, void *_p)
7738 {
7739 u32 *p = _p;
7740 struct tg3 *tp = netdev_priv(dev);
7741 u8 *orig_p = _p;
7742 int i;
7743
7744 regs->version = 0;
7745
7746 memset(p, 0, TG3_REGDUMP_LEN);
7747
7748 if (tp->link_config.phy_is_low_power)
7749 return;
7750
7751 tg3_full_lock(tp, 0);
7752
7753 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7754 #define GET_REG32_LOOP(base,len) \
7755 do { p = (u32 *)(orig_p + (base)); \
7756 for (i = 0; i < len; i += 4) \
7757 __GET_REG32((base) + i); \
7758 } while (0)
7759 #define GET_REG32_1(reg) \
7760 do { p = (u32 *)(orig_p + (reg)); \
7761 __GET_REG32((reg)); \
7762 } while (0)
7763
7764 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7765 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7766 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7767 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7768 GET_REG32_1(SNDDATAC_MODE);
7769 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7770 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7771 GET_REG32_1(SNDBDC_MODE);
7772 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7773 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7774 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7775 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7776 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7777 GET_REG32_1(RCVDCC_MODE);
7778 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7779 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7780 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7781 GET_REG32_1(MBFREE_MODE);
7782 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7783 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7784 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7785 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7786 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7787 GET_REG32_1(RX_CPU_MODE);
7788 GET_REG32_1(RX_CPU_STATE);
7789 GET_REG32_1(RX_CPU_PGMCTR);
7790 GET_REG32_1(RX_CPU_HWBKPT);
7791 GET_REG32_1(TX_CPU_MODE);
7792 GET_REG32_1(TX_CPU_STATE);
7793 GET_REG32_1(TX_CPU_PGMCTR);
7794 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7795 GET_REG32_LOOP(FTQ_RESET, 0x120);
7796 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7797 GET_REG32_1(DMAC_MODE);
7798 GET_REG32_LOOP(GRC_MODE, 0x4c);
7799 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7800 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7801
7802 #undef __GET_REG32
7803 #undef GET_REG32_LOOP
7804 #undef GET_REG32_1
7805
7806 tg3_full_unlock(tp);
7807 }
7808
7809 static int tg3_get_eeprom_len(struct net_device *dev)
7810 {
7811 struct tg3 *tp = netdev_priv(dev);
7812
7813 return tp->nvram_size;
7814 }
7815
7816 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7817 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7818
7819 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7820 {
7821 struct tg3 *tp = netdev_priv(dev);
7822 int ret;
7823 u8 *pd;
7824 u32 i, offset, len, val, b_offset, b_count;
7825
7826 if (tp->link_config.phy_is_low_power)
7827 return -EAGAIN;
7828
7829 offset = eeprom->offset;
7830 len = eeprom->len;
7831 eeprom->len = 0;
7832
7833 eeprom->magic = TG3_EEPROM_MAGIC;
7834
7835 if (offset & 3) {
7836 /* adjustments to start on required 4 byte boundary */
7837 b_offset = offset & 3;
7838 b_count = 4 - b_offset;
7839 if (b_count > len) {
7840 /* i.e. offset=1 len=2 */
7841 b_count = len;
7842 }
7843 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7844 if (ret)
7845 return ret;
7846 val = cpu_to_le32(val);
7847 memcpy(data, ((char*)&val) + b_offset, b_count);
7848 len -= b_count;
7849 offset += b_count;
7850 eeprom->len += b_count;
7851 }
7852
7853 /* read bytes upto the last 4 byte boundary */
7854 pd = &data[eeprom->len];
7855 for (i = 0; i < (len - (len & 3)); i += 4) {
7856 ret = tg3_nvram_read(tp, offset + i, &val);
7857 if (ret) {
7858 eeprom->len += i;
7859 return ret;
7860 }
7861 val = cpu_to_le32(val);
7862 memcpy(pd + i, &val, 4);
7863 }
7864 eeprom->len += i;
7865
7866 if (len & 3) {
7867 /* read last bytes not ending on 4 byte boundary */
7868 pd = &data[eeprom->len];
7869 b_count = len & 3;
7870 b_offset = offset + len - b_count;
7871 ret = tg3_nvram_read(tp, b_offset, &val);
7872 if (ret)
7873 return ret;
7874 val = cpu_to_le32(val);
7875 memcpy(pd, ((char*)&val), b_count);
7876 eeprom->len += b_count;
7877 }
7878 return 0;
7879 }
7880
7881 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7882
7883 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7884 {
7885 struct tg3 *tp = netdev_priv(dev);
7886 int ret;
7887 u32 offset, len, b_offset, odd_len, start, end;
7888 u8 *buf;
7889
7890 if (tp->link_config.phy_is_low_power)
7891 return -EAGAIN;
7892
7893 if (eeprom->magic != TG3_EEPROM_MAGIC)
7894 return -EINVAL;
7895
7896 offset = eeprom->offset;
7897 len = eeprom->len;
7898
7899 if ((b_offset = (offset & 3))) {
7900 /* adjustments to start on required 4 byte boundary */
7901 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7902 if (ret)
7903 return ret;
7904 start = cpu_to_le32(start);
7905 len += b_offset;
7906 offset &= ~3;
7907 if (len < 4)
7908 len = 4;
7909 }
7910
7911 odd_len = 0;
7912 if (len & 3) {
7913 /* adjustments to end on required 4 byte boundary */
7914 odd_len = 1;
7915 len = (len + 3) & ~3;
7916 ret = tg3_nvram_read(tp, offset+len-4, &end);
7917 if (ret)
7918 return ret;
7919 end = cpu_to_le32(end);
7920 }
7921
7922 buf = data;
7923 if (b_offset || odd_len) {
7924 buf = kmalloc(len, GFP_KERNEL);
7925 if (buf == 0)
7926 return -ENOMEM;
7927 if (b_offset)
7928 memcpy(buf, &start, 4);
7929 if (odd_len)
7930 memcpy(buf+len-4, &end, 4);
7931 memcpy(buf + b_offset, data, eeprom->len);
7932 }
7933
7934 ret = tg3_nvram_write_block(tp, offset, len, buf);
7935
7936 if (buf != data)
7937 kfree(buf);
7938
7939 return ret;
7940 }
7941
7942 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7943 {
7944 struct tg3 *tp = netdev_priv(dev);
7945
7946 cmd->supported = (SUPPORTED_Autoneg);
7947
7948 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7949 cmd->supported |= (SUPPORTED_1000baseT_Half |
7950 SUPPORTED_1000baseT_Full);
7951
7952 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7953 cmd->supported |= (SUPPORTED_100baseT_Half |
7954 SUPPORTED_100baseT_Full |
7955 SUPPORTED_10baseT_Half |
7956 SUPPORTED_10baseT_Full |
7957 SUPPORTED_MII);
7958 cmd->port = PORT_TP;
7959 } else {
7960 cmd->supported |= SUPPORTED_FIBRE;
7961 cmd->port = PORT_FIBRE;
7962 }
7963
7964 cmd->advertising = tp->link_config.advertising;
7965 if (netif_running(dev)) {
7966 cmd->speed = tp->link_config.active_speed;
7967 cmd->duplex = tp->link_config.active_duplex;
7968 }
7969 cmd->phy_address = PHY_ADDR;
7970 cmd->transceiver = 0;
7971 cmd->autoneg = tp->link_config.autoneg;
7972 cmd->maxtxpkt = 0;
7973 cmd->maxrxpkt = 0;
7974 return 0;
7975 }
7976
7977 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7978 {
7979 struct tg3 *tp = netdev_priv(dev);
7980
7981 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7982 /* These are the only valid advertisement bits allowed. */
7983 if (cmd->autoneg == AUTONEG_ENABLE &&
7984 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7985 ADVERTISED_1000baseT_Full |
7986 ADVERTISED_Autoneg |
7987 ADVERTISED_FIBRE)))
7988 return -EINVAL;
7989 /* Fiber can only do SPEED_1000. */
7990 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7991 (cmd->speed != SPEED_1000))
7992 return -EINVAL;
7993 /* Copper cannot force SPEED_1000. */
7994 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7995 (cmd->speed == SPEED_1000))
7996 return -EINVAL;
7997 else if ((cmd->speed == SPEED_1000) &&
7998 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7999 return -EINVAL;
8000
8001 tg3_full_lock(tp, 0);
8002
8003 tp->link_config.autoneg = cmd->autoneg;
8004 if (cmd->autoneg == AUTONEG_ENABLE) {
8005 tp->link_config.advertising = cmd->advertising;
8006 tp->link_config.speed = SPEED_INVALID;
8007 tp->link_config.duplex = DUPLEX_INVALID;
8008 } else {
8009 tp->link_config.advertising = 0;
8010 tp->link_config.speed = cmd->speed;
8011 tp->link_config.duplex = cmd->duplex;
8012 }
8013
8014 tp->link_config.orig_speed = tp->link_config.speed;
8015 tp->link_config.orig_duplex = tp->link_config.duplex;
8016 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8017
8018 if (netif_running(dev))
8019 tg3_setup_phy(tp, 1);
8020
8021 tg3_full_unlock(tp);
8022
8023 return 0;
8024 }
8025
8026 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8027 {
8028 struct tg3 *tp = netdev_priv(dev);
8029
8030 strcpy(info->driver, DRV_MODULE_NAME);
8031 strcpy(info->version, DRV_MODULE_VERSION);
8032 strcpy(info->fw_version, tp->fw_ver);
8033 strcpy(info->bus_info, pci_name(tp->pdev));
8034 }
8035
8036 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8037 {
8038 struct tg3 *tp = netdev_priv(dev);
8039
8040 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8041 wol->supported = WAKE_MAGIC;
8042 else
8043 wol->supported = 0;
8044 wol->wolopts = 0;
8045 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8046 wol->wolopts = WAKE_MAGIC;
8047 memset(&wol->sopass, 0, sizeof(wol->sopass));
8048 }
8049
8050 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8051 {
8052 struct tg3 *tp = netdev_priv(dev);
8053
8054 if (wol->wolopts & ~WAKE_MAGIC)
8055 return -EINVAL;
8056 if ((wol->wolopts & WAKE_MAGIC) &&
8057 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8058 return -EINVAL;
8059
8060 spin_lock_bh(&tp->lock);
8061 if (wol->wolopts & WAKE_MAGIC)
8062 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8063 else
8064 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8065 spin_unlock_bh(&tp->lock);
8066
8067 return 0;
8068 }
8069
8070 static u32 tg3_get_msglevel(struct net_device *dev)
8071 {
8072 struct tg3 *tp = netdev_priv(dev);
8073 return tp->msg_enable;
8074 }
8075
8076 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8077 {
8078 struct tg3 *tp = netdev_priv(dev);
8079 tp->msg_enable = value;
8080 }
8081
8082 static int tg3_set_tso(struct net_device *dev, u32 value)
8083 {
8084 struct tg3 *tp = netdev_priv(dev);
8085
8086 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8087 if (value)
8088 return -EINVAL;
8089 return 0;
8090 }
8091 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8092 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8093 if (value)
8094 dev->features |= NETIF_F_TSO6;
8095 else
8096 dev->features &= ~NETIF_F_TSO6;
8097 }
8098 return ethtool_op_set_tso(dev, value);
8099 }
8100
8101 static int tg3_nway_reset(struct net_device *dev)
8102 {
8103 struct tg3 *tp = netdev_priv(dev);
8104 u32 bmcr;
8105 int r;
8106
8107 if (!netif_running(dev))
8108 return -EAGAIN;
8109
8110 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8111 return -EINVAL;
8112
8113 spin_lock_bh(&tp->lock);
8114 r = -EINVAL;
8115 tg3_readphy(tp, MII_BMCR, &bmcr);
8116 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8117 ((bmcr & BMCR_ANENABLE) ||
8118 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8119 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8120 BMCR_ANENABLE);
8121 r = 0;
8122 }
8123 spin_unlock_bh(&tp->lock);
8124
8125 return r;
8126 }
8127
8128 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8129 {
8130 struct tg3 *tp = netdev_priv(dev);
8131
8132 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8133 ering->rx_mini_max_pending = 0;
8134 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8135 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8136 else
8137 ering->rx_jumbo_max_pending = 0;
8138
8139 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8140
8141 ering->rx_pending = tp->rx_pending;
8142 ering->rx_mini_pending = 0;
8143 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8144 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8145 else
8146 ering->rx_jumbo_pending = 0;
8147
8148 ering->tx_pending = tp->tx_pending;
8149 }
8150
8151 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8152 {
8153 struct tg3 *tp = netdev_priv(dev);
8154 int irq_sync = 0, err = 0;
8155
8156 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8157 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8158 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8159 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8160 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8161 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8162 return -EINVAL;
8163
8164 if (netif_running(dev)) {
8165 tg3_netif_stop(tp);
8166 irq_sync = 1;
8167 }
8168
8169 tg3_full_lock(tp, irq_sync);
8170
8171 tp->rx_pending = ering->rx_pending;
8172
8173 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8174 tp->rx_pending > 63)
8175 tp->rx_pending = 63;
8176 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8177 tp->tx_pending = ering->tx_pending;
8178
8179 if (netif_running(dev)) {
8180 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8181 err = tg3_restart_hw(tp, 1);
8182 if (!err)
8183 tg3_netif_start(tp);
8184 }
8185
8186 tg3_full_unlock(tp);
8187
8188 return err;
8189 }
8190
8191 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8192 {
8193 struct tg3 *tp = netdev_priv(dev);
8194
8195 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8196 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8197 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8198 }
8199
8200 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8201 {
8202 struct tg3 *tp = netdev_priv(dev);
8203 int irq_sync = 0, err = 0;
8204
8205 if (netif_running(dev)) {
8206 tg3_netif_stop(tp);
8207 irq_sync = 1;
8208 }
8209
8210 tg3_full_lock(tp, irq_sync);
8211
8212 if (epause->autoneg)
8213 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8214 else
8215 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8216 if (epause->rx_pause)
8217 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8218 else
8219 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8220 if (epause->tx_pause)
8221 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8222 else
8223 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8224
8225 if (netif_running(dev)) {
8226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8227 err = tg3_restart_hw(tp, 1);
8228 if (!err)
8229 tg3_netif_start(tp);
8230 }
8231
8232 tg3_full_unlock(tp);
8233
8234 return err;
8235 }
8236
8237 static u32 tg3_get_rx_csum(struct net_device *dev)
8238 {
8239 struct tg3 *tp = netdev_priv(dev);
8240 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8241 }
8242
8243 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8244 {
8245 struct tg3 *tp = netdev_priv(dev);
8246
8247 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8248 if (data != 0)
8249 return -EINVAL;
8250 return 0;
8251 }
8252
8253 spin_lock_bh(&tp->lock);
8254 if (data)
8255 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8256 else
8257 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8258 spin_unlock_bh(&tp->lock);
8259
8260 return 0;
8261 }
8262
8263 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8264 {
8265 struct tg3 *tp = netdev_priv(dev);
8266
8267 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8268 if (data != 0)
8269 return -EINVAL;
8270 return 0;
8271 }
8272
8273 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8274 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8275 ethtool_op_set_tx_hw_csum(dev, data);
8276 else
8277 ethtool_op_set_tx_csum(dev, data);
8278
8279 return 0;
8280 }
8281
8282 static int tg3_get_stats_count (struct net_device *dev)
8283 {
8284 return TG3_NUM_STATS;
8285 }
8286
8287 static int tg3_get_test_count (struct net_device *dev)
8288 {
8289 return TG3_NUM_TEST;
8290 }
8291
8292 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8293 {
8294 switch (stringset) {
8295 case ETH_SS_STATS:
8296 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8297 break;
8298 case ETH_SS_TEST:
8299 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8300 break;
8301 default:
8302 WARN_ON(1); /* we need a WARN() */
8303 break;
8304 }
8305 }
8306
8307 static int tg3_phys_id(struct net_device *dev, u32 data)
8308 {
8309 struct tg3 *tp = netdev_priv(dev);
8310 int i;
8311
8312 if (!netif_running(tp->dev))
8313 return -EAGAIN;
8314
8315 if (data == 0)
8316 data = 2;
8317
8318 for (i = 0; i < (data * 2); i++) {
8319 if ((i % 2) == 0)
8320 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8321 LED_CTRL_1000MBPS_ON |
8322 LED_CTRL_100MBPS_ON |
8323 LED_CTRL_10MBPS_ON |
8324 LED_CTRL_TRAFFIC_OVERRIDE |
8325 LED_CTRL_TRAFFIC_BLINK |
8326 LED_CTRL_TRAFFIC_LED);
8327
8328 else
8329 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8330 LED_CTRL_TRAFFIC_OVERRIDE);
8331
8332 if (msleep_interruptible(500))
8333 break;
8334 }
8335 tw32(MAC_LED_CTRL, tp->led_ctrl);
8336 return 0;
8337 }
8338
8339 static void tg3_get_ethtool_stats (struct net_device *dev,
8340 struct ethtool_stats *estats, u64 *tmp_stats)
8341 {
8342 struct tg3 *tp = netdev_priv(dev);
8343 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8344 }
8345
8346 #define NVRAM_TEST_SIZE 0x100
8347 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8348 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8349 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8350
8351 static int tg3_test_nvram(struct tg3 *tp)
8352 {
8353 u32 *buf, csum, magic;
8354 int i, j, err = 0, size;
8355
8356 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8357 return -EIO;
8358
8359 if (magic == TG3_EEPROM_MAGIC)
8360 size = NVRAM_TEST_SIZE;
8361 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8362 if ((magic & 0xe00000) == 0x200000)
8363 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8364 else
8365 return 0;
8366 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8367 size = NVRAM_SELFBOOT_HW_SIZE;
8368 else
8369 return -EIO;
8370
8371 buf = kmalloc(size, GFP_KERNEL);
8372 if (buf == NULL)
8373 return -ENOMEM;
8374
8375 err = -EIO;
8376 for (i = 0, j = 0; i < size; i += 4, j++) {
8377 u32 val;
8378
8379 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8380 break;
8381 buf[j] = cpu_to_le32(val);
8382 }
8383 if (i < size)
8384 goto out;
8385
8386 /* Selfboot format */
8387 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8388 TG3_EEPROM_MAGIC_FW) {
8389 u8 *buf8 = (u8 *) buf, csum8 = 0;
8390
8391 for (i = 0; i < size; i++)
8392 csum8 += buf8[i];
8393
8394 if (csum8 == 0) {
8395 err = 0;
8396 goto out;
8397 }
8398
8399 err = -EIO;
8400 goto out;
8401 }
8402
8403 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8404 TG3_EEPROM_MAGIC_HW) {
8405 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8406 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8407 u8 *buf8 = (u8 *) buf;
8408 int j, k;
8409
8410 /* Separate the parity bits and the data bytes. */
8411 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8412 if ((i == 0) || (i == 8)) {
8413 int l;
8414 u8 msk;
8415
8416 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8417 parity[k++] = buf8[i] & msk;
8418 i++;
8419 }
8420 else if (i == 16) {
8421 int l;
8422 u8 msk;
8423
8424 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8425 parity[k++] = buf8[i] & msk;
8426 i++;
8427
8428 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8429 parity[k++] = buf8[i] & msk;
8430 i++;
8431 }
8432 data[j++] = buf8[i];
8433 }
8434
8435 err = -EIO;
8436 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8437 u8 hw8 = hweight8(data[i]);
8438
8439 if ((hw8 & 0x1) && parity[i])
8440 goto out;
8441 else if (!(hw8 & 0x1) && !parity[i])
8442 goto out;
8443 }
8444 err = 0;
8445 goto out;
8446 }
8447
8448 /* Bootstrap checksum at offset 0x10 */
8449 csum = calc_crc((unsigned char *) buf, 0x10);
8450 if(csum != cpu_to_le32(buf[0x10/4]))
8451 goto out;
8452
8453 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8454 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8455 if (csum != cpu_to_le32(buf[0xfc/4]))
8456 goto out;
8457
8458 err = 0;
8459
8460 out:
8461 kfree(buf);
8462 return err;
8463 }
8464
8465 #define TG3_SERDES_TIMEOUT_SEC 2
8466 #define TG3_COPPER_TIMEOUT_SEC 6
8467
8468 static int tg3_test_link(struct tg3 *tp)
8469 {
8470 int i, max;
8471
8472 if (!netif_running(tp->dev))
8473 return -ENODEV;
8474
8475 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8476 max = TG3_SERDES_TIMEOUT_SEC;
8477 else
8478 max = TG3_COPPER_TIMEOUT_SEC;
8479
8480 for (i = 0; i < max; i++) {
8481 if (netif_carrier_ok(tp->dev))
8482 return 0;
8483
8484 if (msleep_interruptible(1000))
8485 break;
8486 }
8487
8488 return -EIO;
8489 }
8490
8491 /* Only test the commonly used registers */
8492 static int tg3_test_registers(struct tg3 *tp)
8493 {
8494 int i, is_5705, is_5750;
8495 u32 offset, read_mask, write_mask, val, save_val, read_val;
8496 static struct {
8497 u16 offset;
8498 u16 flags;
8499 #define TG3_FL_5705 0x1
8500 #define TG3_FL_NOT_5705 0x2
8501 #define TG3_FL_NOT_5788 0x4
8502 #define TG3_FL_NOT_5750 0x8
8503 u32 read_mask;
8504 u32 write_mask;
8505 } reg_tbl[] = {
8506 /* MAC Control Registers */
8507 { MAC_MODE, TG3_FL_NOT_5705,
8508 0x00000000, 0x00ef6f8c },
8509 { MAC_MODE, TG3_FL_5705,
8510 0x00000000, 0x01ef6b8c },
8511 { MAC_STATUS, TG3_FL_NOT_5705,
8512 0x03800107, 0x00000000 },
8513 { MAC_STATUS, TG3_FL_5705,
8514 0x03800100, 0x00000000 },
8515 { MAC_ADDR_0_HIGH, 0x0000,
8516 0x00000000, 0x0000ffff },
8517 { MAC_ADDR_0_LOW, 0x0000,
8518 0x00000000, 0xffffffff },
8519 { MAC_RX_MTU_SIZE, 0x0000,
8520 0x00000000, 0x0000ffff },
8521 { MAC_TX_MODE, 0x0000,
8522 0x00000000, 0x00000070 },
8523 { MAC_TX_LENGTHS, 0x0000,
8524 0x00000000, 0x00003fff },
8525 { MAC_RX_MODE, TG3_FL_NOT_5705,
8526 0x00000000, 0x000007fc },
8527 { MAC_RX_MODE, TG3_FL_5705,
8528 0x00000000, 0x000007dc },
8529 { MAC_HASH_REG_0, 0x0000,
8530 0x00000000, 0xffffffff },
8531 { MAC_HASH_REG_1, 0x0000,
8532 0x00000000, 0xffffffff },
8533 { MAC_HASH_REG_2, 0x0000,
8534 0x00000000, 0xffffffff },
8535 { MAC_HASH_REG_3, 0x0000,
8536 0x00000000, 0xffffffff },
8537
8538 /* Receive Data and Receive BD Initiator Control Registers. */
8539 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8540 0x00000000, 0xffffffff },
8541 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8542 0x00000000, 0xffffffff },
8543 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8544 0x00000000, 0x00000003 },
8545 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8546 0x00000000, 0xffffffff },
8547 { RCVDBDI_STD_BD+0, 0x0000,
8548 0x00000000, 0xffffffff },
8549 { RCVDBDI_STD_BD+4, 0x0000,
8550 0x00000000, 0xffffffff },
8551 { RCVDBDI_STD_BD+8, 0x0000,
8552 0x00000000, 0xffff0002 },
8553 { RCVDBDI_STD_BD+0xc, 0x0000,
8554 0x00000000, 0xffffffff },
8555
8556 /* Receive BD Initiator Control Registers. */
8557 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8558 0x00000000, 0xffffffff },
8559 { RCVBDI_STD_THRESH, TG3_FL_5705,
8560 0x00000000, 0x000003ff },
8561 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8562 0x00000000, 0xffffffff },
8563
8564 /* Host Coalescing Control Registers. */
8565 { HOSTCC_MODE, TG3_FL_NOT_5705,
8566 0x00000000, 0x00000004 },
8567 { HOSTCC_MODE, TG3_FL_5705,
8568 0x00000000, 0x000000f6 },
8569 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8570 0x00000000, 0xffffffff },
8571 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8572 0x00000000, 0x000003ff },
8573 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8574 0x00000000, 0xffffffff },
8575 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8576 0x00000000, 0x000003ff },
8577 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8578 0x00000000, 0xffffffff },
8579 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8580 0x00000000, 0x000000ff },
8581 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8582 0x00000000, 0xffffffff },
8583 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8584 0x00000000, 0x000000ff },
8585 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8586 0x00000000, 0xffffffff },
8587 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8588 0x00000000, 0xffffffff },
8589 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8590 0x00000000, 0xffffffff },
8591 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8592 0x00000000, 0x000000ff },
8593 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8594 0x00000000, 0xffffffff },
8595 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8596 0x00000000, 0x000000ff },
8597 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8598 0x00000000, 0xffffffff },
8599 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8600 0x00000000, 0xffffffff },
8601 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8602 0x00000000, 0xffffffff },
8603 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8604 0x00000000, 0xffffffff },
8605 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8606 0x00000000, 0xffffffff },
8607 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8608 0xffffffff, 0x00000000 },
8609 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8610 0xffffffff, 0x00000000 },
8611
8612 /* Buffer Manager Control Registers. */
8613 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8614 0x00000000, 0x007fff80 },
8615 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8616 0x00000000, 0x007fffff },
8617 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8618 0x00000000, 0x0000003f },
8619 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8620 0x00000000, 0x000001ff },
8621 { BUFMGR_MB_HIGH_WATER, 0x0000,
8622 0x00000000, 0x000001ff },
8623 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8624 0xffffffff, 0x00000000 },
8625 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8626 0xffffffff, 0x00000000 },
8627
8628 /* Mailbox Registers */
8629 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8630 0x00000000, 0x000001ff },
8631 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8632 0x00000000, 0x000001ff },
8633 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8634 0x00000000, 0x000007ff },
8635 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8636 0x00000000, 0x000001ff },
8637
8638 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8639 };
8640
8641 is_5705 = is_5750 = 0;
8642 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8643 is_5705 = 1;
8644 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8645 is_5750 = 1;
8646 }
8647
8648 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8649 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8650 continue;
8651
8652 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8653 continue;
8654
8655 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8656 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8657 continue;
8658
8659 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8660 continue;
8661
8662 offset = (u32) reg_tbl[i].offset;
8663 read_mask = reg_tbl[i].read_mask;
8664 write_mask = reg_tbl[i].write_mask;
8665
8666 /* Save the original register content */
8667 save_val = tr32(offset);
8668
8669 /* Determine the read-only value. */
8670 read_val = save_val & read_mask;
8671
8672 /* Write zero to the register, then make sure the read-only bits
8673 * are not changed and the read/write bits are all zeros.
8674 */
8675 tw32(offset, 0);
8676
8677 val = tr32(offset);
8678
8679 /* Test the read-only and read/write bits. */
8680 if (((val & read_mask) != read_val) || (val & write_mask))
8681 goto out;
8682
8683 /* Write ones to all the bits defined by RdMask and WrMask, then
8684 * make sure the read-only bits are not changed and the
8685 * read/write bits are all ones.
8686 */
8687 tw32(offset, read_mask | write_mask);
8688
8689 val = tr32(offset);
8690
8691 /* Test the read-only bits. */
8692 if ((val & read_mask) != read_val)
8693 goto out;
8694
8695 /* Test the read/write bits. */
8696 if ((val & write_mask) != write_mask)
8697 goto out;
8698
8699 tw32(offset, save_val);
8700 }
8701
8702 return 0;
8703
8704 out:
8705 if (netif_msg_hw(tp))
8706 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8707 offset);
8708 tw32(offset, save_val);
8709 return -EIO;
8710 }
8711
8712 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8713 {
8714 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8715 int i;
8716 u32 j;
8717
8718 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8719 for (j = 0; j < len; j += 4) {
8720 u32 val;
8721
8722 tg3_write_mem(tp, offset + j, test_pattern[i]);
8723 tg3_read_mem(tp, offset + j, &val);
8724 if (val != test_pattern[i])
8725 return -EIO;
8726 }
8727 }
8728 return 0;
8729 }
8730
8731 static int tg3_test_memory(struct tg3 *tp)
8732 {
8733 static struct mem_entry {
8734 u32 offset;
8735 u32 len;
8736 } mem_tbl_570x[] = {
8737 { 0x00000000, 0x00b50},
8738 { 0x00002000, 0x1c000},
8739 { 0xffffffff, 0x00000}
8740 }, mem_tbl_5705[] = {
8741 { 0x00000100, 0x0000c},
8742 { 0x00000200, 0x00008},
8743 { 0x00004000, 0x00800},
8744 { 0x00006000, 0x01000},
8745 { 0x00008000, 0x02000},
8746 { 0x00010000, 0x0e000},
8747 { 0xffffffff, 0x00000}
8748 }, mem_tbl_5755[] = {
8749 { 0x00000200, 0x00008},
8750 { 0x00004000, 0x00800},
8751 { 0x00006000, 0x00800},
8752 { 0x00008000, 0x02000},
8753 { 0x00010000, 0x0c000},
8754 { 0xffffffff, 0x00000}
8755 }, mem_tbl_5906[] = {
8756 { 0x00000200, 0x00008},
8757 { 0x00004000, 0x00400},
8758 { 0x00006000, 0x00400},
8759 { 0x00008000, 0x01000},
8760 { 0x00010000, 0x01000},
8761 { 0xffffffff, 0x00000}
8762 };
8763 struct mem_entry *mem_tbl;
8764 int err = 0;
8765 int i;
8766
8767 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8768 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8770 mem_tbl = mem_tbl_5755;
8771 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8772 mem_tbl = mem_tbl_5906;
8773 else
8774 mem_tbl = mem_tbl_5705;
8775 } else
8776 mem_tbl = mem_tbl_570x;
8777
8778 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8779 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8780 mem_tbl[i].len)) != 0)
8781 break;
8782 }
8783
8784 return err;
8785 }
8786
8787 #define TG3_MAC_LOOPBACK 0
8788 #define TG3_PHY_LOOPBACK 1
8789
8790 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8791 {
8792 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8793 u32 desc_idx;
8794 struct sk_buff *skb, *rx_skb;
8795 u8 *tx_data;
8796 dma_addr_t map;
8797 int num_pkts, tx_len, rx_len, i, err;
8798 struct tg3_rx_buffer_desc *desc;
8799
8800 if (loopback_mode == TG3_MAC_LOOPBACK) {
8801 /* HW errata - mac loopback fails in some cases on 5780.
8802 * Normal traffic and PHY loopback are not affected by
8803 * errata.
8804 */
8805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8806 return 0;
8807
8808 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8809 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8810 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8811 mac_mode |= MAC_MODE_PORT_MODE_MII;
8812 else
8813 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8814 tw32(MAC_MODE, mac_mode);
8815 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8816 u32 val;
8817
8818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8819 u32 phytest;
8820
8821 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8822 u32 phy;
8823
8824 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8825 phytest | MII_TG3_EPHY_SHADOW_EN);
8826 if (!tg3_readphy(tp, 0x1b, &phy))
8827 tg3_writephy(tp, 0x1b, phy & ~0x20);
8828 if (!tg3_readphy(tp, 0x10, &phy))
8829 tg3_writephy(tp, 0x10, phy & ~0x4000);
8830 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8831 }
8832 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8833 } else
8834 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8835
8836 tg3_writephy(tp, MII_BMCR, val);
8837 udelay(40);
8838
8839 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8840 MAC_MODE_LINK_POLARITY;
8841 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8842 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8843 mac_mode |= MAC_MODE_PORT_MODE_MII;
8844 } else
8845 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8846
8847 /* reset to prevent losing 1st rx packet intermittently */
8848 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8849 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8850 udelay(10);
8851 tw32_f(MAC_RX_MODE, tp->rx_mode);
8852 }
8853 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8854 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8857 }
8858 tw32(MAC_MODE, mac_mode);
8859 }
8860 else
8861 return -EINVAL;
8862
8863 err = -EIO;
8864
8865 tx_len = 1514;
8866 skb = netdev_alloc_skb(tp->dev, tx_len);
8867 if (!skb)
8868 return -ENOMEM;
8869
8870 tx_data = skb_put(skb, tx_len);
8871 memcpy(tx_data, tp->dev->dev_addr, 6);
8872 memset(tx_data + 6, 0x0, 8);
8873
8874 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8875
8876 for (i = 14; i < tx_len; i++)
8877 tx_data[i] = (u8) (i & 0xff);
8878
8879 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8880
8881 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8882 HOSTCC_MODE_NOW);
8883
8884 udelay(10);
8885
8886 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8887
8888 num_pkts = 0;
8889
8890 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8891
8892 tp->tx_prod++;
8893 num_pkts++;
8894
8895 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8896 tp->tx_prod);
8897 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8898
8899 udelay(10);
8900
8901 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8902 for (i = 0; i < 25; i++) {
8903 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8904 HOSTCC_MODE_NOW);
8905
8906 udelay(10);
8907
8908 tx_idx = tp->hw_status->idx[0].tx_consumer;
8909 rx_idx = tp->hw_status->idx[0].rx_producer;
8910 if ((tx_idx == tp->tx_prod) &&
8911 (rx_idx == (rx_start_idx + num_pkts)))
8912 break;
8913 }
8914
8915 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8916 dev_kfree_skb(skb);
8917
8918 if (tx_idx != tp->tx_prod)
8919 goto out;
8920
8921 if (rx_idx != rx_start_idx + num_pkts)
8922 goto out;
8923
8924 desc = &tp->rx_rcb[rx_start_idx];
8925 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8926 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8927 if (opaque_key != RXD_OPAQUE_RING_STD)
8928 goto out;
8929
8930 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8931 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8932 goto out;
8933
8934 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8935 if (rx_len != tx_len)
8936 goto out;
8937
8938 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8939
8940 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8941 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8942
8943 for (i = 14; i < tx_len; i++) {
8944 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8945 goto out;
8946 }
8947 err = 0;
8948
8949 /* tg3_free_rings will unmap and free the rx_skb */
8950 out:
8951 return err;
8952 }
8953
8954 #define TG3_MAC_LOOPBACK_FAILED 1
8955 #define TG3_PHY_LOOPBACK_FAILED 2
8956 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8957 TG3_PHY_LOOPBACK_FAILED)
8958
8959 static int tg3_test_loopback(struct tg3 *tp)
8960 {
8961 int err = 0;
8962
8963 if (!netif_running(tp->dev))
8964 return TG3_LOOPBACK_FAILED;
8965
8966 err = tg3_reset_hw(tp, 1);
8967 if (err)
8968 return TG3_LOOPBACK_FAILED;
8969
8970 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8971 err |= TG3_MAC_LOOPBACK_FAILED;
8972 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8973 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8974 err |= TG3_PHY_LOOPBACK_FAILED;
8975 }
8976
8977 return err;
8978 }
8979
8980 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8981 u64 *data)
8982 {
8983 struct tg3 *tp = netdev_priv(dev);
8984
8985 if (tp->link_config.phy_is_low_power)
8986 tg3_set_power_state(tp, PCI_D0);
8987
8988 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8989
8990 if (tg3_test_nvram(tp) != 0) {
8991 etest->flags |= ETH_TEST_FL_FAILED;
8992 data[0] = 1;
8993 }
8994 if (tg3_test_link(tp) != 0) {
8995 etest->flags |= ETH_TEST_FL_FAILED;
8996 data[1] = 1;
8997 }
8998 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8999 int err, irq_sync = 0;
9000
9001 if (netif_running(dev)) {
9002 tg3_netif_stop(tp);
9003 irq_sync = 1;
9004 }
9005
9006 tg3_full_lock(tp, irq_sync);
9007
9008 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9009 err = tg3_nvram_lock(tp);
9010 tg3_halt_cpu(tp, RX_CPU_BASE);
9011 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9012 tg3_halt_cpu(tp, TX_CPU_BASE);
9013 if (!err)
9014 tg3_nvram_unlock(tp);
9015
9016 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9017 tg3_phy_reset(tp);
9018
9019 if (tg3_test_registers(tp) != 0) {
9020 etest->flags |= ETH_TEST_FL_FAILED;
9021 data[2] = 1;
9022 }
9023 if (tg3_test_memory(tp) != 0) {
9024 etest->flags |= ETH_TEST_FL_FAILED;
9025 data[3] = 1;
9026 }
9027 if ((data[4] = tg3_test_loopback(tp)) != 0)
9028 etest->flags |= ETH_TEST_FL_FAILED;
9029
9030 tg3_full_unlock(tp);
9031
9032 if (tg3_test_interrupt(tp) != 0) {
9033 etest->flags |= ETH_TEST_FL_FAILED;
9034 data[5] = 1;
9035 }
9036
9037 tg3_full_lock(tp, 0);
9038
9039 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9040 if (netif_running(dev)) {
9041 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9042 if (!tg3_restart_hw(tp, 1))
9043 tg3_netif_start(tp);
9044 }
9045
9046 tg3_full_unlock(tp);
9047 }
9048 if (tp->link_config.phy_is_low_power)
9049 tg3_set_power_state(tp, PCI_D3hot);
9050
9051 }
9052
9053 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9054 {
9055 struct mii_ioctl_data *data = if_mii(ifr);
9056 struct tg3 *tp = netdev_priv(dev);
9057 int err;
9058
9059 switch(cmd) {
9060 case SIOCGMIIPHY:
9061 data->phy_id = PHY_ADDR;
9062
9063 /* fallthru */
9064 case SIOCGMIIREG: {
9065 u32 mii_regval;
9066
9067 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9068 break; /* We have no PHY */
9069
9070 if (tp->link_config.phy_is_low_power)
9071 return -EAGAIN;
9072
9073 spin_lock_bh(&tp->lock);
9074 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9075 spin_unlock_bh(&tp->lock);
9076
9077 data->val_out = mii_regval;
9078
9079 return err;
9080 }
9081
9082 case SIOCSMIIREG:
9083 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9084 break; /* We have no PHY */
9085
9086 if (!capable(CAP_NET_ADMIN))
9087 return -EPERM;
9088
9089 if (tp->link_config.phy_is_low_power)
9090 return -EAGAIN;
9091
9092 spin_lock_bh(&tp->lock);
9093 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9094 spin_unlock_bh(&tp->lock);
9095
9096 return err;
9097
9098 default:
9099 /* do nothing */
9100 break;
9101 }
9102 return -EOPNOTSUPP;
9103 }
9104
9105 #if TG3_VLAN_TAG_USED
9106 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9107 {
9108 struct tg3 *tp = netdev_priv(dev);
9109
9110 if (netif_running(dev))
9111 tg3_netif_stop(tp);
9112
9113 tg3_full_lock(tp, 0);
9114
9115 tp->vlgrp = grp;
9116
9117 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9118 __tg3_set_rx_mode(dev);
9119
9120 tg3_full_unlock(tp);
9121
9122 if (netif_running(dev))
9123 tg3_netif_start(tp);
9124 }
9125
9126 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9127 {
9128 struct tg3 *tp = netdev_priv(dev);
9129
9130 if (netif_running(dev))
9131 tg3_netif_stop(tp);
9132
9133 tg3_full_lock(tp, 0);
9134 vlan_group_set_device(tp->vlgrp, vid, NULL);
9135 tg3_full_unlock(tp);
9136
9137 if (netif_running(dev))
9138 tg3_netif_start(tp);
9139 }
9140 #endif
9141
9142 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9143 {
9144 struct tg3 *tp = netdev_priv(dev);
9145
9146 memcpy(ec, &tp->coal, sizeof(*ec));
9147 return 0;
9148 }
9149
9150 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9151 {
9152 struct tg3 *tp = netdev_priv(dev);
9153 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9154 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9155
9156 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9157 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9158 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9159 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9160 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9161 }
9162
9163 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9164 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9165 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9166 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9167 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9168 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9169 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9170 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9171 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9172 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9173 return -EINVAL;
9174
9175 /* No rx interrupts will be generated if both are zero */
9176 if ((ec->rx_coalesce_usecs == 0) &&
9177 (ec->rx_max_coalesced_frames == 0))
9178 return -EINVAL;
9179
9180 /* No tx interrupts will be generated if both are zero */
9181 if ((ec->tx_coalesce_usecs == 0) &&
9182 (ec->tx_max_coalesced_frames == 0))
9183 return -EINVAL;
9184
9185 /* Only copy relevant parameters, ignore all others. */
9186 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9187 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9188 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9189 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9190 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9191 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9192 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9193 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9194 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9195
9196 if (netif_running(dev)) {
9197 tg3_full_lock(tp, 0);
9198 __tg3_set_coalesce(tp, &tp->coal);
9199 tg3_full_unlock(tp);
9200 }
9201 return 0;
9202 }
9203
9204 static const struct ethtool_ops tg3_ethtool_ops = {
9205 .get_settings = tg3_get_settings,
9206 .set_settings = tg3_set_settings,
9207 .get_drvinfo = tg3_get_drvinfo,
9208 .get_regs_len = tg3_get_regs_len,
9209 .get_regs = tg3_get_regs,
9210 .get_wol = tg3_get_wol,
9211 .set_wol = tg3_set_wol,
9212 .get_msglevel = tg3_get_msglevel,
9213 .set_msglevel = tg3_set_msglevel,
9214 .nway_reset = tg3_nway_reset,
9215 .get_link = ethtool_op_get_link,
9216 .get_eeprom_len = tg3_get_eeprom_len,
9217 .get_eeprom = tg3_get_eeprom,
9218 .set_eeprom = tg3_set_eeprom,
9219 .get_ringparam = tg3_get_ringparam,
9220 .set_ringparam = tg3_set_ringparam,
9221 .get_pauseparam = tg3_get_pauseparam,
9222 .set_pauseparam = tg3_set_pauseparam,
9223 .get_rx_csum = tg3_get_rx_csum,
9224 .set_rx_csum = tg3_set_rx_csum,
9225 .get_tx_csum = ethtool_op_get_tx_csum,
9226 .set_tx_csum = tg3_set_tx_csum,
9227 .get_sg = ethtool_op_get_sg,
9228 .set_sg = ethtool_op_set_sg,
9229 .get_tso = ethtool_op_get_tso,
9230 .set_tso = tg3_set_tso,
9231 .self_test_count = tg3_get_test_count,
9232 .self_test = tg3_self_test,
9233 .get_strings = tg3_get_strings,
9234 .phys_id = tg3_phys_id,
9235 .get_stats_count = tg3_get_stats_count,
9236 .get_ethtool_stats = tg3_get_ethtool_stats,
9237 .get_coalesce = tg3_get_coalesce,
9238 .set_coalesce = tg3_set_coalesce,
9239 .get_perm_addr = ethtool_op_get_perm_addr,
9240 };
9241
9242 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9243 {
9244 u32 cursize, val, magic;
9245
9246 tp->nvram_size = EEPROM_CHIP_SIZE;
9247
9248 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9249 return;
9250
9251 if ((magic != TG3_EEPROM_MAGIC) &&
9252 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9253 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9254 return;
9255
9256 /*
9257 * Size the chip by reading offsets at increasing powers of two.
9258 * When we encounter our validation signature, we know the addressing
9259 * has wrapped around, and thus have our chip size.
9260 */
9261 cursize = 0x10;
9262
9263 while (cursize < tp->nvram_size) {
9264 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9265 return;
9266
9267 if (val == magic)
9268 break;
9269
9270 cursize <<= 1;
9271 }
9272
9273 tp->nvram_size = cursize;
9274 }
9275
9276 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9277 {
9278 u32 val;
9279
9280 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9281 return;
9282
9283 /* Selfboot format */
9284 if (val != TG3_EEPROM_MAGIC) {
9285 tg3_get_eeprom_size(tp);
9286 return;
9287 }
9288
9289 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9290 if (val != 0) {
9291 tp->nvram_size = (val >> 16) * 1024;
9292 return;
9293 }
9294 }
9295 tp->nvram_size = 0x80000;
9296 }
9297
9298 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9299 {
9300 u32 nvcfg1;
9301
9302 nvcfg1 = tr32(NVRAM_CFG1);
9303 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9304 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9305 }
9306 else {
9307 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9308 tw32(NVRAM_CFG1, nvcfg1);
9309 }
9310
9311 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9312 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9313 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9314 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9315 tp->nvram_jedecnum = JEDEC_ATMEL;
9316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9318 break;
9319 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9320 tp->nvram_jedecnum = JEDEC_ATMEL;
9321 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9322 break;
9323 case FLASH_VENDOR_ATMEL_EEPROM:
9324 tp->nvram_jedecnum = JEDEC_ATMEL;
9325 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9327 break;
9328 case FLASH_VENDOR_ST:
9329 tp->nvram_jedecnum = JEDEC_ST;
9330 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9331 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9332 break;
9333 case FLASH_VENDOR_SAIFUN:
9334 tp->nvram_jedecnum = JEDEC_SAIFUN;
9335 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9336 break;
9337 case FLASH_VENDOR_SST_SMALL:
9338 case FLASH_VENDOR_SST_LARGE:
9339 tp->nvram_jedecnum = JEDEC_SST;
9340 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9341 break;
9342 }
9343 }
9344 else {
9345 tp->nvram_jedecnum = JEDEC_ATMEL;
9346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9347 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9348 }
9349 }
9350
9351 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9352 {
9353 u32 nvcfg1;
9354
9355 nvcfg1 = tr32(NVRAM_CFG1);
9356
9357 /* NVRAM protection for TPM */
9358 if (nvcfg1 & (1 << 27))
9359 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9360
9361 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9362 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9363 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9364 tp->nvram_jedecnum = JEDEC_ATMEL;
9365 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9366 break;
9367 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9368 tp->nvram_jedecnum = JEDEC_ATMEL;
9369 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9370 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9371 break;
9372 case FLASH_5752VENDOR_ST_M45PE10:
9373 case FLASH_5752VENDOR_ST_M45PE20:
9374 case FLASH_5752VENDOR_ST_M45PE40:
9375 tp->nvram_jedecnum = JEDEC_ST;
9376 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9377 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9378 break;
9379 }
9380
9381 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9382 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9383 case FLASH_5752PAGE_SIZE_256:
9384 tp->nvram_pagesize = 256;
9385 break;
9386 case FLASH_5752PAGE_SIZE_512:
9387 tp->nvram_pagesize = 512;
9388 break;
9389 case FLASH_5752PAGE_SIZE_1K:
9390 tp->nvram_pagesize = 1024;
9391 break;
9392 case FLASH_5752PAGE_SIZE_2K:
9393 tp->nvram_pagesize = 2048;
9394 break;
9395 case FLASH_5752PAGE_SIZE_4K:
9396 tp->nvram_pagesize = 4096;
9397 break;
9398 case FLASH_5752PAGE_SIZE_264:
9399 tp->nvram_pagesize = 264;
9400 break;
9401 }
9402 }
9403 else {
9404 /* For eeprom, set pagesize to maximum eeprom size */
9405 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9406
9407 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9408 tw32(NVRAM_CFG1, nvcfg1);
9409 }
9410 }
9411
9412 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9413 {
9414 u32 nvcfg1, protect = 0;
9415
9416 nvcfg1 = tr32(NVRAM_CFG1);
9417
9418 /* NVRAM protection for TPM */
9419 if (nvcfg1 & (1 << 27)) {
9420 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9421 protect = 1;
9422 }
9423
9424 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9425 switch (nvcfg1) {
9426 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9427 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9428 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9429 tp->nvram_jedecnum = JEDEC_ATMEL;
9430 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9431 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9432 tp->nvram_pagesize = 264;
9433 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9434 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9435 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9436 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9437 else
9438 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9439 break;
9440 case FLASH_5752VENDOR_ST_M45PE10:
9441 case FLASH_5752VENDOR_ST_M45PE20:
9442 case FLASH_5752VENDOR_ST_M45PE40:
9443 tp->nvram_jedecnum = JEDEC_ST;
9444 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9445 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9446 tp->nvram_pagesize = 256;
9447 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9448 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9449 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9450 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9451 else
9452 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9453 break;
9454 }
9455 }
9456
9457 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9458 {
9459 u32 nvcfg1;
9460
9461 nvcfg1 = tr32(NVRAM_CFG1);
9462
9463 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9464 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9465 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9466 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9467 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9468 tp->nvram_jedecnum = JEDEC_ATMEL;
9469 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9470 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9471
9472 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9473 tw32(NVRAM_CFG1, nvcfg1);
9474 break;
9475 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9476 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9477 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9478 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9479 tp->nvram_jedecnum = JEDEC_ATMEL;
9480 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9481 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9482 tp->nvram_pagesize = 264;
9483 break;
9484 case FLASH_5752VENDOR_ST_M45PE10:
9485 case FLASH_5752VENDOR_ST_M45PE20:
9486 case FLASH_5752VENDOR_ST_M45PE40:
9487 tp->nvram_jedecnum = JEDEC_ST;
9488 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9489 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9490 tp->nvram_pagesize = 256;
9491 break;
9492 }
9493 }
9494
9495 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9496 {
9497 tp->nvram_jedecnum = JEDEC_ATMEL;
9498 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9499 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9500 }
9501
9502 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9503 static void __devinit tg3_nvram_init(struct tg3 *tp)
9504 {
9505 tw32_f(GRC_EEPROM_ADDR,
9506 (EEPROM_ADDR_FSM_RESET |
9507 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9508 EEPROM_ADDR_CLKPERD_SHIFT)));
9509
9510 msleep(1);
9511
9512 /* Enable seeprom accesses. */
9513 tw32_f(GRC_LOCAL_CTRL,
9514 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9515 udelay(100);
9516
9517 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9518 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9519 tp->tg3_flags |= TG3_FLAG_NVRAM;
9520
9521 if (tg3_nvram_lock(tp)) {
9522 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9523 "tg3_nvram_init failed.\n", tp->dev->name);
9524 return;
9525 }
9526 tg3_enable_nvram_access(tp);
9527
9528 tp->nvram_size = 0;
9529
9530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9531 tg3_get_5752_nvram_info(tp);
9532 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9533 tg3_get_5755_nvram_info(tp);
9534 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9535 tg3_get_5787_nvram_info(tp);
9536 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9537 tg3_get_5906_nvram_info(tp);
9538 else
9539 tg3_get_nvram_info(tp);
9540
9541 if (tp->nvram_size == 0)
9542 tg3_get_nvram_size(tp);
9543
9544 tg3_disable_nvram_access(tp);
9545 tg3_nvram_unlock(tp);
9546
9547 } else {
9548 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9549
9550 tg3_get_eeprom_size(tp);
9551 }
9552 }
9553
9554 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9555 u32 offset, u32 *val)
9556 {
9557 u32 tmp;
9558 int i;
9559
9560 if (offset > EEPROM_ADDR_ADDR_MASK ||
9561 (offset % 4) != 0)
9562 return -EINVAL;
9563
9564 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9565 EEPROM_ADDR_DEVID_MASK |
9566 EEPROM_ADDR_READ);
9567 tw32(GRC_EEPROM_ADDR,
9568 tmp |
9569 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9570 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9571 EEPROM_ADDR_ADDR_MASK) |
9572 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9573
9574 for (i = 0; i < 1000; i++) {
9575 tmp = tr32(GRC_EEPROM_ADDR);
9576
9577 if (tmp & EEPROM_ADDR_COMPLETE)
9578 break;
9579 msleep(1);
9580 }
9581 if (!(tmp & EEPROM_ADDR_COMPLETE))
9582 return -EBUSY;
9583
9584 *val = tr32(GRC_EEPROM_DATA);
9585 return 0;
9586 }
9587
9588 #define NVRAM_CMD_TIMEOUT 10000
9589
9590 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9591 {
9592 int i;
9593
9594 tw32(NVRAM_CMD, nvram_cmd);
9595 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9596 udelay(10);
9597 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9598 udelay(10);
9599 break;
9600 }
9601 }
9602 if (i == NVRAM_CMD_TIMEOUT) {
9603 return -EBUSY;
9604 }
9605 return 0;
9606 }
9607
9608 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9609 {
9610 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9611 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9612 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9613 (tp->nvram_jedecnum == JEDEC_ATMEL))
9614
9615 addr = ((addr / tp->nvram_pagesize) <<
9616 ATMEL_AT45DB0X1B_PAGE_POS) +
9617 (addr % tp->nvram_pagesize);
9618
9619 return addr;
9620 }
9621
9622 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9623 {
9624 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9625 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9626 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9627 (tp->nvram_jedecnum == JEDEC_ATMEL))
9628
9629 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9630 tp->nvram_pagesize) +
9631 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9632
9633 return addr;
9634 }
9635
9636 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9637 {
9638 int ret;
9639
9640 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9641 return tg3_nvram_read_using_eeprom(tp, offset, val);
9642
9643 offset = tg3_nvram_phys_addr(tp, offset);
9644
9645 if (offset > NVRAM_ADDR_MSK)
9646 return -EINVAL;
9647
9648 ret = tg3_nvram_lock(tp);
9649 if (ret)
9650 return ret;
9651
9652 tg3_enable_nvram_access(tp);
9653
9654 tw32(NVRAM_ADDR, offset);
9655 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9656 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9657
9658 if (ret == 0)
9659 *val = swab32(tr32(NVRAM_RDDATA));
9660
9661 tg3_disable_nvram_access(tp);
9662
9663 tg3_nvram_unlock(tp);
9664
9665 return ret;
9666 }
9667
9668 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9669 {
9670 int err;
9671 u32 tmp;
9672
9673 err = tg3_nvram_read(tp, offset, &tmp);
9674 *val = swab32(tmp);
9675 return err;
9676 }
9677
9678 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9679 u32 offset, u32 len, u8 *buf)
9680 {
9681 int i, j, rc = 0;
9682 u32 val;
9683
9684 for (i = 0; i < len; i += 4) {
9685 u32 addr, data;
9686
9687 addr = offset + i;
9688
9689 memcpy(&data, buf + i, 4);
9690
9691 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9692
9693 val = tr32(GRC_EEPROM_ADDR);
9694 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9695
9696 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9697 EEPROM_ADDR_READ);
9698 tw32(GRC_EEPROM_ADDR, val |
9699 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9700 (addr & EEPROM_ADDR_ADDR_MASK) |
9701 EEPROM_ADDR_START |
9702 EEPROM_ADDR_WRITE);
9703
9704 for (j = 0; j < 1000; j++) {
9705 val = tr32(GRC_EEPROM_ADDR);
9706
9707 if (val & EEPROM_ADDR_COMPLETE)
9708 break;
9709 msleep(1);
9710 }
9711 if (!(val & EEPROM_ADDR_COMPLETE)) {
9712 rc = -EBUSY;
9713 break;
9714 }
9715 }
9716
9717 return rc;
9718 }
9719
9720 /* offset and length are dword aligned */
9721 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9722 u8 *buf)
9723 {
9724 int ret = 0;
9725 u32 pagesize = tp->nvram_pagesize;
9726 u32 pagemask = pagesize - 1;
9727 u32 nvram_cmd;
9728 u8 *tmp;
9729
9730 tmp = kmalloc(pagesize, GFP_KERNEL);
9731 if (tmp == NULL)
9732 return -ENOMEM;
9733
9734 while (len) {
9735 int j;
9736 u32 phy_addr, page_off, size;
9737
9738 phy_addr = offset & ~pagemask;
9739
9740 for (j = 0; j < pagesize; j += 4) {
9741 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9742 (u32 *) (tmp + j))))
9743 break;
9744 }
9745 if (ret)
9746 break;
9747
9748 page_off = offset & pagemask;
9749 size = pagesize;
9750 if (len < size)
9751 size = len;
9752
9753 len -= size;
9754
9755 memcpy(tmp + page_off, buf, size);
9756
9757 offset = offset + (pagesize - page_off);
9758
9759 tg3_enable_nvram_access(tp);
9760
9761 /*
9762 * Before we can erase the flash page, we need
9763 * to issue a special "write enable" command.
9764 */
9765 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9766
9767 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9768 break;
9769
9770 /* Erase the target page */
9771 tw32(NVRAM_ADDR, phy_addr);
9772
9773 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9774 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9775
9776 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9777 break;
9778
9779 /* Issue another write enable to start the write. */
9780 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9781
9782 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9783 break;
9784
9785 for (j = 0; j < pagesize; j += 4) {
9786 u32 data;
9787
9788 data = *((u32 *) (tmp + j));
9789 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9790
9791 tw32(NVRAM_ADDR, phy_addr + j);
9792
9793 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9794 NVRAM_CMD_WR;
9795
9796 if (j == 0)
9797 nvram_cmd |= NVRAM_CMD_FIRST;
9798 else if (j == (pagesize - 4))
9799 nvram_cmd |= NVRAM_CMD_LAST;
9800
9801 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9802 break;
9803 }
9804 if (ret)
9805 break;
9806 }
9807
9808 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9809 tg3_nvram_exec_cmd(tp, nvram_cmd);
9810
9811 kfree(tmp);
9812
9813 return ret;
9814 }
9815
9816 /* offset and length are dword aligned */
9817 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9818 u8 *buf)
9819 {
9820 int i, ret = 0;
9821
9822 for (i = 0; i < len; i += 4, offset += 4) {
9823 u32 data, page_off, phy_addr, nvram_cmd;
9824
9825 memcpy(&data, buf + i, 4);
9826 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9827
9828 page_off = offset % tp->nvram_pagesize;
9829
9830 phy_addr = tg3_nvram_phys_addr(tp, offset);
9831
9832 tw32(NVRAM_ADDR, phy_addr);
9833
9834 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9835
9836 if ((page_off == 0) || (i == 0))
9837 nvram_cmd |= NVRAM_CMD_FIRST;
9838 if (page_off == (tp->nvram_pagesize - 4))
9839 nvram_cmd |= NVRAM_CMD_LAST;
9840
9841 if (i == (len - 4))
9842 nvram_cmd |= NVRAM_CMD_LAST;
9843
9844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9845 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9846 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9847 (tp->nvram_jedecnum == JEDEC_ST) &&
9848 (nvram_cmd & NVRAM_CMD_FIRST)) {
9849
9850 if ((ret = tg3_nvram_exec_cmd(tp,
9851 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9852 NVRAM_CMD_DONE)))
9853
9854 break;
9855 }
9856 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9857 /* We always do complete word writes to eeprom. */
9858 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9859 }
9860
9861 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9862 break;
9863 }
9864 return ret;
9865 }
9866
9867 /* offset and length are dword aligned */
9868 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9869 {
9870 int ret;
9871
9872 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9873 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9874 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9875 udelay(40);
9876 }
9877
9878 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9879 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9880 }
9881 else {
9882 u32 grc_mode;
9883
9884 ret = tg3_nvram_lock(tp);
9885 if (ret)
9886 return ret;
9887
9888 tg3_enable_nvram_access(tp);
9889 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9890 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9891 tw32(NVRAM_WRITE1, 0x406);
9892
9893 grc_mode = tr32(GRC_MODE);
9894 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9895
9896 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9897 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9898
9899 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9900 buf);
9901 }
9902 else {
9903 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9904 buf);
9905 }
9906
9907 grc_mode = tr32(GRC_MODE);
9908 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9909
9910 tg3_disable_nvram_access(tp);
9911 tg3_nvram_unlock(tp);
9912 }
9913
9914 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9915 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9916 udelay(40);
9917 }
9918
9919 return ret;
9920 }
9921
9922 struct subsys_tbl_ent {
9923 u16 subsys_vendor, subsys_devid;
9924 u32 phy_id;
9925 };
9926
9927 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9928 /* Broadcom boards. */
9929 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9930 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9931 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9932 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9933 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9934 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9935 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9936 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9937 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9938 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9939 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9940
9941 /* 3com boards. */
9942 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9943 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9944 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9945 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9946 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9947
9948 /* DELL boards. */
9949 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9950 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9951 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9952 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9953
9954 /* Compaq boards. */
9955 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9956 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9957 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9958 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9959 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9960
9961 /* IBM boards. */
9962 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9963 };
9964
9965 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9966 {
9967 int i;
9968
9969 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9970 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9971 tp->pdev->subsystem_vendor) &&
9972 (subsys_id_to_phy_id[i].subsys_devid ==
9973 tp->pdev->subsystem_device))
9974 return &subsys_id_to_phy_id[i];
9975 }
9976 return NULL;
9977 }
9978
9979 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9980 {
9981 u32 val;
9982 u16 pmcsr;
9983
9984 /* On some early chips the SRAM cannot be accessed in D3hot state,
9985 * so need make sure we're in D0.
9986 */
9987 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9988 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9989 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9990 msleep(1);
9991
9992 /* Make sure register accesses (indirect or otherwise)
9993 * will function correctly.
9994 */
9995 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9996 tp->misc_host_ctrl);
9997
9998 /* The memory arbiter has to be enabled in order for SRAM accesses
9999 * to succeed. Normally on powerup the tg3 chip firmware will make
10000 * sure it is enabled, but other entities such as system netboot
10001 * code might disable it.
10002 */
10003 val = tr32(MEMARB_MODE);
10004 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10005
10006 tp->phy_id = PHY_ID_INVALID;
10007 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10008
10009 /* Assume an onboard device and WOL capable by default. */
10010 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10011
10012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10013 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10014 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10015 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10016 }
10017 return;
10018 }
10019
10020 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10021 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10022 u32 nic_cfg, led_cfg;
10023 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10024 int eeprom_phy_serdes = 0;
10025
10026 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10027 tp->nic_sram_data_cfg = nic_cfg;
10028
10029 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10030 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10031 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10032 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10033 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10034 (ver > 0) && (ver < 0x100))
10035 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10036
10037 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10038 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10039 eeprom_phy_serdes = 1;
10040
10041 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10042 if (nic_phy_id != 0) {
10043 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10044 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10045
10046 eeprom_phy_id = (id1 >> 16) << 10;
10047 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10048 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10049 } else
10050 eeprom_phy_id = 0;
10051
10052 tp->phy_id = eeprom_phy_id;
10053 if (eeprom_phy_serdes) {
10054 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10055 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10056 else
10057 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10058 }
10059
10060 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10061 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10062 SHASTA_EXT_LED_MODE_MASK);
10063 else
10064 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10065
10066 switch (led_cfg) {
10067 default:
10068 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10069 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10070 break;
10071
10072 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10073 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10074 break;
10075
10076 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10077 tp->led_ctrl = LED_CTRL_MODE_MAC;
10078
10079 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10080 * read on some older 5700/5701 bootcode.
10081 */
10082 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10083 ASIC_REV_5700 ||
10084 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10085 ASIC_REV_5701)
10086 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10087
10088 break;
10089
10090 case SHASTA_EXT_LED_SHARED:
10091 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10092 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10093 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10094 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10095 LED_CTRL_MODE_PHY_2);
10096 break;
10097
10098 case SHASTA_EXT_LED_MAC:
10099 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10100 break;
10101
10102 case SHASTA_EXT_LED_COMBO:
10103 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10104 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10105 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10106 LED_CTRL_MODE_PHY_2);
10107 break;
10108
10109 };
10110
10111 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10113 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10114 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10115
10116 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10117 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10118 if ((tp->pdev->subsystem_vendor ==
10119 PCI_VENDOR_ID_ARIMA) &&
10120 (tp->pdev->subsystem_device == 0x205a ||
10121 tp->pdev->subsystem_device == 0x2063))
10122 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10123 } else {
10124 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10125 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10126 }
10127
10128 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10129 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10130 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10131 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10132 }
10133 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10134 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10135 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10136
10137 if (cfg2 & (1 << 17))
10138 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10139
10140 /* serdes signal pre-emphasis in register 0x590 set by */
10141 /* bootcode if bit 18 is set */
10142 if (cfg2 & (1 << 18))
10143 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10144 }
10145 }
10146
10147 static int __devinit tg3_phy_probe(struct tg3 *tp)
10148 {
10149 u32 hw_phy_id_1, hw_phy_id_2;
10150 u32 hw_phy_id, hw_phy_id_masked;
10151 int err;
10152
10153 /* Reading the PHY ID register can conflict with ASF
10154 * firwmare access to the PHY hardware.
10155 */
10156 err = 0;
10157 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10158 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10159 } else {
10160 /* Now read the physical PHY_ID from the chip and verify
10161 * that it is sane. If it doesn't look good, we fall back
10162 * to either the hard-coded table based PHY_ID and failing
10163 * that the value found in the eeprom area.
10164 */
10165 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10166 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10167
10168 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10169 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10170 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10171
10172 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10173 }
10174
10175 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10176 tp->phy_id = hw_phy_id;
10177 if (hw_phy_id_masked == PHY_ID_BCM8002)
10178 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10179 else
10180 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10181 } else {
10182 if (tp->phy_id != PHY_ID_INVALID) {
10183 /* Do nothing, phy ID already set up in
10184 * tg3_get_eeprom_hw_cfg().
10185 */
10186 } else {
10187 struct subsys_tbl_ent *p;
10188
10189 /* No eeprom signature? Try the hardcoded
10190 * subsys device table.
10191 */
10192 p = lookup_by_subsys(tp);
10193 if (!p)
10194 return -ENODEV;
10195
10196 tp->phy_id = p->phy_id;
10197 if (!tp->phy_id ||
10198 tp->phy_id == PHY_ID_BCM8002)
10199 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10200 }
10201 }
10202
10203 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10204 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10205 u32 bmsr, adv_reg, tg3_ctrl, mask;
10206
10207 tg3_readphy(tp, MII_BMSR, &bmsr);
10208 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10209 (bmsr & BMSR_LSTATUS))
10210 goto skip_phy_reset;
10211
10212 err = tg3_phy_reset(tp);
10213 if (err)
10214 return err;
10215
10216 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10217 ADVERTISE_100HALF | ADVERTISE_100FULL |
10218 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10219 tg3_ctrl = 0;
10220 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10221 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10222 MII_TG3_CTRL_ADV_1000_FULL);
10223 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10224 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10225 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10226 MII_TG3_CTRL_ENABLE_AS_MASTER);
10227 }
10228
10229 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10230 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10231 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10232 if (!tg3_copper_is_advertising_all(tp, mask)) {
10233 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10234
10235 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10236 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10237
10238 tg3_writephy(tp, MII_BMCR,
10239 BMCR_ANENABLE | BMCR_ANRESTART);
10240 }
10241 tg3_phy_set_wirespeed(tp);
10242
10243 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10244 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10245 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10246 }
10247
10248 skip_phy_reset:
10249 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10250 err = tg3_init_5401phy_dsp(tp);
10251 if (err)
10252 return err;
10253 }
10254
10255 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10256 err = tg3_init_5401phy_dsp(tp);
10257 }
10258
10259 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10260 tp->link_config.advertising =
10261 (ADVERTISED_1000baseT_Half |
10262 ADVERTISED_1000baseT_Full |
10263 ADVERTISED_Autoneg |
10264 ADVERTISED_FIBRE);
10265 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10266 tp->link_config.advertising &=
10267 ~(ADVERTISED_1000baseT_Half |
10268 ADVERTISED_1000baseT_Full);
10269
10270 return err;
10271 }
10272
10273 static void __devinit tg3_read_partno(struct tg3 *tp)
10274 {
10275 unsigned char vpd_data[256];
10276 unsigned int i;
10277 u32 magic;
10278
10279 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10280 goto out_not_found;
10281
10282 if (magic == TG3_EEPROM_MAGIC) {
10283 for (i = 0; i < 256; i += 4) {
10284 u32 tmp;
10285
10286 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10287 goto out_not_found;
10288
10289 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10290 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10291 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10292 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10293 }
10294 } else {
10295 int vpd_cap;
10296
10297 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10298 for (i = 0; i < 256; i += 4) {
10299 u32 tmp, j = 0;
10300 u16 tmp16;
10301
10302 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10303 i);
10304 while (j++ < 100) {
10305 pci_read_config_word(tp->pdev, vpd_cap +
10306 PCI_VPD_ADDR, &tmp16);
10307 if (tmp16 & 0x8000)
10308 break;
10309 msleep(1);
10310 }
10311 if (!(tmp16 & 0x8000))
10312 goto out_not_found;
10313
10314 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10315 &tmp);
10316 tmp = cpu_to_le32(tmp);
10317 memcpy(&vpd_data[i], &tmp, 4);
10318 }
10319 }
10320
10321 /* Now parse and find the part number. */
10322 for (i = 0; i < 254; ) {
10323 unsigned char val = vpd_data[i];
10324 unsigned int block_end;
10325
10326 if (val == 0x82 || val == 0x91) {
10327 i = (i + 3 +
10328 (vpd_data[i + 1] +
10329 (vpd_data[i + 2] << 8)));
10330 continue;
10331 }
10332
10333 if (val != 0x90)
10334 goto out_not_found;
10335
10336 block_end = (i + 3 +
10337 (vpd_data[i + 1] +
10338 (vpd_data[i + 2] << 8)));
10339 i += 3;
10340
10341 if (block_end > 256)
10342 goto out_not_found;
10343
10344 while (i < (block_end - 2)) {
10345 if (vpd_data[i + 0] == 'P' &&
10346 vpd_data[i + 1] == 'N') {
10347 int partno_len = vpd_data[i + 2];
10348
10349 i += 3;
10350 if (partno_len > 24 || (partno_len + i) > 256)
10351 goto out_not_found;
10352
10353 memcpy(tp->board_part_number,
10354 &vpd_data[i], partno_len);
10355
10356 /* Success. */
10357 return;
10358 }
10359 i += 3 + vpd_data[i + 2];
10360 }
10361
10362 /* Part number not found. */
10363 goto out_not_found;
10364 }
10365
10366 out_not_found:
10367 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10368 strcpy(tp->board_part_number, "BCM95906");
10369 else
10370 strcpy(tp->board_part_number, "none");
10371 }
10372
10373 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10374 {
10375 u32 val, offset, start;
10376
10377 if (tg3_nvram_read_swab(tp, 0, &val))
10378 return;
10379
10380 if (val != TG3_EEPROM_MAGIC)
10381 return;
10382
10383 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10384 tg3_nvram_read_swab(tp, 0x4, &start))
10385 return;
10386
10387 offset = tg3_nvram_logical_addr(tp, offset);
10388 if (tg3_nvram_read_swab(tp, offset, &val))
10389 return;
10390
10391 if ((val & 0xfc000000) == 0x0c000000) {
10392 u32 ver_offset, addr;
10393 int i;
10394
10395 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10396 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10397 return;
10398
10399 if (val != 0)
10400 return;
10401
10402 addr = offset + ver_offset - start;
10403 for (i = 0; i < 16; i += 4) {
10404 if (tg3_nvram_read(tp, addr + i, &val))
10405 return;
10406
10407 val = cpu_to_le32(val);
10408 memcpy(tp->fw_ver + i, &val, 4);
10409 }
10410 }
10411 }
10412
10413 static int __devinit tg3_get_invariants(struct tg3 *tp)
10414 {
10415 static struct pci_device_id write_reorder_chipsets[] = {
10416 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10417 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10418 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10419 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10420 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10421 PCI_DEVICE_ID_VIA_8385_0) },
10422 { },
10423 };
10424 u32 misc_ctrl_reg;
10425 u32 cacheline_sz_reg;
10426 u32 pci_state_reg, grc_misc_cfg;
10427 u32 val;
10428 u16 pci_cmd;
10429 int err, pcie_cap;
10430
10431 /* Force memory write invalidate off. If we leave it on,
10432 * then on 5700_BX chips we have to enable a workaround.
10433 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10434 * to match the cacheline size. The Broadcom driver have this
10435 * workaround but turns MWI off all the times so never uses
10436 * it. This seems to suggest that the workaround is insufficient.
10437 */
10438 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10439 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10440 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10441
10442 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10443 * has the register indirect write enable bit set before
10444 * we try to access any of the MMIO registers. It is also
10445 * critical that the PCI-X hw workaround situation is decided
10446 * before that as well.
10447 */
10448 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10449 &misc_ctrl_reg);
10450
10451 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10452 MISC_HOST_CTRL_CHIPREV_SHIFT);
10453
10454 /* Wrong chip ID in 5752 A0. This code can be removed later
10455 * as A0 is not in production.
10456 */
10457 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10458 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10459
10460 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10461 * we need to disable memory and use config. cycles
10462 * only to access all registers. The 5702/03 chips
10463 * can mistakenly decode the special cycles from the
10464 * ICH chipsets as memory write cycles, causing corruption
10465 * of register and memory space. Only certain ICH bridges
10466 * will drive special cycles with non-zero data during the
10467 * address phase which can fall within the 5703's address
10468 * range. This is not an ICH bug as the PCI spec allows
10469 * non-zero address during special cycles. However, only
10470 * these ICH bridges are known to drive non-zero addresses
10471 * during special cycles.
10472 *
10473 * Since special cycles do not cross PCI bridges, we only
10474 * enable this workaround if the 5703 is on the secondary
10475 * bus of these ICH bridges.
10476 */
10477 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10478 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10479 static struct tg3_dev_id {
10480 u32 vendor;
10481 u32 device;
10482 u32 rev;
10483 } ich_chipsets[] = {
10484 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10485 PCI_ANY_ID },
10486 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10487 PCI_ANY_ID },
10488 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10489 0xa },
10490 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10491 PCI_ANY_ID },
10492 { },
10493 };
10494 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10495 struct pci_dev *bridge = NULL;
10496
10497 while (pci_id->vendor != 0) {
10498 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10499 bridge);
10500 if (!bridge) {
10501 pci_id++;
10502 continue;
10503 }
10504 if (pci_id->rev != PCI_ANY_ID) {
10505 u8 rev;
10506
10507 pci_read_config_byte(bridge, PCI_REVISION_ID,
10508 &rev);
10509 if (rev > pci_id->rev)
10510 continue;
10511 }
10512 if (bridge->subordinate &&
10513 (bridge->subordinate->number ==
10514 tp->pdev->bus->number)) {
10515
10516 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10517 pci_dev_put(bridge);
10518 break;
10519 }
10520 }
10521 }
10522
10523 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10524 * DMA addresses > 40-bit. This bridge may have other additional
10525 * 57xx devices behind it in some 4-port NIC designs for example.
10526 * Any tg3 device found behind the bridge will also need the 40-bit
10527 * DMA workaround.
10528 */
10529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10530 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10531 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10532 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10533 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10534 }
10535 else {
10536 struct pci_dev *bridge = NULL;
10537
10538 do {
10539 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10540 PCI_DEVICE_ID_SERVERWORKS_EPB,
10541 bridge);
10542 if (bridge && bridge->subordinate &&
10543 (bridge->subordinate->number <=
10544 tp->pdev->bus->number) &&
10545 (bridge->subordinate->subordinate >=
10546 tp->pdev->bus->number)) {
10547 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10548 pci_dev_put(bridge);
10549 break;
10550 }
10551 } while (bridge);
10552 }
10553
10554 /* Initialize misc host control in PCI block. */
10555 tp->misc_host_ctrl |= (misc_ctrl_reg &
10556 MISC_HOST_CTRL_CHIPREV);
10557 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10558 tp->misc_host_ctrl);
10559
10560 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10561 &cacheline_sz_reg);
10562
10563 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10564 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10565 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10566 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10567
10568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10573 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10574 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10575
10576 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10577 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10578 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10579
10580 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10581 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10582 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10583 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10584 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10585 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10586 } else {
10587 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10588 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10589 ASIC_REV_5750 &&
10590 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10591 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10592 }
10593 }
10594
10595 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10596 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10597 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10598 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10599 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10600 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10601 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10602
10603 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10604 if (pcie_cap != 0) {
10605 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10607 u16 lnkctl;
10608
10609 pci_read_config_word(tp->pdev,
10610 pcie_cap + PCI_EXP_LNKCTL,
10611 &lnkctl);
10612 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10613 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10614 }
10615 }
10616
10617 /* If we have an AMD 762 or VIA K8T800 chipset, write
10618 * reordering to the mailbox registers done by the host
10619 * controller can cause major troubles. We read back from
10620 * every mailbox register write to force the writes to be
10621 * posted to the chip in order.
10622 */
10623 if (pci_dev_present(write_reorder_chipsets) &&
10624 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10625 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10626
10627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10628 tp->pci_lat_timer < 64) {
10629 tp->pci_lat_timer = 64;
10630
10631 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10632 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10633 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10634 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10635
10636 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10637 cacheline_sz_reg);
10638 }
10639
10640 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10641 &pci_state_reg);
10642
10643 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10644 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10645
10646 /* If this is a 5700 BX chipset, and we are in PCI-X
10647 * mode, enable register write workaround.
10648 *
10649 * The workaround is to use indirect register accesses
10650 * for all chip writes not to mailbox registers.
10651 */
10652 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10653 u32 pm_reg;
10654 u16 pci_cmd;
10655
10656 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10657
10658 /* The chip can have it's power management PCI config
10659 * space registers clobbered due to this bug.
10660 * So explicitly force the chip into D0 here.
10661 */
10662 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10663 &pm_reg);
10664 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10665 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10666 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10667 pm_reg);
10668
10669 /* Also, force SERR#/PERR# in PCI command. */
10670 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10671 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10672 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10673 }
10674 }
10675
10676 /* 5700 BX chips need to have their TX producer index mailboxes
10677 * written twice to workaround a bug.
10678 */
10679 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10680 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10681
10682 /* Back to back register writes can cause problems on this chip,
10683 * the workaround is to read back all reg writes except those to
10684 * mailbox regs. See tg3_write_indirect_reg32().
10685 *
10686 * PCI Express 5750_A0 rev chips need this workaround too.
10687 */
10688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10689 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10690 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10691 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10692
10693 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10694 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10695 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10696 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10697
10698 /* Chip-specific fixup from Broadcom driver */
10699 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10700 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10701 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10702 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10703 }
10704
10705 /* Default fast path register access methods */
10706 tp->read32 = tg3_read32;
10707 tp->write32 = tg3_write32;
10708 tp->read32_mbox = tg3_read32;
10709 tp->write32_mbox = tg3_write32;
10710 tp->write32_tx_mbox = tg3_write32;
10711 tp->write32_rx_mbox = tg3_write32;
10712
10713 /* Various workaround register access methods */
10714 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10715 tp->write32 = tg3_write_indirect_reg32;
10716 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10717 tp->write32 = tg3_write_flush_reg32;
10718
10719 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10720 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10721 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10722 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10723 tp->write32_rx_mbox = tg3_write_flush_reg32;
10724 }
10725
10726 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10727 tp->read32 = tg3_read_indirect_reg32;
10728 tp->write32 = tg3_write_indirect_reg32;
10729 tp->read32_mbox = tg3_read_indirect_mbox;
10730 tp->write32_mbox = tg3_write_indirect_mbox;
10731 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10732 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10733
10734 iounmap(tp->regs);
10735 tp->regs = NULL;
10736
10737 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10738 pci_cmd &= ~PCI_COMMAND_MEMORY;
10739 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10740 }
10741 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10742 tp->read32_mbox = tg3_read32_mbox_5906;
10743 tp->write32_mbox = tg3_write32_mbox_5906;
10744 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10745 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10746 }
10747
10748 if (tp->write32 == tg3_write_indirect_reg32 ||
10749 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10750 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10751 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10752 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10753
10754 /* Get eeprom hw config before calling tg3_set_power_state().
10755 * In particular, the TG3_FLG2_IS_NIC flag must be
10756 * determined before calling tg3_set_power_state() so that
10757 * we know whether or not to switch out of Vaux power.
10758 * When the flag is set, it means that GPIO1 is used for eeprom
10759 * write protect and also implies that it is a LOM where GPIOs
10760 * are not used to switch power.
10761 */
10762 tg3_get_eeprom_hw_cfg(tp);
10763
10764 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10765 * GPIO1 driven high will bring 5700's external PHY out of reset.
10766 * It is also used as eeprom write protect on LOMs.
10767 */
10768 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10769 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10770 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10771 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10772 GRC_LCLCTRL_GPIO_OUTPUT1);
10773 /* Unused GPIO3 must be driven as output on 5752 because there
10774 * are no pull-up resistors on unused GPIO pins.
10775 */
10776 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10777 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10778
10779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10780 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10781
10782 /* Force the chip into D0. */
10783 err = tg3_set_power_state(tp, PCI_D0);
10784 if (err) {
10785 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10786 pci_name(tp->pdev));
10787 return err;
10788 }
10789
10790 /* 5700 B0 chips do not support checksumming correctly due
10791 * to hardware bugs.
10792 */
10793 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10794 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10795
10796 /* Derive initial jumbo mode from MTU assigned in
10797 * ether_setup() via the alloc_etherdev() call
10798 */
10799 if (tp->dev->mtu > ETH_DATA_LEN &&
10800 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10801 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10802
10803 /* Determine WakeOnLan speed to use. */
10804 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10805 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10806 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10807 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10808 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10809 } else {
10810 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10811 }
10812
10813 /* A few boards don't want Ethernet@WireSpeed phy feature */
10814 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10815 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10816 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10817 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10818 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10819 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10820 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10821
10822 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10823 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10824 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10825 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10826 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10827
10828 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10829 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10830 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10831 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10832 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10833 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10834 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10835 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10836 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10837 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10838 }
10839
10840 tp->coalesce_mode = 0;
10841 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10842 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10843 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10844
10845 /* Initialize MAC MI mode, polling disabled. */
10846 tw32_f(MAC_MI_MODE, tp->mi_mode);
10847 udelay(80);
10848
10849 /* Initialize data/descriptor byte/word swapping. */
10850 val = tr32(GRC_MODE);
10851 val &= GRC_MODE_HOST_STACKUP;
10852 tw32(GRC_MODE, val | tp->grc_mode);
10853
10854 tg3_switch_clocks(tp);
10855
10856 /* Clear this out for sanity. */
10857 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10858
10859 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10860 &pci_state_reg);
10861 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10862 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10863 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10864
10865 if (chiprevid == CHIPREV_ID_5701_A0 ||
10866 chiprevid == CHIPREV_ID_5701_B0 ||
10867 chiprevid == CHIPREV_ID_5701_B2 ||
10868 chiprevid == CHIPREV_ID_5701_B5) {
10869 void __iomem *sram_base;
10870
10871 /* Write some dummy words into the SRAM status block
10872 * area, see if it reads back correctly. If the return
10873 * value is bad, force enable the PCIX workaround.
10874 */
10875 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10876
10877 writel(0x00000000, sram_base);
10878 writel(0x00000000, sram_base + 4);
10879 writel(0xffffffff, sram_base + 4);
10880 if (readl(sram_base) != 0x00000000)
10881 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10882 }
10883 }
10884
10885 udelay(50);
10886 tg3_nvram_init(tp);
10887
10888 grc_misc_cfg = tr32(GRC_MISC_CFG);
10889 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10890
10891 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10892 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10893 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10894 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10895
10896 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10897 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10898 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10899 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10900 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10901 HOSTCC_MODE_CLRTICK_TXBD);
10902
10903 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10904 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10905 tp->misc_host_ctrl);
10906 }
10907
10908 /* these are limited to 10/100 only */
10909 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10910 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10911 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10912 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10913 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10914 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10915 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10916 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10917 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10918 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10919 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10920 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10921 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10922
10923 err = tg3_phy_probe(tp);
10924 if (err) {
10925 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10926 pci_name(tp->pdev), err);
10927 /* ... but do not return immediately ... */
10928 }
10929
10930 tg3_read_partno(tp);
10931 tg3_read_fw_ver(tp);
10932
10933 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10934 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10935 } else {
10936 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10937 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10938 else
10939 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10940 }
10941
10942 /* 5700 {AX,BX} chips have a broken status block link
10943 * change bit implementation, so we must use the
10944 * status register in those cases.
10945 */
10946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10947 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10948 else
10949 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10950
10951 /* The led_ctrl is set during tg3_phy_probe, here we might
10952 * have to force the link status polling mechanism based
10953 * upon subsystem IDs.
10954 */
10955 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10956 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10957 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10958 TG3_FLAG_USE_LINKCHG_REG);
10959 }
10960
10961 /* For all SERDES we poll the MAC status register. */
10962 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10963 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10964 else
10965 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10966
10967 /* All chips before 5787 can get confused if TX buffers
10968 * straddle the 4GB address boundary in some cases.
10969 */
10970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10973 tp->dev->hard_start_xmit = tg3_start_xmit;
10974 else
10975 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10976
10977 tp->rx_offset = 2;
10978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10979 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10980 tp->rx_offset = 0;
10981
10982 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10983
10984 /* Increment the rx prod index on the rx std ring by at most
10985 * 8 for these chips to workaround hw errata.
10986 */
10987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10990 tp->rx_std_max_post = 8;
10991
10992 /* By default, disable wake-on-lan. User can change this
10993 * using ETHTOOL_SWOL.
10994 */
10995 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10996
10997 return err;
10998 }
10999
11000 #ifdef CONFIG_SPARC
11001 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11002 {
11003 struct net_device *dev = tp->dev;
11004 struct pci_dev *pdev = tp->pdev;
11005 struct device_node *dp = pci_device_to_OF_node(pdev);
11006 const unsigned char *addr;
11007 int len;
11008
11009 addr = of_get_property(dp, "local-mac-address", &len);
11010 if (addr && len == 6) {
11011 memcpy(dev->dev_addr, addr, 6);
11012 memcpy(dev->perm_addr, dev->dev_addr, 6);
11013 return 0;
11014 }
11015 return -ENODEV;
11016 }
11017
11018 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11019 {
11020 struct net_device *dev = tp->dev;
11021
11022 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11023 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11024 return 0;
11025 }
11026 #endif
11027
11028 static int __devinit tg3_get_device_address(struct tg3 *tp)
11029 {
11030 struct net_device *dev = tp->dev;
11031 u32 hi, lo, mac_offset;
11032 int addr_ok = 0;
11033
11034 #ifdef CONFIG_SPARC
11035 if (!tg3_get_macaddr_sparc(tp))
11036 return 0;
11037 #endif
11038
11039 mac_offset = 0x7c;
11040 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11041 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11042 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11043 mac_offset = 0xcc;
11044 if (tg3_nvram_lock(tp))
11045 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11046 else
11047 tg3_nvram_unlock(tp);
11048 }
11049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11050 mac_offset = 0x10;
11051
11052 /* First try to get it from MAC address mailbox. */
11053 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11054 if ((hi >> 16) == 0x484b) {
11055 dev->dev_addr[0] = (hi >> 8) & 0xff;
11056 dev->dev_addr[1] = (hi >> 0) & 0xff;
11057
11058 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11059 dev->dev_addr[2] = (lo >> 24) & 0xff;
11060 dev->dev_addr[3] = (lo >> 16) & 0xff;
11061 dev->dev_addr[4] = (lo >> 8) & 0xff;
11062 dev->dev_addr[5] = (lo >> 0) & 0xff;
11063
11064 /* Some old bootcode may report a 0 MAC address in SRAM */
11065 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11066 }
11067 if (!addr_ok) {
11068 /* Next, try NVRAM. */
11069 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11070 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11071 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11072 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11073 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11074 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11075 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11076 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11077 }
11078 /* Finally just fetch it out of the MAC control regs. */
11079 else {
11080 hi = tr32(MAC_ADDR_0_HIGH);
11081 lo = tr32(MAC_ADDR_0_LOW);
11082
11083 dev->dev_addr[5] = lo & 0xff;
11084 dev->dev_addr[4] = (lo >> 8) & 0xff;
11085 dev->dev_addr[3] = (lo >> 16) & 0xff;
11086 dev->dev_addr[2] = (lo >> 24) & 0xff;
11087 dev->dev_addr[1] = hi & 0xff;
11088 dev->dev_addr[0] = (hi >> 8) & 0xff;
11089 }
11090 }
11091
11092 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11093 #ifdef CONFIG_SPARC64
11094 if (!tg3_get_default_macaddr_sparc(tp))
11095 return 0;
11096 #endif
11097 return -EINVAL;
11098 }
11099 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11100 return 0;
11101 }
11102
11103 #define BOUNDARY_SINGLE_CACHELINE 1
11104 #define BOUNDARY_MULTI_CACHELINE 2
11105
11106 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11107 {
11108 int cacheline_size;
11109 u8 byte;
11110 int goal;
11111
11112 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11113 if (byte == 0)
11114 cacheline_size = 1024;
11115 else
11116 cacheline_size = (int) byte * 4;
11117
11118 /* On 5703 and later chips, the boundary bits have no
11119 * effect.
11120 */
11121 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11122 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11123 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11124 goto out;
11125
11126 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11127 goal = BOUNDARY_MULTI_CACHELINE;
11128 #else
11129 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11130 goal = BOUNDARY_SINGLE_CACHELINE;
11131 #else
11132 goal = 0;
11133 #endif
11134 #endif
11135
11136 if (!goal)
11137 goto out;
11138
11139 /* PCI controllers on most RISC systems tend to disconnect
11140 * when a device tries to burst across a cache-line boundary.
11141 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11142 *
11143 * Unfortunately, for PCI-E there are only limited
11144 * write-side controls for this, and thus for reads
11145 * we will still get the disconnects. We'll also waste
11146 * these PCI cycles for both read and write for chips
11147 * other than 5700 and 5701 which do not implement the
11148 * boundary bits.
11149 */
11150 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11151 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11152 switch (cacheline_size) {
11153 case 16:
11154 case 32:
11155 case 64:
11156 case 128:
11157 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11158 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11159 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11160 } else {
11161 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11162 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11163 }
11164 break;
11165
11166 case 256:
11167 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11168 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11169 break;
11170
11171 default:
11172 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11173 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11174 break;
11175 };
11176 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11177 switch (cacheline_size) {
11178 case 16:
11179 case 32:
11180 case 64:
11181 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11182 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11183 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11184 break;
11185 }
11186 /* fallthrough */
11187 case 128:
11188 default:
11189 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11190 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11191 break;
11192 };
11193 } else {
11194 switch (cacheline_size) {
11195 case 16:
11196 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11197 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11198 DMA_RWCTRL_WRITE_BNDRY_16);
11199 break;
11200 }
11201 /* fallthrough */
11202 case 32:
11203 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11204 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11205 DMA_RWCTRL_WRITE_BNDRY_32);
11206 break;
11207 }
11208 /* fallthrough */
11209 case 64:
11210 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11211 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11212 DMA_RWCTRL_WRITE_BNDRY_64);
11213 break;
11214 }
11215 /* fallthrough */
11216 case 128:
11217 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11218 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11219 DMA_RWCTRL_WRITE_BNDRY_128);
11220 break;
11221 }
11222 /* fallthrough */
11223 case 256:
11224 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11225 DMA_RWCTRL_WRITE_BNDRY_256);
11226 break;
11227 case 512:
11228 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11229 DMA_RWCTRL_WRITE_BNDRY_512);
11230 break;
11231 case 1024:
11232 default:
11233 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11234 DMA_RWCTRL_WRITE_BNDRY_1024);
11235 break;
11236 };
11237 }
11238
11239 out:
11240 return val;
11241 }
11242
11243 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11244 {
11245 struct tg3_internal_buffer_desc test_desc;
11246 u32 sram_dma_descs;
11247 int i, ret;
11248
11249 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11250
11251 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11252 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11253 tw32(RDMAC_STATUS, 0);
11254 tw32(WDMAC_STATUS, 0);
11255
11256 tw32(BUFMGR_MODE, 0);
11257 tw32(FTQ_RESET, 0);
11258
11259 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11260 test_desc.addr_lo = buf_dma & 0xffffffff;
11261 test_desc.nic_mbuf = 0x00002100;
11262 test_desc.len = size;
11263
11264 /*
11265 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11266 * the *second* time the tg3 driver was getting loaded after an
11267 * initial scan.
11268 *
11269 * Broadcom tells me:
11270 * ...the DMA engine is connected to the GRC block and a DMA
11271 * reset may affect the GRC block in some unpredictable way...
11272 * The behavior of resets to individual blocks has not been tested.
11273 *
11274 * Broadcom noted the GRC reset will also reset all sub-components.
11275 */
11276 if (to_device) {
11277 test_desc.cqid_sqid = (13 << 8) | 2;
11278
11279 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11280 udelay(40);
11281 } else {
11282 test_desc.cqid_sqid = (16 << 8) | 7;
11283
11284 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11285 udelay(40);
11286 }
11287 test_desc.flags = 0x00000005;
11288
11289 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11290 u32 val;
11291
11292 val = *(((u32 *)&test_desc) + i);
11293 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11294 sram_dma_descs + (i * sizeof(u32)));
11295 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11296 }
11297 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11298
11299 if (to_device) {
11300 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11301 } else {
11302 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11303 }
11304
11305 ret = -ENODEV;
11306 for (i = 0; i < 40; i++) {
11307 u32 val;
11308
11309 if (to_device)
11310 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11311 else
11312 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11313 if ((val & 0xffff) == sram_dma_descs) {
11314 ret = 0;
11315 break;
11316 }
11317
11318 udelay(100);
11319 }
11320
11321 return ret;
11322 }
11323
11324 #define TEST_BUFFER_SIZE 0x2000
11325
11326 static int __devinit tg3_test_dma(struct tg3 *tp)
11327 {
11328 dma_addr_t buf_dma;
11329 u32 *buf, saved_dma_rwctrl;
11330 int ret;
11331
11332 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11333 if (!buf) {
11334 ret = -ENOMEM;
11335 goto out_nofree;
11336 }
11337
11338 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11339 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11340
11341 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11342
11343 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11344 /* DMA read watermark not used on PCIE */
11345 tp->dma_rwctrl |= 0x00180000;
11346 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11349 tp->dma_rwctrl |= 0x003f0000;
11350 else
11351 tp->dma_rwctrl |= 0x003f000f;
11352 } else {
11353 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11354 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11355 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11356 u32 read_water = 0x7;
11357
11358 /* If the 5704 is behind the EPB bridge, we can
11359 * do the less restrictive ONE_DMA workaround for
11360 * better performance.
11361 */
11362 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11364 tp->dma_rwctrl |= 0x8000;
11365 else if (ccval == 0x6 || ccval == 0x7)
11366 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11367
11368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11369 read_water = 4;
11370 /* Set bit 23 to enable PCIX hw bug fix */
11371 tp->dma_rwctrl |=
11372 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11373 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11374 (1 << 23);
11375 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11376 /* 5780 always in PCIX mode */
11377 tp->dma_rwctrl |= 0x00144000;
11378 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11379 /* 5714 always in PCIX mode */
11380 tp->dma_rwctrl |= 0x00148000;
11381 } else {
11382 tp->dma_rwctrl |= 0x001b000f;
11383 }
11384 }
11385
11386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11387 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11388 tp->dma_rwctrl &= 0xfffffff0;
11389
11390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11391 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11392 /* Remove this if it causes problems for some boards. */
11393 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11394
11395 /* On 5700/5701 chips, we need to set this bit.
11396 * Otherwise the chip will issue cacheline transactions
11397 * to streamable DMA memory with not all the byte
11398 * enables turned on. This is an error on several
11399 * RISC PCI controllers, in particular sparc64.
11400 *
11401 * On 5703/5704 chips, this bit has been reassigned
11402 * a different meaning. In particular, it is used
11403 * on those chips to enable a PCI-X workaround.
11404 */
11405 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11406 }
11407
11408 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11409
11410 #if 0
11411 /* Unneeded, already done by tg3_get_invariants. */
11412 tg3_switch_clocks(tp);
11413 #endif
11414
11415 ret = 0;
11416 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11417 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11418 goto out;
11419
11420 /* It is best to perform DMA test with maximum write burst size
11421 * to expose the 5700/5701 write DMA bug.
11422 */
11423 saved_dma_rwctrl = tp->dma_rwctrl;
11424 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11425 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11426
11427 while (1) {
11428 u32 *p = buf, i;
11429
11430 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11431 p[i] = i;
11432
11433 /* Send the buffer to the chip. */
11434 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11435 if (ret) {
11436 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11437 break;
11438 }
11439
11440 #if 0
11441 /* validate data reached card RAM correctly. */
11442 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11443 u32 val;
11444 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11445 if (le32_to_cpu(val) != p[i]) {
11446 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11447 /* ret = -ENODEV here? */
11448 }
11449 p[i] = 0;
11450 }
11451 #endif
11452 /* Now read it back. */
11453 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11454 if (ret) {
11455 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11456
11457 break;
11458 }
11459
11460 /* Verify it. */
11461 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11462 if (p[i] == i)
11463 continue;
11464
11465 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11466 DMA_RWCTRL_WRITE_BNDRY_16) {
11467 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11468 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11469 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11470 break;
11471 } else {
11472 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11473 ret = -ENODEV;
11474 goto out;
11475 }
11476 }
11477
11478 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11479 /* Success. */
11480 ret = 0;
11481 break;
11482 }
11483 }
11484 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11485 DMA_RWCTRL_WRITE_BNDRY_16) {
11486 static struct pci_device_id dma_wait_state_chipsets[] = {
11487 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11488 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11489 { },
11490 };
11491
11492 /* DMA test passed without adjusting DMA boundary,
11493 * now look for chipsets that are known to expose the
11494 * DMA bug without failing the test.
11495 */
11496 if (pci_dev_present(dma_wait_state_chipsets)) {
11497 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11498 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11499 }
11500 else
11501 /* Safe to use the calculated DMA boundary. */
11502 tp->dma_rwctrl = saved_dma_rwctrl;
11503
11504 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11505 }
11506
11507 out:
11508 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11509 out_nofree:
11510 return ret;
11511 }
11512
11513 static void __devinit tg3_init_link_config(struct tg3 *tp)
11514 {
11515 tp->link_config.advertising =
11516 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11517 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11518 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11519 ADVERTISED_Autoneg | ADVERTISED_MII);
11520 tp->link_config.speed = SPEED_INVALID;
11521 tp->link_config.duplex = DUPLEX_INVALID;
11522 tp->link_config.autoneg = AUTONEG_ENABLE;
11523 tp->link_config.active_speed = SPEED_INVALID;
11524 tp->link_config.active_duplex = DUPLEX_INVALID;
11525 tp->link_config.phy_is_low_power = 0;
11526 tp->link_config.orig_speed = SPEED_INVALID;
11527 tp->link_config.orig_duplex = DUPLEX_INVALID;
11528 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11529 }
11530
11531 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11532 {
11533 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11534 tp->bufmgr_config.mbuf_read_dma_low_water =
11535 DEFAULT_MB_RDMA_LOW_WATER_5705;
11536 tp->bufmgr_config.mbuf_mac_rx_low_water =
11537 DEFAULT_MB_MACRX_LOW_WATER_5705;
11538 tp->bufmgr_config.mbuf_high_water =
11539 DEFAULT_MB_HIGH_WATER_5705;
11540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11541 tp->bufmgr_config.mbuf_mac_rx_low_water =
11542 DEFAULT_MB_MACRX_LOW_WATER_5906;
11543 tp->bufmgr_config.mbuf_high_water =
11544 DEFAULT_MB_HIGH_WATER_5906;
11545 }
11546
11547 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11548 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11549 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11550 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11551 tp->bufmgr_config.mbuf_high_water_jumbo =
11552 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11553 } else {
11554 tp->bufmgr_config.mbuf_read_dma_low_water =
11555 DEFAULT_MB_RDMA_LOW_WATER;
11556 tp->bufmgr_config.mbuf_mac_rx_low_water =
11557 DEFAULT_MB_MACRX_LOW_WATER;
11558 tp->bufmgr_config.mbuf_high_water =
11559 DEFAULT_MB_HIGH_WATER;
11560
11561 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11562 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11563 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11564 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11565 tp->bufmgr_config.mbuf_high_water_jumbo =
11566 DEFAULT_MB_HIGH_WATER_JUMBO;
11567 }
11568
11569 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11570 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11571 }
11572
11573 static char * __devinit tg3_phy_string(struct tg3 *tp)
11574 {
11575 switch (tp->phy_id & PHY_ID_MASK) {
11576 case PHY_ID_BCM5400: return "5400";
11577 case PHY_ID_BCM5401: return "5401";
11578 case PHY_ID_BCM5411: return "5411";
11579 case PHY_ID_BCM5701: return "5701";
11580 case PHY_ID_BCM5703: return "5703";
11581 case PHY_ID_BCM5704: return "5704";
11582 case PHY_ID_BCM5705: return "5705";
11583 case PHY_ID_BCM5750: return "5750";
11584 case PHY_ID_BCM5752: return "5752";
11585 case PHY_ID_BCM5714: return "5714";
11586 case PHY_ID_BCM5780: return "5780";
11587 case PHY_ID_BCM5755: return "5755";
11588 case PHY_ID_BCM5787: return "5787";
11589 case PHY_ID_BCM5756: return "5722/5756";
11590 case PHY_ID_BCM5906: return "5906";
11591 case PHY_ID_BCM8002: return "8002/serdes";
11592 case 0: return "serdes";
11593 default: return "unknown";
11594 };
11595 }
11596
11597 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11598 {
11599 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11600 strcpy(str, "PCI Express");
11601 return str;
11602 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11603 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11604
11605 strcpy(str, "PCIX:");
11606
11607 if ((clock_ctrl == 7) ||
11608 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11609 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11610 strcat(str, "133MHz");
11611 else if (clock_ctrl == 0)
11612 strcat(str, "33MHz");
11613 else if (clock_ctrl == 2)
11614 strcat(str, "50MHz");
11615 else if (clock_ctrl == 4)
11616 strcat(str, "66MHz");
11617 else if (clock_ctrl == 6)
11618 strcat(str, "100MHz");
11619 } else {
11620 strcpy(str, "PCI:");
11621 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11622 strcat(str, "66MHz");
11623 else
11624 strcat(str, "33MHz");
11625 }
11626 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11627 strcat(str, ":32-bit");
11628 else
11629 strcat(str, ":64-bit");
11630 return str;
11631 }
11632
11633 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11634 {
11635 struct pci_dev *peer;
11636 unsigned int func, devnr = tp->pdev->devfn & ~7;
11637
11638 for (func = 0; func < 8; func++) {
11639 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11640 if (peer && peer != tp->pdev)
11641 break;
11642 pci_dev_put(peer);
11643 }
11644 /* 5704 can be configured in single-port mode, set peer to
11645 * tp->pdev in that case.
11646 */
11647 if (!peer) {
11648 peer = tp->pdev;
11649 return peer;
11650 }
11651
11652 /*
11653 * We don't need to keep the refcount elevated; there's no way
11654 * to remove one half of this device without removing the other
11655 */
11656 pci_dev_put(peer);
11657
11658 return peer;
11659 }
11660
11661 static void __devinit tg3_init_coal(struct tg3 *tp)
11662 {
11663 struct ethtool_coalesce *ec = &tp->coal;
11664
11665 memset(ec, 0, sizeof(*ec));
11666 ec->cmd = ETHTOOL_GCOALESCE;
11667 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11668 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11669 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11670 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11671 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11672 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11673 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11674 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11675 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11676
11677 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11678 HOSTCC_MODE_CLRTICK_TXBD)) {
11679 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11680 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11681 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11682 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11683 }
11684
11685 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11686 ec->rx_coalesce_usecs_irq = 0;
11687 ec->tx_coalesce_usecs_irq = 0;
11688 ec->stats_block_coalesce_usecs = 0;
11689 }
11690 }
11691
11692 static int __devinit tg3_init_one(struct pci_dev *pdev,
11693 const struct pci_device_id *ent)
11694 {
11695 static int tg3_version_printed = 0;
11696 unsigned long tg3reg_base, tg3reg_len;
11697 struct net_device *dev;
11698 struct tg3 *tp;
11699 int i, err, pm_cap;
11700 char str[40];
11701 u64 dma_mask, persist_dma_mask;
11702
11703 if (tg3_version_printed++ == 0)
11704 printk(KERN_INFO "%s", version);
11705
11706 err = pci_enable_device(pdev);
11707 if (err) {
11708 printk(KERN_ERR PFX "Cannot enable PCI device, "
11709 "aborting.\n");
11710 return err;
11711 }
11712
11713 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11714 printk(KERN_ERR PFX "Cannot find proper PCI device "
11715 "base address, aborting.\n");
11716 err = -ENODEV;
11717 goto err_out_disable_pdev;
11718 }
11719
11720 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11721 if (err) {
11722 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11723 "aborting.\n");
11724 goto err_out_disable_pdev;
11725 }
11726
11727 pci_set_master(pdev);
11728
11729 /* Find power-management capability. */
11730 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11731 if (pm_cap == 0) {
11732 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11733 "aborting.\n");
11734 err = -EIO;
11735 goto err_out_free_res;
11736 }
11737
11738 tg3reg_base = pci_resource_start(pdev, 0);
11739 tg3reg_len = pci_resource_len(pdev, 0);
11740
11741 dev = alloc_etherdev(sizeof(*tp));
11742 if (!dev) {
11743 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11744 err = -ENOMEM;
11745 goto err_out_free_res;
11746 }
11747
11748 SET_MODULE_OWNER(dev);
11749 SET_NETDEV_DEV(dev, &pdev->dev);
11750
11751 #if TG3_VLAN_TAG_USED
11752 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11753 dev->vlan_rx_register = tg3_vlan_rx_register;
11754 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11755 #endif
11756
11757 tp = netdev_priv(dev);
11758 tp->pdev = pdev;
11759 tp->dev = dev;
11760 tp->pm_cap = pm_cap;
11761 tp->mac_mode = TG3_DEF_MAC_MODE;
11762 tp->rx_mode = TG3_DEF_RX_MODE;
11763 tp->tx_mode = TG3_DEF_TX_MODE;
11764 tp->mi_mode = MAC_MI_MODE_BASE;
11765 if (tg3_debug > 0)
11766 tp->msg_enable = tg3_debug;
11767 else
11768 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11769
11770 /* The word/byte swap controls here control register access byte
11771 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11772 * setting below.
11773 */
11774 tp->misc_host_ctrl =
11775 MISC_HOST_CTRL_MASK_PCI_INT |
11776 MISC_HOST_CTRL_WORD_SWAP |
11777 MISC_HOST_CTRL_INDIR_ACCESS |
11778 MISC_HOST_CTRL_PCISTATE_RW;
11779
11780 /* The NONFRM (non-frame) byte/word swap controls take effect
11781 * on descriptor entries, anything which isn't packet data.
11782 *
11783 * The StrongARM chips on the board (one for tx, one for rx)
11784 * are running in big-endian mode.
11785 */
11786 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11787 GRC_MODE_WSWAP_NONFRM_DATA);
11788 #ifdef __BIG_ENDIAN
11789 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11790 #endif
11791 spin_lock_init(&tp->lock);
11792 spin_lock_init(&tp->indirect_lock);
11793 INIT_WORK(&tp->reset_task, tg3_reset_task);
11794
11795 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11796 if (tp->regs == 0UL) {
11797 printk(KERN_ERR PFX "Cannot map device registers, "
11798 "aborting.\n");
11799 err = -ENOMEM;
11800 goto err_out_free_dev;
11801 }
11802
11803 tg3_init_link_config(tp);
11804
11805 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11806 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11807 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11808
11809 dev->open = tg3_open;
11810 dev->stop = tg3_close;
11811 dev->get_stats = tg3_get_stats;
11812 dev->set_multicast_list = tg3_set_rx_mode;
11813 dev->set_mac_address = tg3_set_mac_addr;
11814 dev->do_ioctl = tg3_ioctl;
11815 dev->tx_timeout = tg3_tx_timeout;
11816 dev->poll = tg3_poll;
11817 dev->ethtool_ops = &tg3_ethtool_ops;
11818 dev->weight = 64;
11819 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11820 dev->change_mtu = tg3_change_mtu;
11821 dev->irq = pdev->irq;
11822 #ifdef CONFIG_NET_POLL_CONTROLLER
11823 dev->poll_controller = tg3_poll_controller;
11824 #endif
11825
11826 err = tg3_get_invariants(tp);
11827 if (err) {
11828 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11829 "aborting.\n");
11830 goto err_out_iounmap;
11831 }
11832
11833 /* The EPB bridge inside 5714, 5715, and 5780 and any
11834 * device behind the EPB cannot support DMA addresses > 40-bit.
11835 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11836 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11837 * do DMA address check in tg3_start_xmit().
11838 */
11839 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11840 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11841 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11842 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11843 #ifdef CONFIG_HIGHMEM
11844 dma_mask = DMA_64BIT_MASK;
11845 #endif
11846 } else
11847 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11848
11849 /* Configure DMA attributes. */
11850 if (dma_mask > DMA_32BIT_MASK) {
11851 err = pci_set_dma_mask(pdev, dma_mask);
11852 if (!err) {
11853 dev->features |= NETIF_F_HIGHDMA;
11854 err = pci_set_consistent_dma_mask(pdev,
11855 persist_dma_mask);
11856 if (err < 0) {
11857 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11858 "DMA for consistent allocations\n");
11859 goto err_out_iounmap;
11860 }
11861 }
11862 }
11863 if (err || dma_mask == DMA_32BIT_MASK) {
11864 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11865 if (err) {
11866 printk(KERN_ERR PFX "No usable DMA configuration, "
11867 "aborting.\n");
11868 goto err_out_iounmap;
11869 }
11870 }
11871
11872 tg3_init_bufmgr_config(tp);
11873
11874 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11875 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11876 }
11877 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11878 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11879 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11880 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11881 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11882 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11883 } else {
11884 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11885 }
11886
11887 /* TSO is on by default on chips that support hardware TSO.
11888 * Firmware TSO on older chips gives lower performance, so it
11889 * is off by default, but can be enabled using ethtool.
11890 */
11891 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11892 dev->features |= NETIF_F_TSO;
11893 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11894 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11895 dev->features |= NETIF_F_TSO6;
11896 }
11897
11898
11899 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11900 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11901 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11902 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11903 tp->rx_pending = 63;
11904 }
11905
11906 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11907 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11908 tp->pdev_peer = tg3_find_peer(tp);
11909
11910 err = tg3_get_device_address(tp);
11911 if (err) {
11912 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11913 "aborting.\n");
11914 goto err_out_iounmap;
11915 }
11916
11917 /*
11918 * Reset chip in case UNDI or EFI driver did not shutdown
11919 * DMA self test will enable WDMAC and we'll see (spurious)
11920 * pending DMA on the PCI bus at that point.
11921 */
11922 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11923 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11924 pci_save_state(tp->pdev);
11925 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11926 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11927 }
11928
11929 err = tg3_test_dma(tp);
11930 if (err) {
11931 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11932 goto err_out_iounmap;
11933 }
11934
11935 /* Tigon3 can do ipv4 only... and some chips have buggy
11936 * checksumming.
11937 */
11938 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11939 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11940 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11941 dev->features |= NETIF_F_HW_CSUM;
11942 else
11943 dev->features |= NETIF_F_IP_CSUM;
11944 dev->features |= NETIF_F_SG;
11945 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11946 } else
11947 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11948
11949 /* flow control autonegotiation is default behavior */
11950 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11951
11952 tg3_init_coal(tp);
11953
11954 /* Now that we have fully setup the chip, save away a snapshot
11955 * of the PCI config space. We need to restore this after
11956 * GRC_MISC_CFG core clock resets and some resume events.
11957 */
11958 pci_save_state(tp->pdev);
11959
11960 pci_set_drvdata(pdev, dev);
11961
11962 err = register_netdev(dev);
11963 if (err) {
11964 printk(KERN_ERR PFX "Cannot register net device, "
11965 "aborting.\n");
11966 goto err_out_iounmap;
11967 }
11968
11969 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11970 dev->name,
11971 tp->board_part_number,
11972 tp->pci_chip_rev_id,
11973 tg3_phy_string(tp),
11974 tg3_bus_string(tp, str),
11975 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11976 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11977 "10/100/1000Base-T")));
11978
11979 for (i = 0; i < 6; i++)
11980 printk("%2.2x%c", dev->dev_addr[i],
11981 i == 5 ? '\n' : ':');
11982
11983 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11984 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11985 dev->name,
11986 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11987 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11988 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11989 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11990 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11991 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11992 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11993 dev->name, tp->dma_rwctrl,
11994 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11995 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11996
11997 return 0;
11998
11999 err_out_iounmap:
12000 if (tp->regs) {
12001 iounmap(tp->regs);
12002 tp->regs = NULL;
12003 }
12004
12005 err_out_free_dev:
12006 free_netdev(dev);
12007
12008 err_out_free_res:
12009 pci_release_regions(pdev);
12010
12011 err_out_disable_pdev:
12012 pci_disable_device(pdev);
12013 pci_set_drvdata(pdev, NULL);
12014 return err;
12015 }
12016
12017 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12018 {
12019 struct net_device *dev = pci_get_drvdata(pdev);
12020
12021 if (dev) {
12022 struct tg3 *tp = netdev_priv(dev);
12023
12024 flush_scheduled_work();
12025 unregister_netdev(dev);
12026 if (tp->regs) {
12027 iounmap(tp->regs);
12028 tp->regs = NULL;
12029 }
12030 free_netdev(dev);
12031 pci_release_regions(pdev);
12032 pci_disable_device(pdev);
12033 pci_set_drvdata(pdev, NULL);
12034 }
12035 }
12036
12037 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12038 {
12039 struct net_device *dev = pci_get_drvdata(pdev);
12040 struct tg3 *tp = netdev_priv(dev);
12041 int err;
12042
12043 if (!netif_running(dev))
12044 return 0;
12045
12046 flush_scheduled_work();
12047 tg3_netif_stop(tp);
12048
12049 del_timer_sync(&tp->timer);
12050
12051 tg3_full_lock(tp, 1);
12052 tg3_disable_ints(tp);
12053 tg3_full_unlock(tp);
12054
12055 netif_device_detach(dev);
12056
12057 tg3_full_lock(tp, 0);
12058 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12059 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12060 tg3_full_unlock(tp);
12061
12062 /* Save MSI address and data for resume. */
12063 pci_save_state(pdev);
12064
12065 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12066 if (err) {
12067 tg3_full_lock(tp, 0);
12068
12069 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12070 if (tg3_restart_hw(tp, 1))
12071 goto out;
12072
12073 tp->timer.expires = jiffies + tp->timer_offset;
12074 add_timer(&tp->timer);
12075
12076 netif_device_attach(dev);
12077 tg3_netif_start(tp);
12078
12079 out:
12080 tg3_full_unlock(tp);
12081 }
12082
12083 return err;
12084 }
12085
12086 static int tg3_resume(struct pci_dev *pdev)
12087 {
12088 struct net_device *dev = pci_get_drvdata(pdev);
12089 struct tg3 *tp = netdev_priv(dev);
12090 int err;
12091
12092 if (!netif_running(dev))
12093 return 0;
12094
12095 pci_restore_state(tp->pdev);
12096
12097 err = tg3_set_power_state(tp, PCI_D0);
12098 if (err)
12099 return err;
12100
12101 netif_device_attach(dev);
12102
12103 tg3_full_lock(tp, 0);
12104
12105 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12106 err = tg3_restart_hw(tp, 1);
12107 if (err)
12108 goto out;
12109
12110 tp->timer.expires = jiffies + tp->timer_offset;
12111 add_timer(&tp->timer);
12112
12113 tg3_netif_start(tp);
12114
12115 out:
12116 tg3_full_unlock(tp);
12117
12118 return err;
12119 }
12120
12121 static struct pci_driver tg3_driver = {
12122 .name = DRV_MODULE_NAME,
12123 .id_table = tg3_pci_tbl,
12124 .probe = tg3_init_one,
12125 .remove = __devexit_p(tg3_remove_one),
12126 .suspend = tg3_suspend,
12127 .resume = tg3_resume
12128 };
12129
12130 static int __init tg3_init(void)
12131 {
12132 return pci_register_driver(&tg3_driver);
12133 }
12134
12135 static void __exit tg3_cleanup(void)
12136 {
12137 pci_unregister_driver(&tg3_driver);
12138 }
12139
12140 module_init(tg3_init);
12141 module_exit(tg3_cleanup);
linux v2.6.22.y-op