2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
36 #include <linux/init.h>
42 #include "mthca_dev.h"
43 #include "mthca_cmd.h"
44 #include "mthca_memfree.h"
47 MTHCA_MAX_DIRECT_QP_SIZE
= 4 * PAGE_SIZE
,
48 MTHCA_ACK_REQ_FREQ
= 10,
49 MTHCA_FLIGHT_LIMIT
= 9,
50 MTHCA_UD_HEADER_SIZE
= 72, /* largest UD header possible */
51 MTHCA_INLINE_HEADER_SIZE
= 4, /* data segment overhead for inline */
52 MTHCA_INLINE_CHUNK_SIZE
= 16 /* inline data segment chunk */
56 MTHCA_QP_STATE_RST
= 0,
57 MTHCA_QP_STATE_INIT
= 1,
58 MTHCA_QP_STATE_RTR
= 2,
59 MTHCA_QP_STATE_RTS
= 3,
60 MTHCA_QP_STATE_SQE
= 4,
61 MTHCA_QP_STATE_SQD
= 5,
62 MTHCA_QP_STATE_ERR
= 6,
63 MTHCA_QP_STATE_DRAINING
= 7
75 MTHCA_QP_PM_MIGRATED
= 0x3,
76 MTHCA_QP_PM_ARMED
= 0x0,
77 MTHCA_QP_PM_REARM
= 0x1
81 /* qp_context flags */
82 MTHCA_QP_BIT_DE
= 1 << 8,
84 MTHCA_QP_BIT_SRE
= 1 << 15,
85 MTHCA_QP_BIT_SWE
= 1 << 14,
86 MTHCA_QP_BIT_SAE
= 1 << 13,
87 MTHCA_QP_BIT_SIC
= 1 << 4,
88 MTHCA_QP_BIT_SSC
= 1 << 3,
90 MTHCA_QP_BIT_RRE
= 1 << 15,
91 MTHCA_QP_BIT_RWE
= 1 << 14,
92 MTHCA_QP_BIT_RAE
= 1 << 13,
93 MTHCA_QP_BIT_RIC
= 1 << 4,
94 MTHCA_QP_BIT_RSC
= 1 << 3
97 struct mthca_qp_path
{
106 u32 sl_tclass_flowlabel
;
108 } __attribute__((packed
));
110 struct mthca_qp_context
{
112 u32 tavor_sched_queue
; /* Reserved on Arbel */
114 u8 rq_size_stride
; /* Reserved on Tavor */
115 u8 sq_size_stride
; /* Reserved on Tavor */
116 u8 rlkey_arbel_sched_queue
; /* Reserved on Tavor */
121 struct mthca_qp_path pri_path
;
122 struct mthca_qp_path alt_path
;
131 u32 snd_wqe_base_l
; /* Next send WQE on Tavor */
132 u32 snd_db_index
; /* (debugging only entries) */
139 u32 rcv_wqe_base_l
; /* Next recv WQE on Tavor */
140 u32 rcv_db_index
; /* (debugging only entries) */
144 u16 rq_wqe_counter
; /* reserved on Tavor */
145 u16 sq_wqe_counter
; /* reserved on Tavor */
147 } __attribute__((packed
));
149 struct mthca_qp_param
{
152 struct mthca_qp_context context
;
154 } __attribute__((packed
));
157 MTHCA_QP_OPTPAR_ALT_ADDR_PATH
= 1 << 0,
158 MTHCA_QP_OPTPAR_RRE
= 1 << 1,
159 MTHCA_QP_OPTPAR_RAE
= 1 << 2,
160 MTHCA_QP_OPTPAR_RWE
= 1 << 3,
161 MTHCA_QP_OPTPAR_PKEY_INDEX
= 1 << 4,
162 MTHCA_QP_OPTPAR_Q_KEY
= 1 << 5,
163 MTHCA_QP_OPTPAR_RNR_TIMEOUT
= 1 << 6,
164 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
= 1 << 7,
165 MTHCA_QP_OPTPAR_SRA_MAX
= 1 << 8,
166 MTHCA_QP_OPTPAR_RRA_MAX
= 1 << 9,
167 MTHCA_QP_OPTPAR_PM_STATE
= 1 << 10,
168 MTHCA_QP_OPTPAR_PORT_NUM
= 1 << 11,
169 MTHCA_QP_OPTPAR_RETRY_COUNT
= 1 << 12,
170 MTHCA_QP_OPTPAR_ALT_RNR_RETRY
= 1 << 13,
171 MTHCA_QP_OPTPAR_ACK_TIMEOUT
= 1 << 14,
172 MTHCA_QP_OPTPAR_RNR_RETRY
= 1 << 15,
173 MTHCA_QP_OPTPAR_SCHED_QUEUE
= 1 << 16
177 MTHCA_NEXT_DBD
= 1 << 7,
178 MTHCA_NEXT_FENCE
= 1 << 6,
179 MTHCA_NEXT_CQ_UPDATE
= 1 << 3,
180 MTHCA_NEXT_EVENT_GEN
= 1 << 2,
181 MTHCA_NEXT_SOLICIT
= 1 << 1,
183 MTHCA_MLX_VL15
= 1 << 17,
184 MTHCA_MLX_SLR
= 1 << 16
188 MTHCA_INVAL_LKEY
= 0x100
191 struct mthca_next_seg
{
192 u32 nda_op
; /* [31:6] next WQE [4:0] next opcode */
193 u32 ee_nds
; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
194 u32 flags
; /* [3] CQ [2] Event [1] Solicit */
195 u32 imm
; /* immediate data */
198 struct mthca_tavor_ud_seg
{
208 struct mthca_arbel_ud_seg
{
215 struct mthca_bind_seg
{
216 u32 flags
; /* [31] Atomic [30] rem write [29] rem read */
224 struct mthca_raddr_seg
{
230 struct mthca_atomic_seg
{
235 struct mthca_data_seg
{
241 struct mthca_mlx_seg
{
244 u32 flags
; /* [17] VL15 [16] SLR [14:12] static rate
245 [11:8] SL [3] C [2] E */
250 static const u8 mthca_opcode
[] = {
251 [IB_WR_SEND
] = MTHCA_OPCODE_SEND
,
252 [IB_WR_SEND_WITH_IMM
] = MTHCA_OPCODE_SEND_IMM
,
253 [IB_WR_RDMA_WRITE
] = MTHCA_OPCODE_RDMA_WRITE
,
254 [IB_WR_RDMA_WRITE_WITH_IMM
] = MTHCA_OPCODE_RDMA_WRITE_IMM
,
255 [IB_WR_RDMA_READ
] = MTHCA_OPCODE_RDMA_READ
,
256 [IB_WR_ATOMIC_CMP_AND_SWP
] = MTHCA_OPCODE_ATOMIC_CS
,
257 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MTHCA_OPCODE_ATOMIC_FA
,
260 static int is_sqp(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
262 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
263 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 3;
266 static int is_qp0(struct mthca_dev
*dev
, struct mthca_qp
*qp
)
268 return qp
->qpn
>= dev
->qp_table
.sqp_start
&&
269 qp
->qpn
<= dev
->qp_table
.sqp_start
+ 1;
272 static void *get_recv_wqe(struct mthca_qp
*qp
, int n
)
275 return qp
->queue
.direct
.buf
+ (n
<< qp
->rq
.wqe_shift
);
277 return qp
->queue
.page_list
[(n
<< qp
->rq
.wqe_shift
) >> PAGE_SHIFT
].buf
+
278 ((n
<< qp
->rq
.wqe_shift
) & (PAGE_SIZE
- 1));
281 static void *get_send_wqe(struct mthca_qp
*qp
, int n
)
284 return qp
->queue
.direct
.buf
+ qp
->send_wqe_offset
+
285 (n
<< qp
->sq
.wqe_shift
);
287 return qp
->queue
.page_list
[(qp
->send_wqe_offset
+
288 (n
<< qp
->sq
.wqe_shift
)) >>
290 ((qp
->send_wqe_offset
+ (n
<< qp
->sq
.wqe_shift
)) &
294 void mthca_qp_event(struct mthca_dev
*dev
, u32 qpn
,
295 enum ib_event_type event_type
)
298 struct ib_event event
;
300 spin_lock(&dev
->qp_table
.lock
);
301 qp
= mthca_array_get(&dev
->qp_table
.qp
, qpn
& (dev
->limits
.num_qps
- 1));
303 atomic_inc(&qp
->refcount
);
304 spin_unlock(&dev
->qp_table
.lock
);
307 mthca_warn(dev
, "Async event for bogus QP %08x\n", qpn
);
311 event
.device
= &dev
->ib_dev
;
312 event
.event
= event_type
;
313 event
.element
.qp
= &qp
->ibqp
;
314 if (qp
->ibqp
.event_handler
)
315 qp
->ibqp
.event_handler(&event
, qp
->ibqp
.qp_context
);
317 if (atomic_dec_and_test(&qp
->refcount
))
321 static int to_mthca_state(enum ib_qp_state ib_state
)
324 case IB_QPS_RESET
: return MTHCA_QP_STATE_RST
;
325 case IB_QPS_INIT
: return MTHCA_QP_STATE_INIT
;
326 case IB_QPS_RTR
: return MTHCA_QP_STATE_RTR
;
327 case IB_QPS_RTS
: return MTHCA_QP_STATE_RTS
;
328 case IB_QPS_SQD
: return MTHCA_QP_STATE_SQD
;
329 case IB_QPS_SQE
: return MTHCA_QP_STATE_SQE
;
330 case IB_QPS_ERR
: return MTHCA_QP_STATE_ERR
;
335 enum { RC
, UC
, UD
, RD
, RDEE
, MLX
, NUM_TRANS
};
337 static int to_mthca_st(int transport
)
340 case RC
: return MTHCA_QP_ST_RC
;
341 case UC
: return MTHCA_QP_ST_UC
;
342 case UD
: return MTHCA_QP_ST_UD
;
343 case RD
: return MTHCA_QP_ST_RD
;
344 case MLX
: return MTHCA_QP_ST_MLX
;
349 static const struct {
351 u32 req_param
[NUM_TRANS
];
352 u32 opt_param
[NUM_TRANS
];
353 } state_table
[IB_QPS_ERR
+ 1][IB_QPS_ERR
+ 1] = {
355 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
356 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
358 .trans
= MTHCA_TRANS_RST2INIT
,
360 [UD
] = (IB_QP_PKEY_INDEX
|
363 [UC
] = (IB_QP_PKEY_INDEX
|
366 [RC
] = (IB_QP_PKEY_INDEX
|
369 [MLX
] = (IB_QP_PKEY_INDEX
|
372 /* bug-for-bug compatibility with VAPI: */
379 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
380 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
382 .trans
= MTHCA_TRANS_INIT2INIT
,
384 [UD
] = (IB_QP_PKEY_INDEX
|
387 [UC
] = (IB_QP_PKEY_INDEX
|
390 [RC
] = (IB_QP_PKEY_INDEX
|
393 [MLX
] = (IB_QP_PKEY_INDEX
|
398 .trans
= MTHCA_TRANS_INIT2RTR
,
404 IB_QP_MAX_DEST_RD_ATOMIC
),
409 IB_QP_MAX_DEST_RD_ATOMIC
|
410 IB_QP_MIN_RNR_TIMER
),
413 [UD
] = (IB_QP_PKEY_INDEX
|
415 [UC
] = (IB_QP_ALT_PATH
|
418 [RC
] = (IB_QP_ALT_PATH
|
421 [MLX
] = (IB_QP_PKEY_INDEX
|
427 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
428 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
430 .trans
= MTHCA_TRANS_RTR2RTS
,
433 [UC
] = (IB_QP_SQ_PSN
|
434 IB_QP_MAX_QP_RD_ATOMIC
),
435 [RC
] = (IB_QP_TIMEOUT
|
439 IB_QP_MAX_QP_RD_ATOMIC
),
440 [MLX
] = IB_QP_SQ_PSN
,
443 [UD
] = (IB_QP_CUR_STATE
|
445 [UC
] = (IB_QP_CUR_STATE
|
449 IB_QP_PATH_MIG_STATE
),
450 [RC
] = (IB_QP_CUR_STATE
|
454 IB_QP_MIN_RNR_TIMER
|
455 IB_QP_PATH_MIG_STATE
),
456 [MLX
] = (IB_QP_CUR_STATE
|
462 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
463 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
465 .trans
= MTHCA_TRANS_RTS2RTS
,
467 [UD
] = (IB_QP_CUR_STATE
|
469 [UC
] = (IB_QP_ACCESS_FLAGS
|
471 IB_QP_PATH_MIG_STATE
),
472 [RC
] = (IB_QP_ACCESS_FLAGS
|
474 IB_QP_PATH_MIG_STATE
|
475 IB_QP_MIN_RNR_TIMER
),
476 [MLX
] = (IB_QP_CUR_STATE
|
481 .trans
= MTHCA_TRANS_RTS2SQD
,
485 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
486 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
488 .trans
= MTHCA_TRANS_SQD2RTS
,
490 [UD
] = (IB_QP_CUR_STATE
|
492 [UC
] = (IB_QP_CUR_STATE
|
495 IB_QP_PATH_MIG_STATE
),
496 [RC
] = (IB_QP_CUR_STATE
|
499 IB_QP_MIN_RNR_TIMER
|
500 IB_QP_PATH_MIG_STATE
),
501 [MLX
] = (IB_QP_CUR_STATE
|
506 .trans
= MTHCA_TRANS_SQD2SQD
,
508 [UD
] = (IB_QP_PKEY_INDEX
|
511 IB_QP_MAX_QP_RD_ATOMIC
|
512 IB_QP_MAX_DEST_RD_ATOMIC
|
517 IB_QP_PATH_MIG_STATE
),
522 IB_QP_MAX_QP_RD_ATOMIC
|
523 IB_QP_MAX_DEST_RD_ATOMIC
|
528 IB_QP_MIN_RNR_TIMER
|
529 IB_QP_PATH_MIG_STATE
),
530 [MLX
] = (IB_QP_PKEY_INDEX
|
536 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
537 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
},
539 .trans
= MTHCA_TRANS_SQERR2RTS
,
541 [UD
] = (IB_QP_CUR_STATE
|
543 [UC
] = (IB_QP_CUR_STATE
),
544 [RC
] = (IB_QP_CUR_STATE
|
545 IB_QP_MIN_RNR_TIMER
),
546 [MLX
] = (IB_QP_CUR_STATE
|
552 [IB_QPS_RESET
] = { .trans
= MTHCA_TRANS_ANY2RST
},
553 [IB_QPS_ERR
] = { .trans
= MTHCA_TRANS_ANY2ERR
}
557 static void store_attrs(struct mthca_sqp
*sqp
, struct ib_qp_attr
*attr
,
560 if (attr_mask
& IB_QP_PKEY_INDEX
)
561 sqp
->pkey_index
= attr
->pkey_index
;
562 if (attr_mask
& IB_QP_QKEY
)
563 sqp
->qkey
= attr
->qkey
;
564 if (attr_mask
& IB_QP_SQ_PSN
)
565 sqp
->send_psn
= attr
->sq_psn
;
568 static void init_port(struct mthca_dev
*dev
, int port
)
572 struct mthca_init_ib_param param
;
574 memset(¶m
, 0, sizeof param
);
578 param
.vl_cap
= dev
->limits
.vl_cap
;
579 param
.mtu_cap
= dev
->limits
.mtu_cap
;
580 param
.gid_cap
= dev
->limits
.gid_table_len
;
581 param
.pkey_cap
= dev
->limits
.pkey_table_len
;
583 err
= mthca_INIT_IB(dev
, ¶m
, port
, &status
);
585 mthca_warn(dev
, "INIT_IB failed, return code %d.\n", err
);
587 mthca_warn(dev
, "INIT_IB returned status %02x.\n", status
);
590 int mthca_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
, int attr_mask
)
592 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
593 struct mthca_qp
*qp
= to_mqp(ibqp
);
594 enum ib_qp_state cur_state
, new_state
;
595 struct mthca_mailbox
*mailbox
;
596 struct mthca_qp_param
*qp_param
;
597 struct mthca_qp_context
*qp_context
;
598 u32 req_param
, opt_param
;
602 if (attr_mask
& IB_QP_CUR_STATE
) {
603 if (attr
->cur_qp_state
!= IB_QPS_RTR
&&
604 attr
->cur_qp_state
!= IB_QPS_RTS
&&
605 attr
->cur_qp_state
!= IB_QPS_SQD
&&
606 attr
->cur_qp_state
!= IB_QPS_SQE
)
609 cur_state
= attr
->cur_qp_state
;
611 spin_lock_irq(&qp
->sq
.lock
);
612 spin_lock(&qp
->rq
.lock
);
613 cur_state
= qp
->state
;
614 spin_unlock(&qp
->rq
.lock
);
615 spin_unlock_irq(&qp
->sq
.lock
);
618 if (attr_mask
& IB_QP_STATE
) {
619 if (attr
->qp_state
< 0 || attr
->qp_state
> IB_QPS_ERR
)
621 new_state
= attr
->qp_state
;
623 new_state
= cur_state
;
625 if (state_table
[cur_state
][new_state
].trans
== MTHCA_TRANS_INVALID
) {
626 mthca_dbg(dev
, "Illegal QP transition "
627 "%d->%d\n", cur_state
, new_state
);
631 req_param
= state_table
[cur_state
][new_state
].req_param
[qp
->transport
];
632 opt_param
= state_table
[cur_state
][new_state
].opt_param
[qp
->transport
];
634 if ((req_param
& attr_mask
) != req_param
) {
635 mthca_dbg(dev
, "QP transition "
636 "%d->%d missing req attr 0x%08x\n",
637 cur_state
, new_state
,
638 req_param
& ~attr_mask
);
642 if (attr_mask
& ~(req_param
| opt_param
| IB_QP_STATE
)) {
643 mthca_dbg(dev
, "QP transition (transport %d) "
644 "%d->%d has extra attr 0x%08x\n",
646 cur_state
, new_state
,
647 attr_mask
& ~(req_param
| opt_param
|
652 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
654 return PTR_ERR(mailbox
);
655 qp_param
= mailbox
->buf
;
656 qp_context
= &qp_param
->context
;
657 memset(qp_param
, 0, sizeof *qp_param
);
659 qp_context
->flags
= cpu_to_be32((to_mthca_state(new_state
) << 28) |
660 (to_mthca_st(qp
->transport
) << 16));
661 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_BIT_DE
);
662 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
663 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
665 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE
);
666 switch (attr
->path_mig_state
) {
667 case IB_MIG_MIGRATED
:
668 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_MIGRATED
<< 11);
671 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_REARM
<< 11);
674 qp_context
->flags
|= cpu_to_be32(MTHCA_QP_PM_ARMED
<< 11);
679 /* leave tavor_sched_queue as 0 */
681 if (qp
->transport
== MLX
|| qp
->transport
== UD
)
682 qp_context
->mtu_msgmax
= (IB_MTU_2048
<< 5) | 11;
683 else if (attr_mask
& IB_QP_PATH_MTU
)
684 qp_context
->mtu_msgmax
= (attr
->path_mtu
<< 5) | 31;
686 if (mthca_is_memfree(dev
)) {
687 qp_context
->rq_size_stride
=
688 ((ffs(qp
->rq
.max
) - 1) << 3) | (qp
->rq
.wqe_shift
- 4);
689 qp_context
->sq_size_stride
=
690 ((ffs(qp
->sq
.max
) - 1) << 3) | (qp
->sq
.wqe_shift
- 4);
693 /* leave arbel_sched_queue as 0 */
695 if (qp
->ibqp
.uobject
)
696 qp_context
->usr_page
=
697 cpu_to_be32(to_mucontext(qp
->ibqp
.uobject
->context
)->uar
.index
);
699 qp_context
->usr_page
= cpu_to_be32(dev
->driver_uar
.index
);
700 qp_context
->local_qpn
= cpu_to_be32(qp
->qpn
);
701 if (attr_mask
& IB_QP_DEST_QPN
) {
702 qp_context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
705 if (qp
->transport
== MLX
)
706 qp_context
->pri_path
.port_pkey
|=
707 cpu_to_be32(to_msqp(qp
)->port
<< 24);
709 if (attr_mask
& IB_QP_PORT
) {
710 qp_context
->pri_path
.port_pkey
|=
711 cpu_to_be32(attr
->port_num
<< 24);
712 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM
);
716 if (attr_mask
& IB_QP_PKEY_INDEX
) {
717 qp_context
->pri_path
.port_pkey
|=
718 cpu_to_be32(attr
->pkey_index
);
719 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX
);
722 if (attr_mask
& IB_QP_RNR_RETRY
) {
723 qp_context
->pri_path
.rnr_retry
= attr
->rnr_retry
<< 5;
724 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY
);
727 if (attr_mask
& IB_QP_AV
) {
728 qp_context
->pri_path
.g_mylmc
= attr
->ah_attr
.src_path_bits
& 0x7f;
729 qp_context
->pri_path
.rlid
= cpu_to_be16(attr
->ah_attr
.dlid
);
730 qp_context
->pri_path
.static_rate
= !!attr
->ah_attr
.static_rate
;
731 if (attr
->ah_attr
.ah_flags
& IB_AH_GRH
) {
732 qp_context
->pri_path
.g_mylmc
|= 1 << 7;
733 qp_context
->pri_path
.mgid_index
= attr
->ah_attr
.grh
.sgid_index
;
734 qp_context
->pri_path
.hop_limit
= attr
->ah_attr
.grh
.hop_limit
;
735 qp_context
->pri_path
.sl_tclass_flowlabel
=
736 cpu_to_be32((attr
->ah_attr
.sl
<< 28) |
737 (attr
->ah_attr
.grh
.traffic_class
<< 20) |
738 (attr
->ah_attr
.grh
.flow_label
));
739 memcpy(qp_context
->pri_path
.rgid
,
740 attr
->ah_attr
.grh
.dgid
.raw
, 16);
742 qp_context
->pri_path
.sl_tclass_flowlabel
=
743 cpu_to_be32(attr
->ah_attr
.sl
<< 28);
745 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH
);
748 if (attr_mask
& IB_QP_TIMEOUT
) {
749 qp_context
->pri_path
.ackto
= attr
->timeout
;
750 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT
);
756 qp_context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pd_num
);
757 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
758 qp_context
->wqe_lkey
= cpu_to_be32(qp
->mr
.ibmr
.lkey
);
759 qp_context
->params1
= cpu_to_be32((MTHCA_ACK_REQ_FREQ
<< 28) |
760 (MTHCA_FLIGHT_LIMIT
<< 24) |
764 if (qp
->sq_policy
== IB_SIGNAL_ALL_WR
)
765 qp_context
->params1
|= cpu_to_be32(MTHCA_QP_BIT_SSC
);
766 if (attr_mask
& IB_QP_RETRY_CNT
) {
767 qp_context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
768 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT
);
771 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
772 qp_context
->params1
|= cpu_to_be32(min(attr
->max_rd_atomic
?
773 ffs(attr
->max_rd_atomic
) - 1 : 0,
775 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX
);
778 if (attr_mask
& IB_QP_SQ_PSN
)
779 qp_context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
780 qp_context
->cqn_snd
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->cqn
);
782 if (mthca_is_memfree(dev
)) {
783 qp_context
->snd_wqe_base_l
= cpu_to_be32(qp
->send_wqe_offset
);
784 qp_context
->snd_db_index
= cpu_to_be32(qp
->sq
.db_index
);
787 if (attr_mask
& IB_QP_ACCESS_FLAGS
) {
789 * Only enable RDMA/atomics if we have responder
790 * resources set to a non-zero value.
792 if (qp
->resp_depth
) {
793 qp_context
->params2
|=
794 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_WRITE
?
795 MTHCA_QP_BIT_RWE
: 0);
796 qp_context
->params2
|=
797 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_READ
?
798 MTHCA_QP_BIT_RRE
: 0);
799 qp_context
->params2
|=
800 cpu_to_be32(attr
->qp_access_flags
& IB_ACCESS_REMOTE_ATOMIC
?
801 MTHCA_QP_BIT_RAE
: 0);
804 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
805 MTHCA_QP_OPTPAR_RRE
|
806 MTHCA_QP_OPTPAR_RAE
);
808 qp
->atomic_rd_en
= attr
->qp_access_flags
;
811 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
814 if (qp
->resp_depth
&& !attr
->max_dest_rd_atomic
) {
816 * Lowering our responder resources to zero.
817 * Turn off RDMA/atomics as responder.
818 * (RWE/RRE/RAE in params2 already zero)
820 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
821 MTHCA_QP_OPTPAR_RRE
|
822 MTHCA_QP_OPTPAR_RAE
);
825 if (!qp
->resp_depth
&& attr
->max_dest_rd_atomic
) {
827 * Increasing our responder resources from
828 * zero. Turn on RDMA/atomics as appropriate.
830 qp_context
->params2
|=
831 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_WRITE
?
832 MTHCA_QP_BIT_RWE
: 0);
833 qp_context
->params2
|=
834 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_READ
?
835 MTHCA_QP_BIT_RRE
: 0);
836 qp_context
->params2
|=
837 cpu_to_be32(qp
->atomic_rd_en
& IB_ACCESS_REMOTE_ATOMIC
?
838 MTHCA_QP_BIT_RAE
: 0);
840 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RWE
|
841 MTHCA_QP_OPTPAR_RRE
|
842 MTHCA_QP_OPTPAR_RAE
);
846 1 << rra_max
< attr
->max_dest_rd_atomic
&&
847 rra_max
< dev
->qp_table
.rdb_shift
;
851 qp_context
->params2
|= cpu_to_be32(rra_max
<< 21);
852 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX
);
854 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
857 qp_context
->params2
|= cpu_to_be32(MTHCA_QP_BIT_RSC
);
859 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
860 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
861 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT
);
863 if (attr_mask
& IB_QP_RQ_PSN
)
864 qp_context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
866 qp_context
->ra_buff_indx
=
867 cpu_to_be32(dev
->qp_table
.rdb_base
+
868 ((qp
->qpn
& (dev
->limits
.num_qps
- 1)) * MTHCA_RDB_ENTRY_SIZE
<<
869 dev
->qp_table
.rdb_shift
));
871 qp_context
->cqn_rcv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->cqn
);
873 if (mthca_is_memfree(dev
))
874 qp_context
->rcv_db_index
= cpu_to_be32(qp
->rq
.db_index
);
876 if (attr_mask
& IB_QP_QKEY
) {
877 qp_context
->qkey
= cpu_to_be32(attr
->qkey
);
878 qp_param
->opt_param_mask
|= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY
);
881 err
= mthca_MODIFY_QP(dev
, state_table
[cur_state
][new_state
].trans
,
882 qp
->qpn
, 0, mailbox
, 0, &status
);
884 mthca_warn(dev
, "modify QP %d returned status %02x.\n",
885 state_table
[cur_state
][new_state
].trans
, status
);
890 qp
->state
= new_state
;
892 mthca_free_mailbox(dev
, mailbox
);
895 store_attrs(to_msqp(qp
), attr
, attr_mask
);
898 * If we are moving QP0 to RTR, bring the IB link up; if we
899 * are moving QP0 to RESET or ERROR, bring the link back down.
901 if (is_qp0(dev
, qp
)) {
902 if (cur_state
!= IB_QPS_RTR
&&
903 new_state
== IB_QPS_RTR
)
904 init_port(dev
, to_msqp(qp
)->port
);
906 if (cur_state
!= IB_QPS_RESET
&&
907 cur_state
!= IB_QPS_ERR
&&
908 (new_state
== IB_QPS_RESET
||
909 new_state
== IB_QPS_ERR
))
910 mthca_CLOSE_IB(dev
, to_msqp(qp
)->port
, &status
);
917 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
918 * rq.max_gs and sq.max_gs must all be assigned.
919 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
920 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
923 static int mthca_alloc_wqe_buf(struct mthca_dev
*dev
,
931 u64
*dma_list
= NULL
;
934 size
= sizeof (struct mthca_next_seg
) +
935 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
);
937 for (qp
->rq
.wqe_shift
= 6; 1 << qp
->rq
.wqe_shift
< size
;
941 size
= sizeof (struct mthca_next_seg
) +
942 qp
->sq
.max_gs
* sizeof (struct mthca_data_seg
);
943 switch (qp
->transport
) {
945 size
+= 2 * sizeof (struct mthca_data_seg
);
948 if (mthca_is_memfree(dev
))
949 size
+= sizeof (struct mthca_arbel_ud_seg
);
951 size
+= sizeof (struct mthca_tavor_ud_seg
);
954 /* bind seg is as big as atomic + raddr segs */
955 size
+= sizeof (struct mthca_bind_seg
);
958 for (qp
->sq
.wqe_shift
= 6; 1 << qp
->sq
.wqe_shift
< size
;
962 qp
->send_wqe_offset
= ALIGN(qp
->rq
.max
<< qp
->rq
.wqe_shift
,
963 1 << qp
->sq
.wqe_shift
);
966 * If this is a userspace QP, we don't actually have to
967 * allocate anything. All we need is to calculate the WQE
968 * sizes and the send_wqe_offset, so we're done now.
970 if (pd
->ibpd
.uobject
)
973 size
= PAGE_ALIGN(qp
->send_wqe_offset
+
974 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
976 qp
->wrid
= kmalloc((qp
->rq
.max
+ qp
->sq
.max
) * sizeof (u64
),
981 if (size
<= MTHCA_MAX_DIRECT_QP_SIZE
) {
984 shift
= get_order(size
) + PAGE_SHIFT
;
987 mthca_dbg(dev
, "Creating direct QP of size %d (shift %d)\n",
990 qp
->queue
.direct
.buf
= dma_alloc_coherent(&dev
->pdev
->dev
, size
,
992 if (!qp
->queue
.direct
.buf
)
995 pci_unmap_addr_set(&qp
->queue
.direct
, mapping
, t
);
997 memset(qp
->queue
.direct
.buf
, 0, size
);
999 while (t
& ((1 << shift
) - 1)) {
1004 dma_list
= kmalloc(npages
* sizeof *dma_list
, GFP_KERNEL
);
1008 for (i
= 0; i
< npages
; ++i
)
1009 dma_list
[i
] = t
+ i
* (1 << shift
);
1012 npages
= size
/ PAGE_SIZE
;
1016 mthca_dbg(dev
, "Creating indirect QP with %d pages\n", npages
);
1018 dma_list
= kmalloc(npages
* sizeof *dma_list
, GFP_KERNEL
);
1022 qp
->queue
.page_list
= kmalloc(npages
*
1023 sizeof *qp
->queue
.page_list
,
1025 if (!qp
->queue
.page_list
)
1028 for (i
= 0; i
< npages
; ++i
) {
1029 qp
->queue
.page_list
[i
].buf
=
1030 dma_alloc_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
1032 if (!qp
->queue
.page_list
[i
].buf
)
1035 memset(qp
->queue
.page_list
[i
].buf
, 0, PAGE_SIZE
);
1037 pci_unmap_addr_set(&qp
->queue
.page_list
[i
], mapping
, t
);
1042 err
= mthca_mr_alloc_phys(dev
, pd
->pd_num
, dma_list
, shift
,
1044 MTHCA_MPT_FLAG_LOCAL_READ
,
1053 if (qp
->is_direct
) {
1054 dma_free_coherent(&dev
->pdev
->dev
, size
, qp
->queue
.direct
.buf
,
1055 pci_unmap_addr(&qp
->queue
.direct
, mapping
));
1057 for (i
= 0; i
< npages
; ++i
) {
1058 if (qp
->queue
.page_list
[i
].buf
)
1059 dma_free_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
1060 qp
->queue
.page_list
[i
].buf
,
1061 pci_unmap_addr(&qp
->queue
.page_list
[i
],
1072 static void mthca_free_wqe_buf(struct mthca_dev
*dev
,
1073 struct mthca_qp
*qp
)
1076 int size
= PAGE_ALIGN(qp
->send_wqe_offset
+
1077 (qp
->sq
.max
<< qp
->sq
.wqe_shift
));
1079 if (qp
->is_direct
) {
1080 dma_free_coherent(&dev
->pdev
->dev
, size
, qp
->queue
.direct
.buf
,
1081 pci_unmap_addr(&qp
->queue
.direct
, mapping
));
1083 for (i
= 0; i
< size
/ PAGE_SIZE
; ++i
) {
1084 dma_free_coherent(&dev
->pdev
->dev
, PAGE_SIZE
,
1085 qp
->queue
.page_list
[i
].buf
,
1086 pci_unmap_addr(&qp
->queue
.page_list
[i
],
1094 static int mthca_map_memfree(struct mthca_dev
*dev
,
1095 struct mthca_qp
*qp
)
1099 if (mthca_is_memfree(dev
)) {
1100 ret
= mthca_table_get(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1104 ret
= mthca_table_get(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1108 ret
= mthca_table_get(dev
, dev
->qp_table
.rdb_table
,
1109 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1118 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1121 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1126 static void mthca_unmap_memfree(struct mthca_dev
*dev
,
1127 struct mthca_qp
*qp
)
1129 mthca_table_put(dev
, dev
->qp_table
.rdb_table
,
1130 qp
->qpn
<< dev
->qp_table
.rdb_shift
);
1131 mthca_table_put(dev
, dev
->qp_table
.eqp_table
, qp
->qpn
);
1132 mthca_table_put(dev
, dev
->qp_table
.qp_table
, qp
->qpn
);
1135 static int mthca_alloc_memfree(struct mthca_dev
*dev
,
1136 struct mthca_qp
*qp
)
1140 if (mthca_is_memfree(dev
)) {
1141 qp
->rq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_RQ
,
1142 qp
->qpn
, &qp
->rq
.db
);
1143 if (qp
->rq
.db_index
< 0)
1146 qp
->sq
.db_index
= mthca_alloc_db(dev
, MTHCA_DB_TYPE_SQ
,
1147 qp
->qpn
, &qp
->sq
.db
);
1148 if (qp
->sq
.db_index
< 0)
1149 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1155 static void mthca_free_memfree(struct mthca_dev
*dev
,
1156 struct mthca_qp
*qp
)
1158 if (mthca_is_memfree(dev
)) {
1159 mthca_free_db(dev
, MTHCA_DB_TYPE_SQ
, qp
->sq
.db_index
);
1160 mthca_free_db(dev
, MTHCA_DB_TYPE_RQ
, qp
->rq
.db_index
);
1164 static void mthca_wq_init(struct mthca_wq
* wq
)
1166 spin_lock_init(&wq
->lock
);
1168 wq
->last_comp
= wq
->max
- 1;
1174 static int mthca_alloc_qp_common(struct mthca_dev
*dev
,
1175 struct mthca_pd
*pd
,
1176 struct mthca_cq
*send_cq
,
1177 struct mthca_cq
*recv_cq
,
1178 enum ib_sig_type send_policy
,
1179 struct mthca_qp
*qp
)
1184 atomic_set(&qp
->refcount
, 1);
1185 qp
->state
= IB_QPS_RESET
;
1186 qp
->atomic_rd_en
= 0;
1188 qp
->sq_policy
= send_policy
;
1189 mthca_wq_init(&qp
->sq
);
1190 mthca_wq_init(&qp
->rq
);
1192 ret
= mthca_map_memfree(dev
, qp
);
1196 ret
= mthca_alloc_wqe_buf(dev
, pd
, qp
);
1198 mthca_unmap_memfree(dev
, qp
);
1203 * If this is a userspace QP, we're done now. The doorbells
1204 * will be allocated and buffers will be initialized in
1207 if (pd
->ibpd
.uobject
)
1210 ret
= mthca_alloc_memfree(dev
, qp
);
1212 mthca_free_wqe_buf(dev
, qp
);
1213 mthca_unmap_memfree(dev
, qp
);
1217 if (mthca_is_memfree(dev
)) {
1218 struct mthca_next_seg
*next
;
1219 struct mthca_data_seg
*scatter
;
1220 int size
= (sizeof (struct mthca_next_seg
) +
1221 qp
->rq
.max_gs
* sizeof (struct mthca_data_seg
)) / 16;
1223 for (i
= 0; i
< qp
->rq
.max
; ++i
) {
1224 next
= get_recv_wqe(qp
, i
);
1225 next
->nda_op
= cpu_to_be32(((i
+ 1) & (qp
->rq
.max
- 1)) <<
1227 next
->ee_nds
= cpu_to_be32(size
);
1229 for (scatter
= (void *) (next
+ 1);
1230 (void *) scatter
< (void *) next
+ (1 << qp
->rq
.wqe_shift
);
1232 scatter
->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
1235 for (i
= 0; i
< qp
->sq
.max
; ++i
) {
1236 next
= get_send_wqe(qp
, i
);
1237 next
->nda_op
= cpu_to_be32((((i
+ 1) & (qp
->sq
.max
- 1)) <<
1239 qp
->send_wqe_offset
);
1246 static int mthca_set_qp_size(struct mthca_dev
*dev
, struct ib_qp_cap
*cap
,
1247 struct mthca_qp
*qp
)
1249 /* Sanity check QP size before proceeding */
1250 if (cap
->max_send_wr
> 65536 || cap
->max_recv_wr
> 65536 ||
1251 cap
->max_send_sge
> 64 || cap
->max_recv_sge
> 64)
1254 if (mthca_is_memfree(dev
)) {
1255 qp
->rq
.max
= cap
->max_recv_wr
?
1256 roundup_pow_of_two(cap
->max_recv_wr
) : 0;
1257 qp
->sq
.max
= cap
->max_send_wr
?
1258 roundup_pow_of_two(cap
->max_send_wr
) : 0;
1260 qp
->rq
.max
= cap
->max_recv_wr
;
1261 qp
->sq
.max
= cap
->max_send_wr
;
1264 qp
->rq
.max_gs
= cap
->max_recv_sge
;
1265 qp
->sq
.max_gs
= max_t(int, cap
->max_send_sge
,
1266 ALIGN(cap
->max_inline_data
+ MTHCA_INLINE_HEADER_SIZE
,
1267 MTHCA_INLINE_CHUNK_SIZE
) /
1268 sizeof (struct mthca_data_seg
));
1271 * For MLX transport we need 2 extra S/G entries:
1272 * one for the header and one for the checksum at the end
1274 if ((qp
->transport
== MLX
&& qp
->sq
.max_gs
+ 2 > dev
->limits
.max_sg
) ||
1275 qp
->sq
.max_gs
> dev
->limits
.max_sg
|| qp
->rq
.max_gs
> dev
->limits
.max_sg
)
1281 int mthca_alloc_qp(struct mthca_dev
*dev
,
1282 struct mthca_pd
*pd
,
1283 struct mthca_cq
*send_cq
,
1284 struct mthca_cq
*recv_cq
,
1285 enum ib_qp_type type
,
1286 enum ib_sig_type send_policy
,
1287 struct ib_qp_cap
*cap
,
1288 struct mthca_qp
*qp
)
1292 err
= mthca_set_qp_size(dev
, cap
, qp
);
1297 case IB_QPT_RC
: qp
->transport
= RC
; break;
1298 case IB_QPT_UC
: qp
->transport
= UC
; break;
1299 case IB_QPT_UD
: qp
->transport
= UD
; break;
1300 default: return -EINVAL
;
1303 qp
->qpn
= mthca_alloc(&dev
->qp_table
.alloc
);
1307 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1310 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1314 spin_lock_irq(&dev
->qp_table
.lock
);
1315 mthca_array_set(&dev
->qp_table
.qp
,
1316 qp
->qpn
& (dev
->limits
.num_qps
- 1), qp
);
1317 spin_unlock_irq(&dev
->qp_table
.lock
);
1322 int mthca_alloc_sqp(struct mthca_dev
*dev
,
1323 struct mthca_pd
*pd
,
1324 struct mthca_cq
*send_cq
,
1325 struct mthca_cq
*recv_cq
,
1326 enum ib_sig_type send_policy
,
1327 struct ib_qp_cap
*cap
,
1330 struct mthca_sqp
*sqp
)
1332 u32 mqpn
= qpn
* 2 + dev
->qp_table
.sqp_start
+ port
- 1;
1335 err
= mthca_set_qp_size(dev
, cap
, &sqp
->qp
);
1339 sqp
->header_buf_size
= sqp
->qp
.sq
.max
* MTHCA_UD_HEADER_SIZE
;
1340 sqp
->header_buf
= dma_alloc_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1341 &sqp
->header_dma
, GFP_KERNEL
);
1342 if (!sqp
->header_buf
)
1345 spin_lock_irq(&dev
->qp_table
.lock
);
1346 if (mthca_array_get(&dev
->qp_table
.qp
, mqpn
))
1349 mthca_array_set(&dev
->qp_table
.qp
, mqpn
, sqp
);
1350 spin_unlock_irq(&dev
->qp_table
.lock
);
1357 sqp
->qp
.transport
= MLX
;
1359 err
= mthca_alloc_qp_common(dev
, pd
, send_cq
, recv_cq
,
1360 send_policy
, &sqp
->qp
);
1364 atomic_inc(&pd
->sqp_count
);
1370 * Lock CQs here, so that CQ polling code can do QP lookup
1371 * without taking a lock.
1373 spin_lock_irq(&send_cq
->lock
);
1374 if (send_cq
!= recv_cq
)
1375 spin_lock(&recv_cq
->lock
);
1377 spin_lock(&dev
->qp_table
.lock
);
1378 mthca_array_clear(&dev
->qp_table
.qp
, mqpn
);
1379 spin_unlock(&dev
->qp_table
.lock
);
1381 if (send_cq
!= recv_cq
)
1382 spin_unlock(&recv_cq
->lock
);
1383 spin_unlock_irq(&send_cq
->lock
);
1386 dma_free_coherent(&dev
->pdev
->dev
, sqp
->header_buf_size
,
1387 sqp
->header_buf
, sqp
->header_dma
);
1392 void mthca_free_qp(struct mthca_dev
*dev
,
1393 struct mthca_qp
*qp
)
1396 struct mthca_cq
*send_cq
;
1397 struct mthca_cq
*recv_cq
;
1399 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1400 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1403 * Lock CQs here, so that CQ polling code can do QP lookup
1404 * without taking a lock.
1406 spin_lock_irq(&send_cq
->lock
);
1407 if (send_cq
!= recv_cq
)
1408 spin_lock(&recv_cq
->lock
);
1410 spin_lock(&dev
->qp_table
.lock
);
1411 mthca_array_clear(&dev
->qp_table
.qp
,
1412 qp
->qpn
& (dev
->limits
.num_qps
- 1));
1413 spin_unlock(&dev
->qp_table
.lock
);
1415 if (send_cq
!= recv_cq
)
1416 spin_unlock(&recv_cq
->lock
);
1417 spin_unlock_irq(&send_cq
->lock
);
1419 atomic_dec(&qp
->refcount
);
1420 wait_event(qp
->wait
, !atomic_read(&qp
->refcount
));
1422 if (qp
->state
!= IB_QPS_RESET
)
1423 mthca_MODIFY_QP(dev
, MTHCA_TRANS_ANY2RST
, qp
->qpn
, 0, NULL
, 0, &status
);
1426 * If this is a userspace QP, the buffers, MR, CQs and so on
1427 * will be cleaned up in userspace, so all we have to do is
1428 * unref the mem-free tables and free the QPN in our table.
1430 if (!qp
->ibqp
.uobject
) {
1431 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.send_cq
)->cqn
, qp
->qpn
);
1432 if (qp
->ibqp
.send_cq
!= qp
->ibqp
.recv_cq
)
1433 mthca_cq_clean(dev
, to_mcq(qp
->ibqp
.recv_cq
)->cqn
, qp
->qpn
);
1435 mthca_free_mr(dev
, &qp
->mr
);
1436 mthca_free_memfree(dev
, qp
);
1437 mthca_free_wqe_buf(dev
, qp
);
1440 mthca_unmap_memfree(dev
, qp
);
1442 if (is_sqp(dev
, qp
)) {
1443 atomic_dec(&(to_mpd(qp
->ibqp
.pd
)->sqp_count
));
1444 dma_free_coherent(&dev
->pdev
->dev
,
1445 to_msqp(qp
)->header_buf_size
,
1446 to_msqp(qp
)->header_buf
,
1447 to_msqp(qp
)->header_dma
);
1449 mthca_free(&dev
->qp_table
.alloc
, qp
->qpn
);
1452 /* Create UD header for an MLX send and build a data segment for it */
1453 static int build_mlx_header(struct mthca_dev
*dev
, struct mthca_sqp
*sqp
,
1454 int ind
, struct ib_send_wr
*wr
,
1455 struct mthca_mlx_seg
*mlx
,
1456 struct mthca_data_seg
*data
)
1461 ib_ud_header_init(256, /* assume a MAD */
1462 sqp
->ud_header
.grh_present
,
1465 err
= mthca_read_ah(dev
, to_mah(wr
->wr
.ud
.ah
), &sqp
->ud_header
);
1468 mlx
->flags
&= ~cpu_to_be32(MTHCA_NEXT_SOLICIT
| 1);
1469 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MTHCA_MLX_VL15
: 0) |
1470 (sqp
->ud_header
.lrh
.destination_lid
== 0xffff ?
1471 MTHCA_MLX_SLR
: 0) |
1472 (sqp
->ud_header
.lrh
.service_level
<< 8));
1473 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1476 switch (wr
->opcode
) {
1478 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1479 sqp
->ud_header
.immediate_present
= 0;
1481 case IB_WR_SEND_WITH_IMM
:
1482 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1483 sqp
->ud_header
.immediate_present
= 1;
1484 sqp
->ud_header
.immediate_data
= wr
->imm_data
;
1490 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1491 if (sqp
->ud_header
.lrh
.destination_lid
== 0xffff)
1492 sqp
->ud_header
.lrh
.source_lid
= 0xffff;
1493 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1494 if (!sqp
->qp
.ibqp
.qp_num
)
1495 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1497 &sqp
->ud_header
.bth
.pkey
);
1499 ib_get_cached_pkey(&dev
->ib_dev
, sqp
->port
,
1500 wr
->wr
.ud
.pkey_index
,
1501 &sqp
->ud_header
.bth
.pkey
);
1502 cpu_to_be16s(&sqp
->ud_header
.bth
.pkey
);
1503 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1504 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1505 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1506 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1507 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1509 header_size
= ib_ud_header_pack(&sqp
->ud_header
,
1511 ind
* MTHCA_UD_HEADER_SIZE
);
1513 data
->byte_count
= cpu_to_be32(header_size
);
1514 data
->lkey
= cpu_to_be32(to_mpd(sqp
->qp
.ibqp
.pd
)->ntmr
.ibmr
.lkey
);
1515 data
->addr
= cpu_to_be64(sqp
->header_dma
+
1516 ind
* MTHCA_UD_HEADER_SIZE
);
1521 static inline int mthca_wq_overflow(struct mthca_wq
*wq
, int nreq
,
1522 struct ib_cq
*ib_cq
)
1525 struct mthca_cq
*cq
;
1527 cur
= wq
->head
- wq
->tail
;
1528 if (likely(cur
+ nreq
< wq
->max
))
1532 spin_lock(&cq
->lock
);
1533 cur
= wq
->head
- wq
->tail
;
1534 spin_unlock(&cq
->lock
);
1536 return cur
+ nreq
>= wq
->max
;
1539 int mthca_tavor_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1540 struct ib_send_wr
**bad_wr
)
1542 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1543 struct mthca_qp
*qp
= to_mqp(ibqp
);
1546 unsigned long flags
;
1556 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1558 /* XXX check that state is OK to post send */
1560 ind
= qp
->sq
.next_ind
;
1562 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1563 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1564 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1565 " %d max, %d nreq)\n", qp
->qpn
,
1566 qp
->sq
.head
, qp
->sq
.tail
,
1573 wqe
= get_send_wqe(qp
, ind
);
1574 prev_wqe
= qp
->sq
.last
;
1577 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1578 ((struct mthca_next_seg
*) wqe
)->ee_nds
= 0;
1579 ((struct mthca_next_seg
*) wqe
)->flags
=
1580 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1581 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1582 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1583 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1585 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1586 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1587 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1589 wqe
+= sizeof (struct mthca_next_seg
);
1590 size
= sizeof (struct mthca_next_seg
) / 16;
1592 switch (qp
->transport
) {
1594 switch (wr
->opcode
) {
1595 case IB_WR_ATOMIC_CMP_AND_SWP
:
1596 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1597 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1598 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1599 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1600 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1601 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1603 wqe
+= sizeof (struct mthca_raddr_seg
);
1605 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1606 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1607 cpu_to_be64(wr
->wr
.atomic
.swap
);
1608 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1609 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1611 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1612 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1613 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1616 wqe
+= sizeof (struct mthca_atomic_seg
);
1617 size
+= sizeof (struct mthca_raddr_seg
) / 16 +
1618 sizeof (struct mthca_atomic_seg
);
1621 case IB_WR_RDMA_WRITE
:
1622 case IB_WR_RDMA_WRITE_WITH_IMM
:
1623 case IB_WR_RDMA_READ
:
1624 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1625 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1626 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1627 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1628 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1629 wqe
+= sizeof (struct mthca_raddr_seg
);
1630 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1634 /* No extra segments required for sends */
1641 switch (wr
->opcode
) {
1642 case IB_WR_RDMA_WRITE
:
1643 case IB_WR_RDMA_WRITE_WITH_IMM
:
1644 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1645 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1646 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1647 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1648 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1649 wqe
+= sizeof (struct mthca_raddr_seg
);
1650 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1654 /* No extra segments required for sends */
1661 ((struct mthca_tavor_ud_seg
*) wqe
)->lkey
=
1662 cpu_to_be32(to_mah(wr
->wr
.ud
.ah
)->key
);
1663 ((struct mthca_tavor_ud_seg
*) wqe
)->av_addr
=
1664 cpu_to_be64(to_mah(wr
->wr
.ud
.ah
)->avdma
);
1665 ((struct mthca_tavor_ud_seg
*) wqe
)->dqpn
=
1666 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1667 ((struct mthca_tavor_ud_seg
*) wqe
)->qkey
=
1668 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1670 wqe
+= sizeof (struct mthca_tavor_ud_seg
);
1671 size
+= sizeof (struct mthca_tavor_ud_seg
) / 16;
1675 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1676 wqe
- sizeof (struct mthca_next_seg
),
1682 wqe
+= sizeof (struct mthca_data_seg
);
1683 size
+= sizeof (struct mthca_data_seg
) / 16;
1687 if (wr
->num_sge
> qp
->sq
.max_gs
) {
1688 mthca_err(dev
, "too many gathers\n");
1694 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1695 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1696 cpu_to_be32(wr
->sg_list
[i
].length
);
1697 ((struct mthca_data_seg
*) wqe
)->lkey
=
1698 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1699 ((struct mthca_data_seg
*) wqe
)->addr
=
1700 cpu_to_be64(wr
->sg_list
[i
].addr
);
1701 wqe
+= sizeof (struct mthca_data_seg
);
1702 size
+= sizeof (struct mthca_data_seg
) / 16;
1705 /* Add one more inline data segment for ICRC */
1706 if (qp
->transport
== MLX
) {
1707 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1708 cpu_to_be32((1 << 31) | 4);
1709 ((u32
*) wqe
)[1] = 0;
1710 wqe
+= sizeof (struct mthca_data_seg
);
1711 size
+= sizeof (struct mthca_data_seg
) / 16;
1714 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
1716 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
1717 mthca_err(dev
, "opcode invalid\n");
1724 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1725 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
1726 qp
->send_wqe_offset
) |
1727 mthca_opcode
[wr
->opcode
]);
1729 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1730 cpu_to_be32((size0
? 0 : MTHCA_NEXT_DBD
) | size
);
1735 op0
= mthca_opcode
[wr
->opcode
];
1739 if (unlikely(ind
>= qp
->sq
.max
))
1747 doorbell
[0] = cpu_to_be32(((qp
->sq
.next_ind
<< qp
->sq
.wqe_shift
) +
1748 qp
->send_wqe_offset
) | f0
| op0
);
1749 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
1753 mthca_write64(doorbell
,
1754 dev
->kar
+ MTHCA_SEND_DOORBELL
,
1755 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1758 qp
->sq
.next_ind
= ind
;
1759 qp
->sq
.head
+= nreq
;
1761 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1765 int mthca_tavor_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1766 struct ib_recv_wr
**bad_wr
)
1768 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1769 struct mthca_qp
*qp
= to_mqp(ibqp
);
1770 unsigned long flags
;
1780 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1782 /* XXX check that state is OK to post receive */
1784 ind
= qp
->rq
.next_ind
;
1786 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1787 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1788 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
1789 " %d max, %d nreq)\n", qp
->qpn
,
1790 qp
->rq
.head
, qp
->rq
.tail
,
1797 wqe
= get_recv_wqe(qp
, ind
);
1798 prev_wqe
= qp
->rq
.last
;
1801 ((struct mthca_next_seg
*) wqe
)->nda_op
= 0;
1802 ((struct mthca_next_seg
*) wqe
)->ee_nds
=
1803 cpu_to_be32(MTHCA_NEXT_DBD
);
1804 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
1806 wqe
+= sizeof (struct mthca_next_seg
);
1807 size
= sizeof (struct mthca_next_seg
) / 16;
1809 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1815 for (i
= 0; i
< wr
->num_sge
; ++i
) {
1816 ((struct mthca_data_seg
*) wqe
)->byte_count
=
1817 cpu_to_be32(wr
->sg_list
[i
].length
);
1818 ((struct mthca_data_seg
*) wqe
)->lkey
=
1819 cpu_to_be32(wr
->sg_list
[i
].lkey
);
1820 ((struct mthca_data_seg
*) wqe
)->addr
=
1821 cpu_to_be64(wr
->sg_list
[i
].addr
);
1822 wqe
+= sizeof (struct mthca_data_seg
);
1823 size
+= sizeof (struct mthca_data_seg
) / 16;
1826 qp
->wrid
[ind
] = wr
->wr_id
;
1828 if (likely(prev_wqe
)) {
1829 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
1830 cpu_to_be32((ind
<< qp
->rq
.wqe_shift
) | 1);
1832 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
1833 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
1840 if (unlikely(ind
>= qp
->rq
.max
))
1848 doorbell
[0] = cpu_to_be32((qp
->rq
.next_ind
<< qp
->rq
.wqe_shift
) | size0
);
1849 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | nreq
);
1853 mthca_write64(doorbell
,
1854 dev
->kar
+ MTHCA_RECEIVE_DOORBELL
,
1855 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
1858 qp
->rq
.next_ind
= ind
;
1859 qp
->rq
.head
+= nreq
;
1861 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1865 int mthca_arbel_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1866 struct ib_send_wr
**bad_wr
)
1868 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
1869 struct mthca_qp
*qp
= to_mqp(ibqp
);
1872 unsigned long flags
;
1882 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1884 /* XXX check that state is OK to post send */
1886 ind
= qp
->sq
.head
& (qp
->sq
.max
- 1);
1888 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1889 if (mthca_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1890 mthca_err(dev
, "SQ %06x full (%u head, %u tail,"
1891 " %d max, %d nreq)\n", qp
->qpn
,
1892 qp
->sq
.head
, qp
->sq
.tail
,
1899 wqe
= get_send_wqe(qp
, ind
);
1900 prev_wqe
= qp
->sq
.last
;
1903 ((struct mthca_next_seg
*) wqe
)->flags
=
1904 ((wr
->send_flags
& IB_SEND_SIGNALED
) ?
1905 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE
) : 0) |
1906 ((wr
->send_flags
& IB_SEND_SOLICITED
) ?
1907 cpu_to_be32(MTHCA_NEXT_SOLICIT
) : 0) |
1909 if (wr
->opcode
== IB_WR_SEND_WITH_IMM
||
1910 wr
->opcode
== IB_WR_RDMA_WRITE_WITH_IMM
)
1911 ((struct mthca_next_seg
*) wqe
)->imm
= wr
->imm_data
;
1913 wqe
+= sizeof (struct mthca_next_seg
);
1914 size
= sizeof (struct mthca_next_seg
) / 16;
1916 switch (qp
->transport
) {
1918 switch (wr
->opcode
) {
1919 case IB_WR_ATOMIC_CMP_AND_SWP
:
1920 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1921 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1922 cpu_to_be64(wr
->wr
.atomic
.remote_addr
);
1923 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1924 cpu_to_be32(wr
->wr
.atomic
.rkey
);
1925 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1927 wqe
+= sizeof (struct mthca_raddr_seg
);
1929 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1930 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1931 cpu_to_be64(wr
->wr
.atomic
.swap
);
1932 ((struct mthca_atomic_seg
*) wqe
)->compare
=
1933 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1935 ((struct mthca_atomic_seg
*) wqe
)->swap_add
=
1936 cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1937 ((struct mthca_atomic_seg
*) wqe
)->compare
= 0;
1940 wqe
+= sizeof (struct mthca_atomic_seg
);
1941 size
+= sizeof (struct mthca_raddr_seg
) / 16 +
1942 sizeof (struct mthca_atomic_seg
);
1945 case IB_WR_RDMA_READ
:
1946 case IB_WR_RDMA_WRITE
:
1947 case IB_WR_RDMA_WRITE_WITH_IMM
:
1948 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1949 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1950 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1951 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1952 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1953 wqe
+= sizeof (struct mthca_raddr_seg
);
1954 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1958 /* No extra segments required for sends */
1965 switch (wr
->opcode
) {
1966 case IB_WR_RDMA_WRITE
:
1967 case IB_WR_RDMA_WRITE_WITH_IMM
:
1968 ((struct mthca_raddr_seg
*) wqe
)->raddr
=
1969 cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
1970 ((struct mthca_raddr_seg
*) wqe
)->rkey
=
1971 cpu_to_be32(wr
->wr
.rdma
.rkey
);
1972 ((struct mthca_raddr_seg
*) wqe
)->reserved
= 0;
1973 wqe
+= sizeof (struct mthca_raddr_seg
);
1974 size
+= sizeof (struct mthca_raddr_seg
) / 16;
1978 /* No extra segments required for sends */
1985 memcpy(((struct mthca_arbel_ud_seg
*) wqe
)->av
,
1986 to_mah(wr
->wr
.ud
.ah
)->av
, MTHCA_AV_SIZE
);
1987 ((struct mthca_arbel_ud_seg
*) wqe
)->dqpn
=
1988 cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1989 ((struct mthca_arbel_ud_seg
*) wqe
)->qkey
=
1990 cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1992 wqe
+= sizeof (struct mthca_arbel_ud_seg
);
1993 size
+= sizeof (struct mthca_arbel_ud_seg
) / 16;
1997 err
= build_mlx_header(dev
, to_msqp(qp
), ind
, wr
,
1998 wqe
- sizeof (struct mthca_next_seg
),
2004 wqe
+= sizeof (struct mthca_data_seg
);
2005 size
+= sizeof (struct mthca_data_seg
) / 16;
2009 if (wr
->num_sge
> qp
->sq
.max_gs
) {
2010 mthca_err(dev
, "too many gathers\n");
2016 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2017 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2018 cpu_to_be32(wr
->sg_list
[i
].length
);
2019 ((struct mthca_data_seg
*) wqe
)->lkey
=
2020 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2021 ((struct mthca_data_seg
*) wqe
)->addr
=
2022 cpu_to_be64(wr
->sg_list
[i
].addr
);
2023 wqe
+= sizeof (struct mthca_data_seg
);
2024 size
+= sizeof (struct mthca_data_seg
) / 16;
2027 /* Add one more inline data segment for ICRC */
2028 if (qp
->transport
== MLX
) {
2029 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2030 cpu_to_be32((1 << 31) | 4);
2031 ((u32
*) wqe
)[1] = 0;
2032 wqe
+= sizeof (struct mthca_data_seg
);
2033 size
+= sizeof (struct mthca_data_seg
) / 16;
2036 qp
->wrid
[ind
+ qp
->rq
.max
] = wr
->wr_id
;
2038 if (wr
->opcode
>= ARRAY_SIZE(mthca_opcode
)) {
2039 mthca_err(dev
, "opcode invalid\n");
2045 if (likely(prev_wqe
)) {
2046 ((struct mthca_next_seg
*) prev_wqe
)->nda_op
=
2047 cpu_to_be32(((ind
<< qp
->sq
.wqe_shift
) +
2048 qp
->send_wqe_offset
) |
2049 mthca_opcode
[wr
->opcode
]);
2051 ((struct mthca_next_seg
*) prev_wqe
)->ee_nds
=
2052 cpu_to_be32(MTHCA_NEXT_DBD
| size
);
2057 op0
= mthca_opcode
[wr
->opcode
];
2061 if (unlikely(ind
>= qp
->sq
.max
))
2069 doorbell
[0] = cpu_to_be32((nreq
<< 24) |
2070 ((qp
->sq
.head
& 0xffff) << 8) |
2072 doorbell
[1] = cpu_to_be32((qp
->qpn
<< 8) | size0
);
2074 qp
->sq
.head
+= nreq
;
2077 * Make sure that descriptors are written before
2081 *qp
->sq
.db
= cpu_to_be32(qp
->sq
.head
& 0xffff);
2084 * Make sure doorbell record is written before we
2085 * write MMIO send doorbell.
2088 mthca_write64(doorbell
,
2089 dev
->kar
+ MTHCA_SEND_DOORBELL
,
2090 MTHCA_GET_DOORBELL_LOCK(&dev
->doorbell_lock
));
2093 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
2097 int mthca_arbel_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
2098 struct ib_recv_wr
**bad_wr
)
2100 struct mthca_dev
*dev
= to_mdev(ibqp
->device
);
2101 struct mthca_qp
*qp
= to_mqp(ibqp
);
2102 unsigned long flags
;
2109 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
2111 /* XXX check that state is OK to post receive */
2113 ind
= qp
->rq
.head
& (qp
->rq
.max
- 1);
2115 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
2116 if (mthca_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
2117 mthca_err(dev
, "RQ %06x full (%u head, %u tail,"
2118 " %d max, %d nreq)\n", qp
->qpn
,
2119 qp
->rq
.head
, qp
->rq
.tail
,
2126 wqe
= get_recv_wqe(qp
, ind
);
2128 ((struct mthca_next_seg
*) wqe
)->flags
= 0;
2130 wqe
+= sizeof (struct mthca_next_seg
);
2132 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
2138 for (i
= 0; i
< wr
->num_sge
; ++i
) {
2139 ((struct mthca_data_seg
*) wqe
)->byte_count
=
2140 cpu_to_be32(wr
->sg_list
[i
].length
);
2141 ((struct mthca_data_seg
*) wqe
)->lkey
=
2142 cpu_to_be32(wr
->sg_list
[i
].lkey
);
2143 ((struct mthca_data_seg
*) wqe
)->addr
=
2144 cpu_to_be64(wr
->sg_list
[i
].addr
);
2145 wqe
+= sizeof (struct mthca_data_seg
);
2148 if (i
< qp
->rq
.max_gs
) {
2149 ((struct mthca_data_seg
*) wqe
)->byte_count
= 0;
2150 ((struct mthca_data_seg
*) wqe
)->lkey
= cpu_to_be32(MTHCA_INVAL_LKEY
);
2151 ((struct mthca_data_seg
*) wqe
)->addr
= 0;
2154 qp
->wrid
[ind
] = wr
->wr_id
;
2157 if (unlikely(ind
>= qp
->rq
.max
))
2162 qp
->rq
.head
+= nreq
;
2165 * Make sure that descriptors are written before
2169 *qp
->rq
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
2172 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
2176 int mthca_free_err_wqe(struct mthca_dev
*dev
, struct mthca_qp
*qp
, int is_send
,
2177 int index
, int *dbd
, u32
*new_wqe
)
2179 struct mthca_next_seg
*next
;
2182 next
= get_send_wqe(qp
, index
);
2184 next
= get_recv_wqe(qp
, index
);
2186 if (mthca_is_memfree(dev
))
2189 *dbd
= !!(next
->ee_nds
& cpu_to_be32(MTHCA_NEXT_DBD
));
2190 if (next
->ee_nds
& cpu_to_be32(0x3f))
2191 *new_wqe
= (next
->nda_op
& cpu_to_be32(~0x3f)) |
2192 (next
->ee_nds
& cpu_to_be32(0x3f));
2199 int __devinit
mthca_init_qp_table(struct mthca_dev
*dev
)
2205 spin_lock_init(&dev
->qp_table
.lock
);
2208 * We reserve 2 extra QPs per port for the special QPs. The
2209 * special QP for port 1 has to be even, so round up.
2211 dev
->qp_table
.sqp_start
= (dev
->limits
.reserved_qps
+ 1) & ~1UL;
2212 err
= mthca_alloc_init(&dev
->qp_table
.alloc
,
2213 dev
->limits
.num_qps
,
2215 dev
->qp_table
.sqp_start
+
2216 MTHCA_MAX_PORTS
* 2);
2220 err
= mthca_array_init(&dev
->qp_table
.qp
,
2221 dev
->limits
.num_qps
);
2223 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2227 for (i
= 0; i
< 2; ++i
) {
2228 err
= mthca_CONF_SPECIAL_QP(dev
, i
? IB_QPT_GSI
: IB_QPT_SMI
,
2229 dev
->qp_table
.sqp_start
+ i
* 2,
2234 mthca_warn(dev
, "CONF_SPECIAL_QP returned "
2235 "status %02x, aborting.\n",
2244 for (i
= 0; i
< 2; ++i
)
2245 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2247 mthca_array_cleanup(&dev
->qp_table
.qp
, dev
->limits
.num_qps
);
2248 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);
2253 void __devexit
mthca_cleanup_qp_table(struct mthca_dev
*dev
)
2258 for (i
= 0; i
< 2; ++i
)
2259 mthca_CONF_SPECIAL_QP(dev
, i
, 0, &status
);
2261 mthca_alloc_cleanup(&dev
->qp_table
.alloc
);