2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus
* bus
)
34 struct list_head
*tmp
;
38 list_for_each(tmp
, &bus
->children
) {
39 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
47 * pci_max_busnr - returns maximum PCI bus number
49 * Returns the highest PCI bus number present in the system global list of
52 unsigned char __devinit
55 struct pci_bus
*bus
= NULL
;
59 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
60 n
= pci_bus_max_busnr(bus
);
69 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 pos
, int cap
)
75 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
79 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
85 pos
+= PCI_CAP_LIST_NEXT
;
90 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
92 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
93 pos
+ PCI_CAP_LIST_NEXT
, cap
);
95 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
97 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
102 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
103 if (!(status
& PCI_STATUS_CAP_LIST
))
107 case PCI_HEADER_TYPE_NORMAL
:
108 case PCI_HEADER_TYPE_BRIDGE
:
109 pos
= PCI_CAPABILITY_LIST
;
111 case PCI_HEADER_TYPE_CARDBUS
:
112 pos
= PCI_CB_CAPABILITY_LIST
;
117 return __pci_find_next_cap(bus
, devfn
, pos
, cap
);
121 * pci_find_capability - query for devices' capabilities
122 * @dev: PCI device to query
123 * @cap: capability code
125 * Tell if a device supports a given PCI capability.
126 * Returns the address of the requested capability structure within the
127 * device's PCI configuration space or 0 in case the device does not
128 * support it. Possible values for @cap:
130 * %PCI_CAP_ID_PM Power Management
131 * %PCI_CAP_ID_AGP Accelerated Graphics Port
132 * %PCI_CAP_ID_VPD Vital Product Data
133 * %PCI_CAP_ID_SLOTID Slot Identification
134 * %PCI_CAP_ID_MSI Message Signalled Interrupts
135 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
136 * %PCI_CAP_ID_PCIX PCI-X
137 * %PCI_CAP_ID_EXP PCI Express
139 int pci_find_capability(struct pci_dev
*dev
, int cap
)
141 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
145 * pci_bus_find_capability - query for devices' capabilities
146 * @bus: the PCI bus to query
147 * @devfn: PCI device to query
148 * @cap: capability code
150 * Like pci_find_capability() but works for pci devices that do not have a
151 * pci_dev structure set up yet.
153 * Returns the address of the requested capability structure within the
154 * device's PCI configuration space or 0 in case the device does not
157 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
161 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
163 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
167 * pci_find_ext_capability - Find an extended capability
168 * @dev: PCI device to query
169 * @cap: capability code
171 * Returns the address of the requested extended capability structure
172 * within the device's PCI configuration space or 0 if the device does
173 * not support it. Possible values for @cap:
175 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
176 * %PCI_EXT_CAP_ID_VC Virtual Channel
177 * %PCI_EXT_CAP_ID_DSN Device Serial Number
178 * %PCI_EXT_CAP_ID_PWR Power Budgeting
180 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
183 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
186 if (dev
->cfg_size
<= 256)
189 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
193 * If we have no capabilities, this is indicated by cap ID,
194 * cap version and next pointer all being 0.
200 if (PCI_EXT_CAP_ID(header
) == cap
)
203 pos
= PCI_EXT_CAP_NEXT(header
);
207 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
215 * pci_find_parent_resource - return resource region of parent bus of given region
216 * @dev: PCI device structure contains resources to be searched
217 * @res: child resource record for which parent is sought
219 * For given resource region of given device, return the resource
220 * region of parent bus the given region is contained in or where
221 * it should be allocated from.
224 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
226 const struct pci_bus
*bus
= dev
->bus
;
228 struct resource
*best
= NULL
;
230 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
231 struct resource
*r
= bus
->resource
[i
];
234 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
235 continue; /* Not contained */
236 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
237 continue; /* Wrong type */
238 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
239 return r
; /* Exact match */
240 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
241 best
= r
; /* Approximating prefetchable by non-prefetchable */
247 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
248 * @dev: PCI device to have its BARs restored
250 * Restore the BAR values for a given device, so as to make it
251 * accessible by its driver.
254 pci_restore_bars(struct pci_dev
*dev
)
258 switch (dev
->hdr_type
) {
259 case PCI_HEADER_TYPE_NORMAL
:
262 case PCI_HEADER_TYPE_BRIDGE
:
265 case PCI_HEADER_TYPE_CARDBUS
:
269 /* Should never get here, but just in case... */
273 for (i
= 0; i
< numres
; i
++)
274 pci_update_resource(dev
, &dev
->resource
[i
], i
);
277 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
280 * pci_set_power_state - Set the power state of a PCI device
281 * @dev: PCI device to be suspended
282 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
284 * Transition a device to a new power state, using the Power Management
285 * Capabilities in the device's config space.
288 * -EINVAL if trying to enter a lower state than we're already in.
289 * 0 if we're already in the requested state.
290 * -EIO if device does not support PCI PM.
291 * 0 if we can successfully change the power state.
294 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
296 int pm
, need_restore
= 0;
299 /* bound the state we're entering */
300 if (state
> PCI_D3hot
)
303 /* Validate current state:
304 * Can enter D0 from any state, but if we can only go deeper
305 * to sleep if we're already in a low power state
307 if (state
!= PCI_D0
&& dev
->current_state
> state
)
309 else if (dev
->current_state
== state
)
310 return 0; /* we're already there */
312 /* find PCI PM capability in list */
313 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
315 /* abort if the device doesn't support PM capabilities */
319 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
320 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
322 "PCI: %s has unsupported PM cap regs version (%u)\n",
323 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
327 /* check if this device supports the desired state */
328 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
330 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
333 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
335 /* If we're (effectively) in D3, force entire word to 0.
336 * This doesn't affect PME_Status, disables PME_En, and
337 * sets PowerState to 0.
339 switch (dev
->current_state
) {
343 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
346 case PCI_UNKNOWN
: /* Boot-up */
347 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
348 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
350 /* Fall-through: force to D0 */
356 /* enter specified state */
357 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
359 /* Mandatory power management transition delays */
360 /* see PCI PM 1.1 5.6.1 table 18 */
361 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
363 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
367 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
368 * Firmware method after natice method ?
370 if (platform_pci_set_power_state
)
371 platform_pci_set_power_state(dev
, state
);
373 dev
->current_state
= state
;
375 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
376 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
377 * from D3hot to D0 _may_ perform an internal reset, thereby
378 * going to "D0 Uninitialized" rather than "D0 Initialized".
379 * For example, at least some versions of the 3c905B and the
380 * 3c556B exhibit this behaviour.
382 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
383 * devices in a D3hot state at boot. Consequently, we need to
384 * restore at least the BARs so that the device will be
385 * accessible to its driver.
388 pci_restore_bars(dev
);
393 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
396 * pci_choose_state - Choose the power state of a PCI device
397 * @dev: PCI device to be suspended
398 * @state: target sleep state for the whole system. This is the value
399 * that is passed to suspend() function.
401 * Returns PCI power state suitable for given device and given system
405 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
409 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
412 if (platform_pci_choose_state
) {
413 ret
= platform_pci_choose_state(dev
, state
);
418 switch (state
.event
) {
421 case PM_EVENT_FREEZE
:
422 case PM_EVENT_SUSPEND
:
425 printk("They asked me for state %d\n", state
.event
);
431 EXPORT_SYMBOL(pci_choose_state
);
434 * pci_save_state - save the PCI configuration space of a device before suspending
435 * @dev: - PCI device that we're dealing with
438 pci_save_state(struct pci_dev
*dev
)
441 /* XXX: 100% dword access ok here? */
442 for (i
= 0; i
< 16; i
++)
443 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
448 * pci_restore_state - Restore the saved state of a PCI device
449 * @dev: - PCI device that we're dealing with
452 pci_restore_state(struct pci_dev
*dev
)
456 for (i
= 0; i
< 16; i
++)
457 pci_write_config_dword(dev
,i
* 4, dev
->saved_config_space
[i
]);
462 * pci_enable_device_bars - Initialize some of a device for use
463 * @dev: PCI device to be initialized
464 * @bars: bitmask of BAR's that must be configured
466 * Initialize device before it's used by a driver. Ask low-level code
467 * to enable selected I/O and memory resources. Wake up the device if it
468 * was suspended. Beware, this function can fail.
472 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
476 err
= pci_set_power_state(dev
, PCI_D0
);
477 if (err
< 0 && err
!= -EIO
)
479 err
= pcibios_enable_device(dev
, bars
);
486 * pci_enable_device - Initialize device before it's used by a driver.
487 * @dev: PCI device to be initialized
489 * Initialize device before it's used by a driver. Ask low-level code
490 * to enable I/O and memory. Wake up the device if it was suspended.
491 * Beware, this function can fail.
494 pci_enable_device(struct pci_dev
*dev
)
498 if ((err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1)))
500 pci_fixup_device(pci_fixup_enable
, dev
);
506 * pcibios_disable_device - disable arch specific PCI resources for device dev
507 * @dev: the PCI device to disable
509 * Disables architecture specific PCI resources for the device. This
510 * is the default implementation. Architecture implementations can
513 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
516 * pci_disable_device - Disable PCI device after use
517 * @dev: PCI device to be disabled
519 * Signal to the system that the PCI device is not in use by the system
520 * anymore. This only involves disabling PCI bus-mastering, if active.
523 pci_disable_device(struct pci_dev
*dev
)
527 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
528 if (pci_command
& PCI_COMMAND_MASTER
) {
529 pci_command
&= ~PCI_COMMAND_MASTER
;
530 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
532 dev
->is_busmaster
= 0;
534 pcibios_disable_device(dev
);
539 * pci_enable_wake - enable device to generate PME# when suspended
540 * @dev: - PCI device to operate on
541 * @state: - Current state of device.
542 * @enable: - Flag to enable or disable generation
544 * Set the bits in the device's PM Capabilities to generate PME# when
545 * the system is suspended.
547 * -EIO is returned if device doesn't have PM Capabilities.
548 * -EINVAL is returned if device supports it, but can't generate wake events.
549 * 0 if operation is successful.
552 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
557 /* find PCI PM capability in list */
558 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
560 /* If device doesn't support PM Capabilities, but request is to disable
561 * wake events, it's a nop; otherwise fail */
563 return enable
? -EIO
: 0;
565 /* Check device's ability to generate PME# */
566 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
568 value
&= PCI_PM_CAP_PME_MASK
;
569 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
571 /* Check if it can generate PME# from requested state. */
572 if (!value
|| !(value
& (1 << state
)))
573 return enable
? -EINVAL
: 0;
575 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
577 /* Clear PME_Status by writing 1 to it and enable PME# */
578 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
581 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
583 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
589 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
597 while (dev
->bus
->self
) {
598 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
599 dev
= dev
->bus
->self
;
606 * pci_release_region - Release a PCI bar
607 * @pdev: PCI device whose resources were previously reserved by pci_request_region
608 * @bar: BAR to release
610 * Releases the PCI I/O and memory resources previously reserved by a
611 * successful call to pci_request_region. Call this function only
612 * after all use of the PCI regions has ceased.
614 void pci_release_region(struct pci_dev
*pdev
, int bar
)
616 if (pci_resource_len(pdev
, bar
) == 0)
618 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
619 release_region(pci_resource_start(pdev
, bar
),
620 pci_resource_len(pdev
, bar
));
621 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
622 release_mem_region(pci_resource_start(pdev
, bar
),
623 pci_resource_len(pdev
, bar
));
627 * pci_request_region - Reserved PCI I/O and memory resource
628 * @pdev: PCI device whose resources are to be reserved
629 * @bar: BAR to be reserved
630 * @res_name: Name to be associated with resource.
632 * Mark the PCI region associated with PCI device @pdev BR @bar as
633 * being reserved by owner @res_name. Do not access any
634 * address inside the PCI regions unless this call returns
637 * Returns 0 on success, or %EBUSY on error. A warning
638 * message is also printed on failure.
640 int pci_request_region(struct pci_dev
*pdev
, int bar
, char *res_name
)
642 if (pci_resource_len(pdev
, bar
) == 0)
645 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
646 if (!request_region(pci_resource_start(pdev
, bar
),
647 pci_resource_len(pdev
, bar
), res_name
))
650 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
651 if (!request_mem_region(pci_resource_start(pdev
, bar
),
652 pci_resource_len(pdev
, bar
), res_name
))
659 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
660 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
661 bar
+ 1, /* PCI BAR # */
662 pci_resource_len(pdev
, bar
), pci_resource_start(pdev
, bar
),
669 * pci_release_regions - Release reserved PCI I/O and memory resources
670 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
672 * Releases all PCI I/O and memory resources previously reserved by a
673 * successful call to pci_request_regions. Call this function only
674 * after all use of the PCI regions has ceased.
677 void pci_release_regions(struct pci_dev
*pdev
)
681 for (i
= 0; i
< 6; i
++)
682 pci_release_region(pdev
, i
);
686 * pci_request_regions - Reserved PCI I/O and memory resources
687 * @pdev: PCI device whose resources are to be reserved
688 * @res_name: Name to be associated with resource.
690 * Mark all PCI regions associated with PCI device @pdev as
691 * being reserved by owner @res_name. Do not access any
692 * address inside the PCI regions unless this call returns
695 * Returns 0 on success, or %EBUSY on error. A warning
696 * message is also printed on failure.
698 int pci_request_regions(struct pci_dev
*pdev
, char *res_name
)
702 for (i
= 0; i
< 6; i
++)
703 if(pci_request_region(pdev
, i
, res_name
))
709 pci_release_region(pdev
, i
);
715 * pci_set_master - enables bus-mastering for device dev
716 * @dev: the PCI device to enable
718 * Enables bus-mastering on the device and calls pcibios_set_master()
719 * to do the needed arch specific settings.
722 pci_set_master(struct pci_dev
*dev
)
726 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
727 if (! (cmd
& PCI_COMMAND_MASTER
)) {
728 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
729 cmd
|= PCI_COMMAND_MASTER
;
730 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
732 dev
->is_busmaster
= 1;
733 pcibios_set_master(dev
);
736 #ifndef HAVE_ARCH_PCI_MWI
737 /* This can be overridden by arch code. */
738 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
741 * pci_generic_prep_mwi - helper function for pci_set_mwi
742 * @dev: the PCI device for which MWI is enabled
744 * Helper function for generic implementation of pcibios_prep_mwi
745 * function. Originally copied from drivers/net/acenic.c.
746 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
748 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
751 pci_generic_prep_mwi(struct pci_dev
*dev
)
755 if (!pci_cache_line_size
)
756 return -EINVAL
; /* The system doesn't support MWI. */
758 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
759 equal to or multiple of the right value. */
760 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
761 if (cacheline_size
>= pci_cache_line_size
&&
762 (cacheline_size
% pci_cache_line_size
) == 0)
765 /* Write the correct value. */
766 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
768 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
769 if (cacheline_size
== pci_cache_line_size
)
772 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
773 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
777 #endif /* !HAVE_ARCH_PCI_MWI */
780 * pci_set_mwi - enables memory-write-invalidate PCI transaction
781 * @dev: the PCI device for which MWI is enabled
783 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
784 * and then calls @pcibios_set_mwi to do the needed arch specific
785 * operations or a generic mwi-prep function.
787 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
790 pci_set_mwi(struct pci_dev
*dev
)
795 #ifdef HAVE_ARCH_PCI_MWI
796 rc
= pcibios_prep_mwi(dev
);
798 rc
= pci_generic_prep_mwi(dev
);
804 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
805 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
806 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
807 cmd
|= PCI_COMMAND_INVALIDATE
;
808 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
815 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
816 * @dev: the PCI device to disable
818 * Disables PCI Memory-Write-Invalidate transaction on the device
821 pci_clear_mwi(struct pci_dev
*dev
)
825 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
826 if (cmd
& PCI_COMMAND_INVALIDATE
) {
827 cmd
&= ~PCI_COMMAND_INVALIDATE
;
828 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
833 * pci_intx - enables/disables PCI INTx for device dev
834 * @pdev: the PCI device to operate on
835 * @enable: boolean: whether to enable or disable PCI INTx
837 * Enables/disables PCI INTx for device dev
840 pci_intx(struct pci_dev
*pdev
, int enable
)
842 u16 pci_command
, new;
844 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
847 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
849 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
852 if (new != pci_command
) {
853 pci_write_config_word(pdev
, PCI_COMMAND
, new);
857 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
859 * These can be overridden by arch-specific implementations
862 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
864 if (!pci_dma_supported(dev
, mask
))
867 dev
->dma_mask
= mask
;
873 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
875 if (!pci_dma_supported(dev
, mask
))
878 dev
->dev
.coherent_dma_mask
= mask
;
884 static int __devinit
pci_init(void)
886 struct pci_dev
*dev
= NULL
;
888 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
889 pci_fixup_device(pci_fixup_final
, dev
);
894 static int __devinit
pci_setup(char *str
)
897 char *k
= strchr(str
, ',');
900 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
901 /* PCI layer options should be handled here */
902 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
909 device_initcall(pci_init
);
911 __setup("pci=", pci_setup
);
913 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
914 /* FIXME: Some boxes have multiple ISA bridges! */
915 struct pci_dev
*isa_bridge
;
916 EXPORT_SYMBOL(isa_bridge
);
919 EXPORT_SYMBOL_GPL(pci_restore_bars
);
920 EXPORT_SYMBOL(pci_enable_device_bars
);
921 EXPORT_SYMBOL(pci_enable_device
);
922 EXPORT_SYMBOL(pci_disable_device
);
923 EXPORT_SYMBOL(pci_find_capability
);
924 EXPORT_SYMBOL(pci_bus_find_capability
);
925 EXPORT_SYMBOL(pci_release_regions
);
926 EXPORT_SYMBOL(pci_request_regions
);
927 EXPORT_SYMBOL(pci_release_region
);
928 EXPORT_SYMBOL(pci_request_region
);
929 EXPORT_SYMBOL(pci_set_master
);
930 EXPORT_SYMBOL(pci_set_mwi
);
931 EXPORT_SYMBOL(pci_clear_mwi
);
932 EXPORT_SYMBOL_GPL(pci_intx
);
933 EXPORT_SYMBOL(pci_set_dma_mask
);
934 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
935 EXPORT_SYMBOL(pci_assign_resource
);
936 EXPORT_SYMBOL(pci_find_parent_resource
);
938 EXPORT_SYMBOL(pci_set_power_state
);
939 EXPORT_SYMBOL(pci_save_state
);
940 EXPORT_SYMBOL(pci_restore_state
);
941 EXPORT_SYMBOL(pci_enable_wake
);
945 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
946 EXPORT_SYMBOL(pci_pci_problems
);