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[ALSA] powermac - Fix Oops when conflicting with aoa driver
[linux-2.6.22.y-op.git] / drivers / scsi / megaraid / megaraid_sas.h
blob3531a14222a737780f8574eae0e010a71c6fd137
1 /*
2 *
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
5 * Copyright (c) 2003-2005 LSI Logic Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * FILE : megaraid_sas.h
13 */
14
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
17
18 /**
19 * MegaRAID SAS Driver meta data
20 */
21 #define MEGASAS_VERSION "00.00.03.01"
22 #define MEGASAS_RELDATE "May 14, 2006"
23 #define MEGASAS_EXT_VERSION "Sun May 14 22:49:52 PDT 2006"
24
25 /*
26 * Device IDs
27 */
28 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
29 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
30
31 /*
32 * =====================================
33 * MegaRAID SAS MFI firmware definitions
34 * =====================================
35 */
36
37 /*
38 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
39 * protocol between the software and firmware. Commands are issued using
40 * "message frames"
41 */
42
43 /**
44 * FW posts its state in upper 4 bits of outbound_msg_0 register
45 */
46 #define MFI_STATE_MASK 0xF0000000
47 #define MFI_STATE_UNDEFINED 0x00000000
48 #define MFI_STATE_BB_INIT 0x10000000
49 #define MFI_STATE_FW_INIT 0x40000000
50 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
51 #define MFI_STATE_FW_INIT_2 0x70000000
52 #define MFI_STATE_DEVICE_SCAN 0x80000000
53 #define MFI_STATE_FLUSH_CACHE 0xA0000000
54 #define MFI_STATE_READY 0xB0000000
55 #define MFI_STATE_OPERATIONAL 0xC0000000
56 #define MFI_STATE_FAULT 0xF0000000
57
58 #define MEGAMFI_FRAME_SIZE 64
59
60 /**
61 * During FW init, clear pending cmds & reset state using inbound_msg_0
62 *
63 * ABORT : Abort all pending cmds
64 * READY : Move from OPERATIONAL to READY state; discard queue info
65 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
66 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
67 */
68 #define MFI_INIT_ABORT 0x00000000
69 #define MFI_INIT_READY 0x00000002
70 #define MFI_INIT_MFIMODE 0x00000004
71 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
72 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE
73
74 /**
75 * MFI frame flags
76 */
77 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
78 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
79 #define MFI_FRAME_SGL32 0x0000
80 #define MFI_FRAME_SGL64 0x0002
81 #define MFI_FRAME_SENSE32 0x0000
82 #define MFI_FRAME_SENSE64 0x0004
83 #define MFI_FRAME_DIR_NONE 0x0000
84 #define MFI_FRAME_DIR_WRITE 0x0008
85 #define MFI_FRAME_DIR_READ 0x0010
86 #define MFI_FRAME_DIR_BOTH 0x0018
87
88 /**
89 * Definition for cmd_status
90 */
91 #define MFI_CMD_STATUS_POLL_MODE 0xFF
92
93 /**
94 * MFI command opcodes
95 */
96 #define MFI_CMD_INIT 0x00
97 #define MFI_CMD_LD_READ 0x01
98 #define MFI_CMD_LD_WRITE 0x02
99 #define MFI_CMD_LD_SCSI_IO 0x03
100 #define MFI_CMD_PD_SCSI_IO 0x04
101 #define MFI_CMD_DCMD 0x05
102 #define MFI_CMD_ABORT 0x06
103 #define MFI_CMD_SMP 0x07
104 #define MFI_CMD_STP 0x08
105
106 #define MR_DCMD_CTRL_GET_INFO 0x01010000
107
108 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
109 #define MR_FLUSH_CTRL_CACHE 0x01
110 #define MR_FLUSH_DISK_CACHE 0x02
111
112 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
113 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
114
115 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
116 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
117 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
118 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
119
120 #define MR_DCMD_CLUSTER 0x08000000
121 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
122 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
123
124 /**
125 * MFI command completion codes
126 */
127 enum MFI_STAT {
128 MFI_STAT_OK = 0x00,
129 MFI_STAT_INVALID_CMD = 0x01,
130 MFI_STAT_INVALID_DCMD = 0x02,
131 MFI_STAT_INVALID_PARAMETER = 0x03,
132 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
133 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
134 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
135 MFI_STAT_APP_IN_USE = 0x07,
136 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
137 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
138 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
139 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
140 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
141 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
142 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
143 MFI_STAT_FLASH_BUSY = 0x0f,
144 MFI_STAT_FLASH_ERROR = 0x10,
145 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
146 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
147 MFI_STAT_FLASH_NOT_OPEN = 0x13,
148 MFI_STAT_FLASH_NOT_STARTED = 0x14,
149 MFI_STAT_FLUSH_FAILED = 0x15,
150 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
151 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
152 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
153 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
154 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
155 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
156 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
157 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
158 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
159 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
160 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
161 MFI_STAT_MFC_HW_ERROR = 0x21,
162 MFI_STAT_NO_HW_PRESENT = 0x22,
163 MFI_STAT_NOT_FOUND = 0x23,
164 MFI_STAT_NOT_IN_ENCL = 0x24,
165 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
166 MFI_STAT_PD_TYPE_WRONG = 0x26,
167 MFI_STAT_PR_DISABLED = 0x27,
168 MFI_STAT_ROW_INDEX_INVALID = 0x28,
169 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
170 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
171 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
172 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
173 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
174 MFI_STAT_SCSI_IO_FAILED = 0x2e,
175 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
176 MFI_STAT_SHUTDOWN_FAILED = 0x30,
177 MFI_STAT_TIME_NOT_SET = 0x31,
178 MFI_STAT_WRONG_STATE = 0x32,
179 MFI_STAT_LD_OFFLINE = 0x33,
180 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
181 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
182 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
183 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
184 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
185
186 MFI_STAT_INVALID_STATUS = 0xFF
187 };
188
189 /*
190 * Number of mailbox bytes in DCMD message frame
191 */
192 #define MFI_MBOX_SIZE 12
193
194 enum MR_EVT_CLASS {
195
196 MR_EVT_CLASS_DEBUG = -2,
197 MR_EVT_CLASS_PROGRESS = -1,
198 MR_EVT_CLASS_INFO = 0,
199 MR_EVT_CLASS_WARNING = 1,
200 MR_EVT_CLASS_CRITICAL = 2,
201 MR_EVT_CLASS_FATAL = 3,
202 MR_EVT_CLASS_DEAD = 4,
203
204 };
205
206 enum MR_EVT_LOCALE {
207
208 MR_EVT_LOCALE_LD = 0x0001,
209 MR_EVT_LOCALE_PD = 0x0002,
210 MR_EVT_LOCALE_ENCL = 0x0004,
211 MR_EVT_LOCALE_BBU = 0x0008,
212 MR_EVT_LOCALE_SAS = 0x0010,
213 MR_EVT_LOCALE_CTRL = 0x0020,
214 MR_EVT_LOCALE_CONFIG = 0x0040,
215 MR_EVT_LOCALE_CLUSTER = 0x0080,
216 MR_EVT_LOCALE_ALL = 0xffff,
217
218 };
219
220 enum MR_EVT_ARGS {
221
222 MR_EVT_ARGS_NONE,
223 MR_EVT_ARGS_CDB_SENSE,
224 MR_EVT_ARGS_LD,
225 MR_EVT_ARGS_LD_COUNT,
226 MR_EVT_ARGS_LD_LBA,
227 MR_EVT_ARGS_LD_OWNER,
228 MR_EVT_ARGS_LD_LBA_PD_LBA,
229 MR_EVT_ARGS_LD_PROG,
230 MR_EVT_ARGS_LD_STATE,
231 MR_EVT_ARGS_LD_STRIP,
232 MR_EVT_ARGS_PD,
233 MR_EVT_ARGS_PD_ERR,
234 MR_EVT_ARGS_PD_LBA,
235 MR_EVT_ARGS_PD_LBA_LD,
236 MR_EVT_ARGS_PD_PROG,
237 MR_EVT_ARGS_PD_STATE,
238 MR_EVT_ARGS_PCI,
239 MR_EVT_ARGS_RATE,
240 MR_EVT_ARGS_STR,
241 MR_EVT_ARGS_TIME,
242 MR_EVT_ARGS_ECC,
243
244 };
245
246 /*
247 * SAS controller properties
248 */
249 struct megasas_ctrl_prop {
250
251 u16 seq_num;
252 u16 pred_fail_poll_interval;
253 u16 intr_throttle_count;
254 u16 intr_throttle_timeouts;
255 u8 rebuild_rate;
256 u8 patrol_read_rate;
257 u8 bgi_rate;
258 u8 cc_rate;
259 u8 recon_rate;
260 u8 cache_flush_interval;
261 u8 spinup_drv_count;
262 u8 spinup_delay;
263 u8 cluster_enable;
264 u8 coercion_mode;
265 u8 alarm_enable;
266 u8 disable_auto_rebuild;
267 u8 disable_battery_warn;
268 u8 ecc_bucket_size;
269 u16 ecc_bucket_leak_rate;
270 u8 restore_hotspare_on_insertion;
271 u8 expose_encl_devices;
272 u8 reserved[38];
273
274 } __attribute__ ((packed));
275
276 /*
277 * SAS controller information
278 */
279 struct megasas_ctrl_info {
280
281 /*
282 * PCI device information
283 */
284 struct {
285
286 u16 vendor_id;
287 u16 device_id;
288 u16 sub_vendor_id;
289 u16 sub_device_id;
290 u8 reserved[24];
291
292 } __attribute__ ((packed)) pci;
293
294 /*
295 * Host interface information
296 */
297 struct {
298
299 u8 PCIX:1;
300 u8 PCIE:1;
301 u8 iSCSI:1;
302 u8 SAS_3G:1;
303 u8 reserved_0:4;
304 u8 reserved_1[6];
305 u8 port_count;
306 u64 port_addr[8];
307
308 } __attribute__ ((packed)) host_interface;
309
310 /*
311 * Device (backend) interface information
312 */
313 struct {
314
315 u8 SPI:1;
316 u8 SAS_3G:1;
317 u8 SATA_1_5G:1;
318 u8 SATA_3G:1;
319 u8 reserved_0:4;
320 u8 reserved_1[6];
321 u8 port_count;
322 u64 port_addr[8];
323
324 } __attribute__ ((packed)) device_interface;
325
326 /*
327 * List of components residing in flash. All str are null terminated
328 */
329 u32 image_check_word;
330 u32 image_component_count;
331
332 struct {
333
334 char name[8];
335 char version[32];
336 char build_date[16];
337 char built_time[16];
338
339 } __attribute__ ((packed)) image_component[8];
340
341 /*
342 * List of flash components that have been flashed on the card, but
343 * are not in use, pending reset of the adapter. This list will be
344 * empty if a flash operation has not occurred. All stings are null
345 * terminated
346 */
347 u32 pending_image_component_count;
348
349 struct {
350
351 char name[8];
352 char version[32];
353 char build_date[16];
354 char build_time[16];
355
356 } __attribute__ ((packed)) pending_image_component[8];
357
358 u8 max_arms;
359 u8 max_spans;
360 u8 max_arrays;
361 u8 max_lds;
362
363 char product_name[80];
364 char serial_no[32];
365
366 /*
367 * Other physical/controller/operation information. Indicates the
368 * presence of the hardware
369 */
370 struct {
371
372 u32 bbu:1;
373 u32 alarm:1;
374 u32 nvram:1;
375 u32 uart:1;
376 u32 reserved:28;
377
378 } __attribute__ ((packed)) hw_present;
379
380 u32 current_fw_time;
381
382 /*
383 * Maximum data transfer sizes
384 */
385 u16 max_concurrent_cmds;
386 u16 max_sge_count;
387 u32 max_request_size;
388
389 /*
390 * Logical and physical device counts
391 */
392 u16 ld_present_count;
393 u16 ld_degraded_count;
394 u16 ld_offline_count;
395
396 u16 pd_present_count;
397 u16 pd_disk_present_count;
398 u16 pd_disk_pred_failure_count;
399 u16 pd_disk_failed_count;
400
401 /*
402 * Memory size information
403 */
404 u16 nvram_size;
405 u16 memory_size;
406 u16 flash_size;
407
408 /*
409 * Error counters
410 */
411 u16 mem_correctable_error_count;
412 u16 mem_uncorrectable_error_count;
413
414 /*
415 * Cluster information
416 */
417 u8 cluster_permitted;
418 u8 cluster_active;
419
420 /*
421 * Additional max data transfer sizes
422 */
423 u16 max_strips_per_io;
424
425 /*
426 * Controller capabilities structures
427 */
428 struct {
429
430 u32 raid_level_0:1;
431 u32 raid_level_1:1;
432 u32 raid_level_5:1;
433 u32 raid_level_1E:1;
434 u32 raid_level_6:1;
435 u32 reserved:27;
436
437 } __attribute__ ((packed)) raid_levels;
438
439 struct {
440
441 u32 rbld_rate:1;
442 u32 cc_rate:1;
443 u32 bgi_rate:1;
444 u32 recon_rate:1;
445 u32 patrol_rate:1;
446 u32 alarm_control:1;
447 u32 cluster_supported:1;
448 u32 bbu:1;
449 u32 spanning_allowed:1;
450 u32 dedicated_hotspares:1;
451 u32 revertible_hotspares:1;
452 u32 foreign_config_import:1;
453 u32 self_diagnostic:1;
454 u32 mixed_redundancy_arr:1;
455 u32 global_hot_spares:1;
456 u32 reserved:17;
457
458 } __attribute__ ((packed)) adapter_operations;
459
460 struct {
461
462 u32 read_policy:1;
463 u32 write_policy:1;
464 u32 io_policy:1;
465 u32 access_policy:1;
466 u32 disk_cache_policy:1;
467 u32 reserved:27;
468
469 } __attribute__ ((packed)) ld_operations;
470
471 struct {
472
473 u8 min;
474 u8 max;
475 u8 reserved[2];
476
477 } __attribute__ ((packed)) stripe_sz_ops;
478
479 struct {
480
481 u32 force_online:1;
482 u32 force_offline:1;
483 u32 force_rebuild:1;
484 u32 reserved:29;
485
486 } __attribute__ ((packed)) pd_operations;
487
488 struct {
489
490 u32 ctrl_supports_sas:1;
491 u32 ctrl_supports_sata:1;
492 u32 allow_mix_in_encl:1;
493 u32 allow_mix_in_ld:1;
494 u32 allow_sata_in_cluster:1;
495 u32 reserved:27;
496
497 } __attribute__ ((packed)) pd_mix_support;
498
499 /*
500 * Define ECC single-bit-error bucket information
501 */
502 u8 ecc_bucket_count;
503 u8 reserved_2[11];
504
505 /*
506 * Include the controller properties (changeable items)
507 */
508 struct megasas_ctrl_prop properties;
509
510 /*
511 * Define FW pkg version (set in envt v'bles on OEM basis)
512 */
513 char package_version[0x60];
514
515 u8 pad[0x800 - 0x6a0];
516
517 } __attribute__ ((packed));
518
519 /*
520 * ===============================
521 * MegaRAID SAS driver definitions
522 * ===============================
523 */
524 #define MEGASAS_MAX_PD_CHANNELS 2
525 #define MEGASAS_MAX_LD_CHANNELS 2
526 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
527 MEGASAS_MAX_LD_CHANNELS)
528 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
529 #define MEGASAS_DEFAULT_INIT_ID -1
530 #define MEGASAS_MAX_LUN 8
531 #define MEGASAS_MAX_LD 64
532
533 /*
534 * When SCSI mid-layer calls driver's reset routine, driver waits for
535 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
536 * that the driver cannot _actually_ abort or reset pending commands. While
537 * it is waiting for the commands to complete, it prints a diagnostic message
538 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
539 */
540 #define MEGASAS_RESET_WAIT_TIME 180
541 #define MEGASAS_RESET_NOTICE_INTERVAL 5
542
543 #define MEGASAS_IOCTL_CMD 0
544
545 /*
546 * FW reports the maximum of number of commands that it can accept (maximum
547 * commands that can be outstanding) at any time. The driver must report a
548 * lower number to the mid layer because it can issue a few internal commands
549 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
550 * is shown below
551 */
552 #define MEGASAS_INT_CMDS 32
553
554 /*
555 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
556 * SGLs based on the size of dma_addr_t
557 */
558 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
559
560 #define MFI_OB_INTR_STATUS_MASK 0x00000002
561 #define MFI_POLL_TIMEOUT_SECS 10
562
563 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
564
565 /*
566 * register set for both 1068 and 1078 controllers
567 * structure extended for 1078 registers
568 */
569
570 struct megasas_register_set {
571 u32 reserved_0[4]; /*0000h*/
572
573 u32 inbound_msg_0; /*0010h*/
574 u32 inbound_msg_1; /*0014h*/
575 u32 outbound_msg_0; /*0018h*/
576 u32 outbound_msg_1; /*001Ch*/
577
578 u32 inbound_doorbell; /*0020h*/
579 u32 inbound_intr_status; /*0024h*/
580 u32 inbound_intr_mask; /*0028h*/
581
582 u32 outbound_doorbell; /*002Ch*/
583 u32 outbound_intr_status; /*0030h*/
584 u32 outbound_intr_mask; /*0034h*/
585
586 u32 reserved_1[2]; /*0038h*/
587
588 u32 inbound_queue_port; /*0040h*/
589 u32 outbound_queue_port; /*0044h*/
590
591 u32 reserved_2[22]; /*0048h*/
592
593 u32 outbound_doorbell_clear; /*00A0h*/
594
595 u32 reserved_3[3]; /*00A4h*/
596
597 u32 outbound_scratch_pad ; /*00B0h*/
598
599 u32 reserved_4[3]; /*00B4h*/
600
601 u32 inbound_low_queue_port ; /*00C0h*/
602
603 u32 inbound_high_queue_port ; /*00C4h*/
604
605 u32 reserved_5; /*00C8h*/
606 u32 index_registers[820]; /*00CCh*/
607
608 } __attribute__ ((packed));
609
610 struct megasas_sge32 {
611
612 u32 phys_addr;
613 u32 length;
614
615 } __attribute__ ((packed));
616
617 struct megasas_sge64 {
618
619 u64 phys_addr;
620 u32 length;
621
622 } __attribute__ ((packed));
623
624 union megasas_sgl {
625
626 struct megasas_sge32 sge32[1];
627 struct megasas_sge64 sge64[1];
628
629 } __attribute__ ((packed));
630
631 struct megasas_header {
632
633 u8 cmd; /*00h */
634 u8 sense_len; /*01h */
635 u8 cmd_status; /*02h */
636 u8 scsi_status; /*03h */
637
638 u8 target_id; /*04h */
639 u8 lun; /*05h */
640 u8 cdb_len; /*06h */
641 u8 sge_count; /*07h */
642
643 u32 context; /*08h */
644 u32 pad_0; /*0Ch */
645
646 u16 flags; /*10h */
647 u16 timeout; /*12h */
648 u32 data_xferlen; /*14h */
649
650 } __attribute__ ((packed));
651
652 union megasas_sgl_frame {
653
654 struct megasas_sge32 sge32[8];
655 struct megasas_sge64 sge64[5];
656
657 } __attribute__ ((packed));
658
659 struct megasas_init_frame {
660
661 u8 cmd; /*00h */
662 u8 reserved_0; /*01h */
663 u8 cmd_status; /*02h */
664
665 u8 reserved_1; /*03h */
666 u32 reserved_2; /*04h */
667
668 u32 context; /*08h */
669 u32 pad_0; /*0Ch */
670
671 u16 flags; /*10h */
672 u16 reserved_3; /*12h */
673 u32 data_xfer_len; /*14h */
674
675 u32 queue_info_new_phys_addr_lo; /*18h */
676 u32 queue_info_new_phys_addr_hi; /*1Ch */
677 u32 queue_info_old_phys_addr_lo; /*20h */
678 u32 queue_info_old_phys_addr_hi; /*24h */
679
680 u32 reserved_4[6]; /*28h */
681
682 } __attribute__ ((packed));
683
684 struct megasas_init_queue_info {
685
686 u32 init_flags; /*00h */
687 u32 reply_queue_entries; /*04h */
688
689 u32 reply_queue_start_phys_addr_lo; /*08h */
690 u32 reply_queue_start_phys_addr_hi; /*0Ch */
691 u32 producer_index_phys_addr_lo; /*10h */
692 u32 producer_index_phys_addr_hi; /*14h */
693 u32 consumer_index_phys_addr_lo; /*18h */
694 u32 consumer_index_phys_addr_hi; /*1Ch */
695
696 } __attribute__ ((packed));
697
698 struct megasas_io_frame {
699
700 u8 cmd; /*00h */
701 u8 sense_len; /*01h */
702 u8 cmd_status; /*02h */
703 u8 scsi_status; /*03h */
704
705 u8 target_id; /*04h */
706 u8 access_byte; /*05h */
707 u8 reserved_0; /*06h */
708 u8 sge_count; /*07h */
709
710 u32 context; /*08h */
711 u32 pad_0; /*0Ch */
712
713 u16 flags; /*10h */
714 u16 timeout; /*12h */
715 u32 lba_count; /*14h */
716
717 u32 sense_buf_phys_addr_lo; /*18h */
718 u32 sense_buf_phys_addr_hi; /*1Ch */
719
720 u32 start_lba_lo; /*20h */
721 u32 start_lba_hi; /*24h */
722
723 union megasas_sgl sgl; /*28h */
724
725 } __attribute__ ((packed));
726
727 struct megasas_pthru_frame {
728
729 u8 cmd; /*00h */
730 u8 sense_len; /*01h */
731 u8 cmd_status; /*02h */
732 u8 scsi_status; /*03h */
733
734 u8 target_id; /*04h */
735 u8 lun; /*05h */
736 u8 cdb_len; /*06h */
737 u8 sge_count; /*07h */
738
739 u32 context; /*08h */
740 u32 pad_0; /*0Ch */
741
742 u16 flags; /*10h */
743 u16 timeout; /*12h */
744 u32 data_xfer_len; /*14h */
745
746 u32 sense_buf_phys_addr_lo; /*18h */
747 u32 sense_buf_phys_addr_hi; /*1Ch */
748
749 u8 cdb[16]; /*20h */
750 union megasas_sgl sgl; /*30h */
751
752 } __attribute__ ((packed));
753
754 struct megasas_dcmd_frame {
755
756 u8 cmd; /*00h */
757 u8 reserved_0; /*01h */
758 u8 cmd_status; /*02h */
759 u8 reserved_1[4]; /*03h */
760 u8 sge_count; /*07h */
761
762 u32 context; /*08h */
763 u32 pad_0; /*0Ch */
764
765 u16 flags; /*10h */
766 u16 timeout; /*12h */
767
768 u32 data_xfer_len; /*14h */
769 u32 opcode; /*18h */
770
771 union { /*1Ch */
772 u8 b[12];
773 u16 s[6];
774 u32 w[3];
775 } mbox;
776
777 union megasas_sgl sgl; /*28h */
778
779 } __attribute__ ((packed));
780
781 struct megasas_abort_frame {
782
783 u8 cmd; /*00h */
784 u8 reserved_0; /*01h */
785 u8 cmd_status; /*02h */
786
787 u8 reserved_1; /*03h */
788 u32 reserved_2; /*04h */
789
790 u32 context; /*08h */
791 u32 pad_0; /*0Ch */
792
793 u16 flags; /*10h */
794 u16 reserved_3; /*12h */
795 u32 reserved_4; /*14h */
796
797 u32 abort_context; /*18h */
798 u32 pad_1; /*1Ch */
799
800 u32 abort_mfi_phys_addr_lo; /*20h */
801 u32 abort_mfi_phys_addr_hi; /*24h */
802
803 u32 reserved_5[6]; /*28h */
804
805 } __attribute__ ((packed));
806
807 struct megasas_smp_frame {
808
809 u8 cmd; /*00h */
810 u8 reserved_1; /*01h */
811 u8 cmd_status; /*02h */
812 u8 connection_status; /*03h */
813
814 u8 reserved_2[3]; /*04h */
815 u8 sge_count; /*07h */
816
817 u32 context; /*08h */
818 u32 pad_0; /*0Ch */
819
820 u16 flags; /*10h */
821 u16 timeout; /*12h */
822
823 u32 data_xfer_len; /*14h */
824 u64 sas_addr; /*18h */
825
826 union {
827 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
828 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
829 } sgl;
830
831 } __attribute__ ((packed));
832
833 struct megasas_stp_frame {
834
835 u8 cmd; /*00h */
836 u8 reserved_1; /*01h */
837 u8 cmd_status; /*02h */
838 u8 reserved_2; /*03h */
839
840 u8 target_id; /*04h */
841 u8 reserved_3[2]; /*05h */
842 u8 sge_count; /*07h */
843
844 u32 context; /*08h */
845 u32 pad_0; /*0Ch */
846
847 u16 flags; /*10h */
848 u16 timeout; /*12h */
849
850 u32 data_xfer_len; /*14h */
851
852 u16 fis[10]; /*18h */
853 u32 stp_flags;
854
855 union {
856 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
857 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
858 } sgl;
859
860 } __attribute__ ((packed));
861
862 union megasas_frame {
863
864 struct megasas_header hdr;
865 struct megasas_init_frame init;
866 struct megasas_io_frame io;
867 struct megasas_pthru_frame pthru;
868 struct megasas_dcmd_frame dcmd;
869 struct megasas_abort_frame abort;
870 struct megasas_smp_frame smp;
871 struct megasas_stp_frame stp;
872
873 u8 raw_bytes[64];
874 };
875
876 struct megasas_cmd;
877
878 union megasas_evt_class_locale {
879
880 struct {
881 u16 locale;
882 u8 reserved;
883 s8 class;
884 } __attribute__ ((packed)) members;
885
886 u32 word;
887
888 } __attribute__ ((packed));
889
890 struct megasas_evt_log_info {
891 u32 newest_seq_num;
892 u32 oldest_seq_num;
893 u32 clear_seq_num;
894 u32 shutdown_seq_num;
895 u32 boot_seq_num;
896
897 } __attribute__ ((packed));
898
899 struct megasas_progress {
900
901 u16 progress;
902 u16 elapsed_seconds;
903
904 } __attribute__ ((packed));
905
906 struct megasas_evtarg_ld {
907
908 u16 target_id;
909 u8 ld_index;
910 u8 reserved;
911
912 } __attribute__ ((packed));
913
914 struct megasas_evtarg_pd {
915 u16 device_id;
916 u8 encl_index;
917 u8 slot_number;
918
919 } __attribute__ ((packed));
920
921 struct megasas_evt_detail {
922
923 u32 seq_num;
924 u32 time_stamp;
925 u32 code;
926 union megasas_evt_class_locale cl;
927 u8 arg_type;
928 u8 reserved1[15];
929
930 union {
931 struct {
932 struct megasas_evtarg_pd pd;
933 u8 cdb_length;
934 u8 sense_length;
935 u8 reserved[2];
936 u8 cdb[16];
937 u8 sense[64];
938 } __attribute__ ((packed)) cdbSense;
939
940 struct megasas_evtarg_ld ld;
941
942 struct {
943 struct megasas_evtarg_ld ld;
944 u64 count;
945 } __attribute__ ((packed)) ld_count;
946
947 struct {
948 u64 lba;
949 struct megasas_evtarg_ld ld;
950 } __attribute__ ((packed)) ld_lba;
951
952 struct {
953 struct megasas_evtarg_ld ld;
954 u32 prevOwner;
955 u32 newOwner;
956 } __attribute__ ((packed)) ld_owner;
957
958 struct {
959 u64 ld_lba;
960 u64 pd_lba;
961 struct megasas_evtarg_ld ld;
962 struct megasas_evtarg_pd pd;
963 } __attribute__ ((packed)) ld_lba_pd_lba;
964
965 struct {
966 struct megasas_evtarg_ld ld;
967 struct megasas_progress prog;
968 } __attribute__ ((packed)) ld_prog;
969
970 struct {
971 struct megasas_evtarg_ld ld;
972 u32 prev_state;
973 u32 new_state;
974 } __attribute__ ((packed)) ld_state;
975
976 struct {
977 u64 strip;
978 struct megasas_evtarg_ld ld;
979 } __attribute__ ((packed)) ld_strip;
980
981 struct megasas_evtarg_pd pd;
982
983 struct {
984 struct megasas_evtarg_pd pd;
985 u32 err;
986 } __attribute__ ((packed)) pd_err;
987
988 struct {
989 u64 lba;
990 struct megasas_evtarg_pd pd;
991 } __attribute__ ((packed)) pd_lba;
992
993 struct {
994 u64 lba;
995 struct megasas_evtarg_pd pd;
996 struct megasas_evtarg_ld ld;
997 } __attribute__ ((packed)) pd_lba_ld;
998
999 struct {
1000 struct megasas_evtarg_pd pd;
1001 struct megasas_progress prog;
1002 } __attribute__ ((packed)) pd_prog;
1003
1004 struct {
1005 struct megasas_evtarg_pd pd;
1006 u32 prevState;
1007 u32 newState;
1008 } __attribute__ ((packed)) pd_state;
1009
1010 struct {
1011 u16 vendorId;
1012 u16 deviceId;
1013 u16 subVendorId;
1014 u16 subDeviceId;
1015 } __attribute__ ((packed)) pci;
1016
1017 u32 rate;
1018 char str[96];
1019
1020 struct {
1021 u32 rtc;
1022 u32 elapsedSeconds;
1023 } __attribute__ ((packed)) time;
1024
1025 struct {
1026 u32 ecar;
1027 u32 elog;
1028 char str[64];
1029 } __attribute__ ((packed)) ecc;
1030
1031 u8 b[96];
1032 u16 s[48];
1033 u32 w[24];
1034 u64 d[12];
1035 } args;
1036
1037 char description[128];
1038
1039 } __attribute__ ((packed));
1040
1041 struct megasas_instance_template {
1042 void (*fire_cmd)(dma_addr_t ,u32 ,struct megasas_register_set __iomem *);
1043
1044 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1045
1046 int (*clear_intr)(struct megasas_register_set __iomem *);
1047
1048 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1049 };
1050
1051 struct megasas_instance {
1052
1053 u32 *producer;
1054 dma_addr_t producer_h;
1055 u32 *consumer;
1056 dma_addr_t consumer_h;
1057
1058 u32 *reply_queue;
1059 dma_addr_t reply_queue_h;
1060
1061 unsigned long base_addr;
1062 struct megasas_register_set __iomem *reg_set;
1063
1064 s8 init_id;
1065 u8 reserved[3];
1066
1067 u16 max_num_sge;
1068 u16 max_fw_cmds;
1069 u32 max_sectors_per_req;
1070
1071 struct megasas_cmd **cmd_list;
1072 struct list_head cmd_pool;
1073 spinlock_t cmd_pool_lock;
1074 struct dma_pool *frame_dma_pool;
1075 struct dma_pool *sense_dma_pool;
1076
1077 struct megasas_evt_detail *evt_detail;
1078 dma_addr_t evt_detail_h;
1079 struct megasas_cmd *aen_cmd;
1080 struct semaphore aen_mutex;
1081 struct semaphore ioctl_sem;
1082
1083 struct Scsi_Host *host;
1084
1085 wait_queue_head_t int_cmd_wait_q;
1086 wait_queue_head_t abort_cmd_wait_q;
1087
1088 struct pci_dev *pdev;
1089 u32 unique_id;
1090
1091 atomic_t fw_outstanding;
1092 u32 hw_crit_error;
1093
1094 struct megasas_instance_template *instancet;
1095 };
1096
1097 #define MEGASAS_IS_LOGICAL(scp) \
1098 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1099
1100 #define MEGASAS_DEV_INDEX(inst, scp) \
1101 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1102 scp->device->id
1103
1104 struct megasas_cmd {
1105
1106 union megasas_frame *frame;
1107 dma_addr_t frame_phys_addr;
1108 u8 *sense;
1109 dma_addr_t sense_phys_addr;
1110
1111 u32 index;
1112 u8 sync_cmd;
1113 u8 cmd_status;
1114 u16 abort_aen;
1115
1116 struct list_head list;
1117 struct scsi_cmnd *scmd;
1118 struct megasas_instance *instance;
1119 u32 frame_count;
1120 };
1121
1122 #define MAX_MGMT_ADAPTERS 1024
1123 #define MAX_IOCTL_SGE 16
1124
1125 struct megasas_iocpacket {
1126
1127 u16 host_no;
1128 u16 __pad1;
1129 u32 sgl_off;
1130 u32 sge_count;
1131 u32 sense_off;
1132 u32 sense_len;
1133 union {
1134 u8 raw[128];
1135 struct megasas_header hdr;
1136 } frame;
1137
1138 struct iovec sgl[MAX_IOCTL_SGE];
1139
1140 } __attribute__ ((packed));
1141
1142 struct megasas_aen {
1143 u16 host_no;
1144 u16 __pad1;
1145 u32 seq_num;
1146 u32 class_locale_word;
1147 } __attribute__ ((packed));
1148
1149 #ifdef CONFIG_COMPAT
1150 struct compat_megasas_iocpacket {
1151 u16 host_no;
1152 u16 __pad1;
1153 u32 sgl_off;
1154 u32 sge_count;
1155 u32 sense_off;
1156 u32 sense_len;
1157 union {
1158 u8 raw[128];
1159 struct megasas_header hdr;
1160 } frame;
1161 struct compat_iovec sgl[MAX_IOCTL_SGE];
1162 } __attribute__ ((packed));
1163
1164 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1165 #endif
1166
1167 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1168 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1169
1170 struct megasas_mgmt_info {
1171
1172 u16 count;
1173 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1174 int max_index;
1175 };
1176
1177 #endif /*LSI_MEGARAID_SAS_H */
linux v2.6.22.y-op