Fix dnotify/close race
[linux-2.6.22.y-op.git] / drivers / net / fec.c
blob255b09124e1120c6c3be9306eaadac0ef1740f48
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/ptrace.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
46 #include <asm/irq.h>
47 #include <asm/uaccess.h>
48 #include <asm/io.h>
49 #include <asm/pgtable.h>
51 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
52 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
53 defined(CONFIG_M520x) || defined(CONFIG_M532x)
54 #include <asm/coldfire.h>
55 #include <asm/mcfsim.h>
56 #include "fec.h"
57 #else
58 #include <asm/8xx_immap.h>
59 #include <asm/mpc8xx.h>
60 #include "commproc.h"
61 #endif
63 #if defined(CONFIG_FEC2)
64 #define FEC_MAX_PORTS 2
65 #else
66 #define FEC_MAX_PORTS 1
67 #endif
70 * Define the fixed address of the FEC hardware.
72 static unsigned int fec_hw[] = {
73 #if defined(CONFIG_M5272)
74 (MCF_MBAR + 0x840),
75 #elif defined(CONFIG_M527x)
76 (MCF_MBAR + 0x1000),
77 (MCF_MBAR + 0x1800),
78 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
79 (MCF_MBAR + 0x1000),
80 #elif defined(CONFIG_M520x)
81 (MCF_MBAR+0x30000),
82 #elif defined(CONFIG_M532x)
83 (MCF_MBAR+0xfc030000),
84 #else
85 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
86 #endif
89 static unsigned char fec_mac_default[] = {
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
94 * Some hardware gets it MAC address out of local flash memory.
95 * if this is non-zero then assume it is the address to get MAC from.
97 #if defined(CONFIG_NETtel)
98 #define FEC_FLASHMAC 0xf0006006
99 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
100 #define FEC_FLASHMAC 0xf0006000
101 #elif defined (CONFIG_MTD_KeyTechnology)
102 #define FEC_FLASHMAC 0xffe04000
103 #elif defined(CONFIG_CANCam)
104 #define FEC_FLASHMAC 0xf0020000
105 #elif defined (CONFIG_M5272C3)
106 #define FEC_FLASHMAC (0xffe04000 + 4)
107 #elif defined(CONFIG_MOD5272)
108 #define FEC_FLASHMAC 0xffc0406b
109 #else
110 #define FEC_FLASHMAC 0
111 #endif
113 /* Forward declarations of some structures to support different PHYs
116 typedef struct {
117 uint mii_data;
118 void (*funct)(uint mii_reg, struct net_device *dev);
119 } phy_cmd_t;
121 typedef struct {
122 uint id;
123 char *name;
125 const phy_cmd_t *config;
126 const phy_cmd_t *startup;
127 const phy_cmd_t *ack_int;
128 const phy_cmd_t *shutdown;
129 } phy_info_t;
131 /* The number of Tx and Rx buffers. These are allocated from the page
132 * pool. The code may assume these are power of two, so it it best
133 * to keep them that size.
134 * We don't need to allocate pages for the transmitter. We just use
135 * the skbuffer directly.
137 #define FEC_ENET_RX_PAGES 8
138 #define FEC_ENET_RX_FRSIZE 2048
139 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
140 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
141 #define FEC_ENET_TX_FRSIZE 2048
142 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
143 #define TX_RING_SIZE 16 /* Must be power of two */
144 #define TX_RING_MOD_MASK 15 /* for this to work */
146 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
147 #error "FEC: descriptor ring size constants too large"
148 #endif
150 /* Interrupt events/masks.
152 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
153 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
154 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
155 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
156 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
157 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
158 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
159 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
160 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
161 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
163 /* The FEC stores dest/src/type, data, and checksum for receive packets.
165 #define PKT_MAXBUF_SIZE 1518
166 #define PKT_MINBUF_SIZE 64
167 #define PKT_MAXBLR_SIZE 1520
171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
176 defined(CONFIG_M520x) || defined(CONFIG_M532x)
177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
178 #else
179 #define OPT_FRAME_SIZE 0
180 #endif
182 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
183 * tx_bd_base always point to the base of the buffer descriptors. The
184 * cur_rx and cur_tx point to the currently available buffer.
185 * The dirty_tx tracks the current buffer that is being sent by the
186 * controller. The cur_tx and dirty_tx are equal under both completely
187 * empty and completely full conditions. The empty/ready indicator in
188 * the buffer descriptor determines the actual condition.
190 struct fec_enet_private {
191 /* Hardware registers of the FEC device */
192 volatile fec_t *hwp;
194 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
195 unsigned char *tx_bounce[TX_RING_SIZE];
196 struct sk_buff* tx_skbuff[TX_RING_SIZE];
197 ushort skb_cur;
198 ushort skb_dirty;
200 /* CPM dual port RAM relative addresses.
202 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
203 cbd_t *tx_bd_base;
204 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
205 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
206 struct net_device_stats stats;
207 uint tx_full;
208 spinlock_t lock;
210 uint phy_id;
211 uint phy_id_done;
212 uint phy_status;
213 uint phy_speed;
214 phy_info_t const *phy;
215 struct work_struct phy_task;
217 uint sequence_done;
218 uint mii_phy_task_queued;
220 uint phy_addr;
222 int index;
223 int opened;
224 int link;
225 int old_link;
226 int full_duplex;
229 static int fec_enet_open(struct net_device *dev);
230 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
231 static void fec_enet_mii(struct net_device *dev);
232 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
233 static void fec_enet_tx(struct net_device *dev);
234 static void fec_enet_rx(struct net_device *dev);
235 static int fec_enet_close(struct net_device *dev);
236 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
237 static void set_multicast_list(struct net_device *dev);
238 static void fec_restart(struct net_device *dev, int duplex);
239 static void fec_stop(struct net_device *dev);
240 static void fec_set_mac_address(struct net_device *dev);
243 /* MII processing. We keep this as simple as possible. Requests are
244 * placed on the list (if there is room). When the request is finished
245 * by the MII, an optional function may be called.
247 typedef struct mii_list {
248 uint mii_regval;
249 void (*mii_func)(uint val, struct net_device *dev);
250 struct mii_list *mii_next;
251 } mii_list_t;
253 #define NMII 20
254 static mii_list_t mii_cmds[NMII];
255 static mii_list_t *mii_free;
256 static mii_list_t *mii_head;
257 static mii_list_t *mii_tail;
259 static int mii_queue(struct net_device *dev, int request,
260 void (*func)(uint, struct net_device *));
262 /* Make MII read/write commands for the FEC.
264 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
265 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
266 (VAL & 0xffff))
267 #define mk_mii_end 0
269 /* Transmitter timeout.
271 #define TX_TIMEOUT (2*HZ)
273 /* Register definitions for the PHY.
276 #define MII_REG_CR 0 /* Control Register */
277 #define MII_REG_SR 1 /* Status Register */
278 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
279 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
280 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
281 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
282 #define MII_REG_ANER 6 /* A-N Expansion Register */
283 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
284 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
286 /* values for phy_status */
288 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
289 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
290 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
291 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
292 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
293 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
294 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
296 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
297 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
298 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
299 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
300 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
301 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
302 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
303 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
306 static int
307 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
309 struct fec_enet_private *fep;
310 volatile fec_t *fecp;
311 volatile cbd_t *bdp;
312 unsigned short status;
314 fep = netdev_priv(dev);
315 fecp = (volatile fec_t*)dev->base_addr;
317 if (!fep->link) {
318 /* Link is down or autonegotiation is in progress. */
319 return 1;
322 /* Fill in a Tx ring entry */
323 bdp = fep->cur_tx;
325 status = bdp->cbd_sc;
326 #ifndef final_version
327 if (status & BD_ENET_TX_READY) {
328 /* Ooops. All transmit buffers are full. Bail out.
329 * This should not happen, since dev->tbusy should be set.
331 printk("%s: tx queue full!.\n", dev->name);
332 return 1;
334 #endif
336 /* Clear all of the status flags.
338 status &= ~BD_ENET_TX_STATS;
340 /* Set buffer length and buffer pointer.
342 bdp->cbd_bufaddr = __pa(skb->data);
343 bdp->cbd_datlen = skb->len;
346 * On some FEC implementations data must be aligned on
347 * 4-byte boundaries. Use bounce buffers to copy data
348 * and get it aligned. Ugh.
350 if (bdp->cbd_bufaddr & 0x3) {
351 unsigned int index;
352 index = bdp - fep->tx_bd_base;
353 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
354 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
357 /* Save skb pointer.
359 fep->tx_skbuff[fep->skb_cur] = skb;
361 fep->stats.tx_bytes += skb->len;
362 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
364 /* Push the data cache so the CPM does not get stale memory
365 * data.
367 flush_dcache_range((unsigned long)skb->data,
368 (unsigned long)skb->data + skb->len);
370 spin_lock_irq(&fep->lock);
372 /* Send it on its way. Tell FEC it's ready, interrupt when done,
373 * it's the last BD of the frame, and to put the CRC on the end.
376 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
377 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
378 bdp->cbd_sc = status;
380 dev->trans_start = jiffies;
382 /* Trigger transmission start */
383 fecp->fec_x_des_active = 0;
385 /* If this was the last BD in the ring, start at the beginning again.
387 if (status & BD_ENET_TX_WRAP) {
388 bdp = fep->tx_bd_base;
389 } else {
390 bdp++;
393 if (bdp == fep->dirty_tx) {
394 fep->tx_full = 1;
395 netif_stop_queue(dev);
398 fep->cur_tx = (cbd_t *)bdp;
400 spin_unlock_irq(&fep->lock);
402 return 0;
405 static void
406 fec_timeout(struct net_device *dev)
408 struct fec_enet_private *fep = netdev_priv(dev);
410 printk("%s: transmit timed out.\n", dev->name);
411 fep->stats.tx_errors++;
412 #ifndef final_version
414 int i;
415 cbd_t *bdp;
417 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
418 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
419 (unsigned long)fep->dirty_tx,
420 (unsigned long)fep->cur_rx);
422 bdp = fep->tx_bd_base;
423 printk(" tx: %u buffers\n", TX_RING_SIZE);
424 for (i = 0 ; i < TX_RING_SIZE; i++) {
425 printk(" %08x: %04x %04x %08x\n",
426 (uint) bdp,
427 bdp->cbd_sc,
428 bdp->cbd_datlen,
429 (int) bdp->cbd_bufaddr);
430 bdp++;
433 bdp = fep->rx_bd_base;
434 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
435 for (i = 0 ; i < RX_RING_SIZE; i++) {
436 printk(" %08x: %04x %04x %08x\n",
437 (uint) bdp,
438 bdp->cbd_sc,
439 bdp->cbd_datlen,
440 (int) bdp->cbd_bufaddr);
441 bdp++;
444 #endif
445 fec_restart(dev, fep->full_duplex);
446 netif_wake_queue(dev);
449 /* The interrupt handler.
450 * This is called from the MPC core interrupt.
452 static irqreturn_t
453 fec_enet_interrupt(int irq, void * dev_id)
455 struct net_device *dev = dev_id;
456 volatile fec_t *fecp;
457 uint int_events;
458 int handled = 0;
460 fecp = (volatile fec_t*)dev->base_addr;
462 /* Get the interrupt events that caused us to be here.
464 while ((int_events = fecp->fec_ievent) != 0) {
465 fecp->fec_ievent = int_events;
467 /* Handle receive event in its own function.
469 if (int_events & FEC_ENET_RXF) {
470 handled = 1;
471 fec_enet_rx(dev);
474 /* Transmit OK, or non-fatal error. Update the buffer
475 descriptors. FEC handles all errors, we just discover
476 them as part of the transmit process.
478 if (int_events & FEC_ENET_TXF) {
479 handled = 1;
480 fec_enet_tx(dev);
483 if (int_events & FEC_ENET_MII) {
484 handled = 1;
485 fec_enet_mii(dev);
489 return IRQ_RETVAL(handled);
493 static void
494 fec_enet_tx(struct net_device *dev)
496 struct fec_enet_private *fep;
497 volatile cbd_t *bdp;
498 unsigned short status;
499 struct sk_buff *skb;
501 fep = netdev_priv(dev);
502 spin_lock(&fep->lock);
503 bdp = fep->dirty_tx;
505 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
506 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
508 skb = fep->tx_skbuff[fep->skb_dirty];
509 /* Check for errors. */
510 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
511 BD_ENET_TX_RL | BD_ENET_TX_UN |
512 BD_ENET_TX_CSL)) {
513 fep->stats.tx_errors++;
514 if (status & BD_ENET_TX_HB) /* No heartbeat */
515 fep->stats.tx_heartbeat_errors++;
516 if (status & BD_ENET_TX_LC) /* Late collision */
517 fep->stats.tx_window_errors++;
518 if (status & BD_ENET_TX_RL) /* Retrans limit */
519 fep->stats.tx_aborted_errors++;
520 if (status & BD_ENET_TX_UN) /* Underrun */
521 fep->stats.tx_fifo_errors++;
522 if (status & BD_ENET_TX_CSL) /* Carrier lost */
523 fep->stats.tx_carrier_errors++;
524 } else {
525 fep->stats.tx_packets++;
528 #ifndef final_version
529 if (status & BD_ENET_TX_READY)
530 printk("HEY! Enet xmit interrupt and TX_READY.\n");
531 #endif
532 /* Deferred means some collisions occurred during transmit,
533 * but we eventually sent the packet OK.
535 if (status & BD_ENET_TX_DEF)
536 fep->stats.collisions++;
538 /* Free the sk buffer associated with this last transmit.
540 dev_kfree_skb_any(skb);
541 fep->tx_skbuff[fep->skb_dirty] = NULL;
542 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
544 /* Update pointer to next buffer descriptor to be transmitted.
546 if (status & BD_ENET_TX_WRAP)
547 bdp = fep->tx_bd_base;
548 else
549 bdp++;
551 /* Since we have freed up a buffer, the ring is no longer
552 * full.
554 if (fep->tx_full) {
555 fep->tx_full = 0;
556 if (netif_queue_stopped(dev))
557 netif_wake_queue(dev);
560 fep->dirty_tx = (cbd_t *)bdp;
561 spin_unlock(&fep->lock);
565 /* During a receive, the cur_rx points to the current incoming buffer.
566 * When we update through the ring, if the next incoming buffer has
567 * not been given to the system, we just set the empty indicator,
568 * effectively tossing the packet.
570 static void
571 fec_enet_rx(struct net_device *dev)
573 struct fec_enet_private *fep;
574 volatile fec_t *fecp;
575 volatile cbd_t *bdp;
576 unsigned short status;
577 struct sk_buff *skb;
578 ushort pkt_len;
579 __u8 *data;
581 #ifdef CONFIG_M532x
582 flush_cache_all();
583 #endif
585 fep = netdev_priv(dev);
586 fecp = (volatile fec_t*)dev->base_addr;
588 /* First, grab all of the stats for the incoming packet.
589 * These get messed up if we get called due to a busy condition.
591 bdp = fep->cur_rx;
593 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
595 #ifndef final_version
596 /* Since we have allocated space to hold a complete frame,
597 * the last indicator should be set.
599 if ((status & BD_ENET_RX_LAST) == 0)
600 printk("FEC ENET: rcv is not +last\n");
601 #endif
603 if (!fep->opened)
604 goto rx_processing_done;
606 /* Check for errors. */
607 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
608 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
609 fep->stats.rx_errors++;
610 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
611 /* Frame too long or too short. */
612 fep->stats.rx_length_errors++;
614 if (status & BD_ENET_RX_NO) /* Frame alignment */
615 fep->stats.rx_frame_errors++;
616 if (status & BD_ENET_RX_CR) /* CRC Error */
617 fep->stats.rx_crc_errors++;
618 if (status & BD_ENET_RX_OV) /* FIFO overrun */
619 fep->stats.rx_fifo_errors++;
622 /* Report late collisions as a frame error.
623 * On this error, the BD is closed, but we don't know what we
624 * have in the buffer. So, just drop this frame on the floor.
626 if (status & BD_ENET_RX_CL) {
627 fep->stats.rx_errors++;
628 fep->stats.rx_frame_errors++;
629 goto rx_processing_done;
632 /* Process the incoming frame.
634 fep->stats.rx_packets++;
635 pkt_len = bdp->cbd_datlen;
636 fep->stats.rx_bytes += pkt_len;
637 data = (__u8*)__va(bdp->cbd_bufaddr);
639 /* This does 16 byte alignment, exactly what we need.
640 * The packet length includes FCS, but we don't want to
641 * include that when passing upstream as it messes up
642 * bridging applications.
644 skb = dev_alloc_skb(pkt_len-4);
646 if (skb == NULL) {
647 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
648 fep->stats.rx_dropped++;
649 } else {
650 skb_put(skb,pkt_len-4); /* Make room */
651 eth_copy_and_sum(skb, data, pkt_len-4, 0);
652 skb->protocol=eth_type_trans(skb,dev);
653 netif_rx(skb);
655 rx_processing_done:
657 /* Clear the status flags for this buffer.
659 status &= ~BD_ENET_RX_STATS;
661 /* Mark the buffer empty.
663 status |= BD_ENET_RX_EMPTY;
664 bdp->cbd_sc = status;
666 /* Update BD pointer to next entry.
668 if (status & BD_ENET_RX_WRAP)
669 bdp = fep->rx_bd_base;
670 else
671 bdp++;
673 #if 1
674 /* Doing this here will keep the FEC running while we process
675 * incoming frames. On a heavily loaded network, we should be
676 * able to keep up at the expense of system resources.
678 fecp->fec_r_des_active = 0;
679 #endif
680 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
681 fep->cur_rx = (cbd_t *)bdp;
683 #if 0
684 /* Doing this here will allow us to process all frames in the
685 * ring before the FEC is allowed to put more there. On a heavily
686 * loaded network, some frames may be lost. Unfortunately, this
687 * increases the interrupt overhead since we can potentially work
688 * our way back to the interrupt return only to come right back
689 * here.
691 fecp->fec_r_des_active = 0;
692 #endif
696 /* called from interrupt context */
697 static void
698 fec_enet_mii(struct net_device *dev)
700 struct fec_enet_private *fep;
701 volatile fec_t *ep;
702 mii_list_t *mip;
703 uint mii_reg;
705 fep = netdev_priv(dev);
706 ep = fep->hwp;
707 mii_reg = ep->fec_mii_data;
709 spin_lock(&fep->lock);
711 if ((mip = mii_head) == NULL) {
712 printk("MII and no head!\n");
713 goto unlock;
716 if (mip->mii_func != NULL)
717 (*(mip->mii_func))(mii_reg, dev);
719 mii_head = mip->mii_next;
720 mip->mii_next = mii_free;
721 mii_free = mip;
723 if ((mip = mii_head) != NULL)
724 ep->fec_mii_data = mip->mii_regval;
726 unlock:
727 spin_unlock(&fep->lock);
730 static int
731 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
733 struct fec_enet_private *fep;
734 unsigned long flags;
735 mii_list_t *mip;
736 int retval;
738 /* Add PHY address to register command.
740 fep = netdev_priv(dev);
741 regval |= fep->phy_addr << 23;
743 retval = 0;
745 spin_lock_irqsave(&fep->lock,flags);
747 if ((mip = mii_free) != NULL) {
748 mii_free = mip->mii_next;
749 mip->mii_regval = regval;
750 mip->mii_func = func;
751 mip->mii_next = NULL;
752 if (mii_head) {
753 mii_tail->mii_next = mip;
754 mii_tail = mip;
756 else {
757 mii_head = mii_tail = mip;
758 fep->hwp->fec_mii_data = regval;
761 else {
762 retval = 1;
765 spin_unlock_irqrestore(&fep->lock,flags);
767 return(retval);
770 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
772 int k;
774 if(!c)
775 return;
777 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
778 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
782 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
784 struct fec_enet_private *fep = netdev_priv(dev);
785 volatile uint *s = &(fep->phy_status);
786 uint status;
788 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
790 if (mii_reg & 0x0004)
791 status |= PHY_STAT_LINK;
792 if (mii_reg & 0x0010)
793 status |= PHY_STAT_FAULT;
794 if (mii_reg & 0x0020)
795 status |= PHY_STAT_ANC;
797 *s = status;
800 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
802 struct fec_enet_private *fep = netdev_priv(dev);
803 volatile uint *s = &(fep->phy_status);
804 uint status;
806 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
808 if (mii_reg & 0x1000)
809 status |= PHY_CONF_ANE;
810 if (mii_reg & 0x4000)
811 status |= PHY_CONF_LOOP;
812 *s = status;
815 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
817 struct fec_enet_private *fep = netdev_priv(dev);
818 volatile uint *s = &(fep->phy_status);
819 uint status;
821 status = *s & ~(PHY_CONF_SPMASK);
823 if (mii_reg & 0x0020)
824 status |= PHY_CONF_10HDX;
825 if (mii_reg & 0x0040)
826 status |= PHY_CONF_10FDX;
827 if (mii_reg & 0x0080)
828 status |= PHY_CONF_100HDX;
829 if (mii_reg & 0x00100)
830 status |= PHY_CONF_100FDX;
831 *s = status;
834 /* ------------------------------------------------------------------------- */
835 /* The Level one LXT970 is used by many boards */
837 #define MII_LXT970_MIRROR 16 /* Mirror register */
838 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
839 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
840 #define MII_LXT970_CONFIG 19 /* Configuration Register */
841 #define MII_LXT970_CSR 20 /* Chip Status Register */
843 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
845 struct fec_enet_private *fep = netdev_priv(dev);
846 volatile uint *s = &(fep->phy_status);
847 uint status;
849 status = *s & ~(PHY_STAT_SPMASK);
850 if (mii_reg & 0x0800) {
851 if (mii_reg & 0x1000)
852 status |= PHY_STAT_100FDX;
853 else
854 status |= PHY_STAT_100HDX;
855 } else {
856 if (mii_reg & 0x1000)
857 status |= PHY_STAT_10FDX;
858 else
859 status |= PHY_STAT_10HDX;
861 *s = status;
864 static phy_cmd_t const phy_cmd_lxt970_config[] = {
865 { mk_mii_read(MII_REG_CR), mii_parse_cr },
866 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
867 { mk_mii_end, }
869 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
870 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
871 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
872 { mk_mii_end, }
874 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
875 /* read SR and ISR to acknowledge */
876 { mk_mii_read(MII_REG_SR), mii_parse_sr },
877 { mk_mii_read(MII_LXT970_ISR), NULL },
879 /* find out the current status */
880 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
881 { mk_mii_end, }
883 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
884 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
885 { mk_mii_end, }
887 static phy_info_t const phy_info_lxt970 = {
888 .id = 0x07810000,
889 .name = "LXT970",
890 .config = phy_cmd_lxt970_config,
891 .startup = phy_cmd_lxt970_startup,
892 .ack_int = phy_cmd_lxt970_ack_int,
893 .shutdown = phy_cmd_lxt970_shutdown
896 /* ------------------------------------------------------------------------- */
897 /* The Level one LXT971 is used on some of my custom boards */
899 /* register definitions for the 971 */
901 #define MII_LXT971_PCR 16 /* Port Control Register */
902 #define MII_LXT971_SR2 17 /* Status Register 2 */
903 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
904 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
905 #define MII_LXT971_LCR 20 /* LED Control Register */
906 #define MII_LXT971_TCR 30 /* Transmit Control Register */
909 * I had some nice ideas of running the MDIO faster...
910 * The 971 should support 8MHz and I tried it, but things acted really
911 * weird, so 2.5 MHz ought to be enough for anyone...
914 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
916 struct fec_enet_private *fep = netdev_priv(dev);
917 volatile uint *s = &(fep->phy_status);
918 uint status;
920 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
922 if (mii_reg & 0x0400) {
923 fep->link = 1;
924 status |= PHY_STAT_LINK;
925 } else {
926 fep->link = 0;
928 if (mii_reg & 0x0080)
929 status |= PHY_STAT_ANC;
930 if (mii_reg & 0x4000) {
931 if (mii_reg & 0x0200)
932 status |= PHY_STAT_100FDX;
933 else
934 status |= PHY_STAT_100HDX;
935 } else {
936 if (mii_reg & 0x0200)
937 status |= PHY_STAT_10FDX;
938 else
939 status |= PHY_STAT_10HDX;
941 if (mii_reg & 0x0008)
942 status |= PHY_STAT_FAULT;
944 *s = status;
947 static phy_cmd_t const phy_cmd_lxt971_config[] = {
948 /* limit to 10MBit because my prototype board
949 * doesn't work with 100. */
950 { mk_mii_read(MII_REG_CR), mii_parse_cr },
951 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
952 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
953 { mk_mii_end, }
955 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
956 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
957 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
958 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
959 /* Somehow does the 971 tell me that the link is down
960 * the first read after power-up.
961 * read here to get a valid value in ack_int */
962 { mk_mii_read(MII_REG_SR), mii_parse_sr },
963 { mk_mii_end, }
965 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
966 /* acknowledge the int before reading status ! */
967 { mk_mii_read(MII_LXT971_ISR), NULL },
968 /* find out the current status */
969 { mk_mii_read(MII_REG_SR), mii_parse_sr },
970 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
971 { mk_mii_end, }
973 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
974 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
975 { mk_mii_end, }
977 static phy_info_t const phy_info_lxt971 = {
978 .id = 0x0001378e,
979 .name = "LXT971",
980 .config = phy_cmd_lxt971_config,
981 .startup = phy_cmd_lxt971_startup,
982 .ack_int = phy_cmd_lxt971_ack_int,
983 .shutdown = phy_cmd_lxt971_shutdown
986 /* ------------------------------------------------------------------------- */
987 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
989 /* register definitions */
991 #define MII_QS6612_MCR 17 /* Mode Control Register */
992 #define MII_QS6612_FTR 27 /* Factory Test Register */
993 #define MII_QS6612_MCO 28 /* Misc. Control Register */
994 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
995 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
996 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
998 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1000 struct fec_enet_private *fep = netdev_priv(dev);
1001 volatile uint *s = &(fep->phy_status);
1002 uint status;
1004 status = *s & ~(PHY_STAT_SPMASK);
1006 switch((mii_reg >> 2) & 7) {
1007 case 1: status |= PHY_STAT_10HDX; break;
1008 case 2: status |= PHY_STAT_100HDX; break;
1009 case 5: status |= PHY_STAT_10FDX; break;
1010 case 6: status |= PHY_STAT_100FDX; break;
1013 *s = status;
1016 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1017 /* The PHY powers up isolated on the RPX,
1018 * so send a command to allow operation.
1020 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1022 /* parse cr and anar to get some info */
1023 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1024 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1025 { mk_mii_end, }
1027 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1028 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1029 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1030 { mk_mii_end, }
1032 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1033 /* we need to read ISR, SR and ANER to acknowledge */
1034 { mk_mii_read(MII_QS6612_ISR), NULL },
1035 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1036 { mk_mii_read(MII_REG_ANER), NULL },
1038 /* read pcr to get info */
1039 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1040 { mk_mii_end, }
1042 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1043 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1044 { mk_mii_end, }
1046 static phy_info_t const phy_info_qs6612 = {
1047 .id = 0x00181440,
1048 .name = "QS6612",
1049 .config = phy_cmd_qs6612_config,
1050 .startup = phy_cmd_qs6612_startup,
1051 .ack_int = phy_cmd_qs6612_ack_int,
1052 .shutdown = phy_cmd_qs6612_shutdown
1055 /* ------------------------------------------------------------------------- */
1056 /* AMD AM79C874 phy */
1058 /* register definitions for the 874 */
1060 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1061 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1062 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1063 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1064 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1065 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1066 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1068 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1070 struct fec_enet_private *fep = netdev_priv(dev);
1071 volatile uint *s = &(fep->phy_status);
1072 uint status;
1074 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1076 if (mii_reg & 0x0080)
1077 status |= PHY_STAT_ANC;
1078 if (mii_reg & 0x0400)
1079 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1080 else
1081 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1083 *s = status;
1086 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1087 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1088 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1089 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1090 { mk_mii_end, }
1092 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1093 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1094 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1095 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1096 { mk_mii_end, }
1098 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1099 /* find out the current status */
1100 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1101 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1102 /* we only need to read ISR to acknowledge */
1103 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1104 { mk_mii_end, }
1106 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1107 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1108 { mk_mii_end, }
1110 static phy_info_t const phy_info_am79c874 = {
1111 .id = 0x00022561,
1112 .name = "AM79C874",
1113 .config = phy_cmd_am79c874_config,
1114 .startup = phy_cmd_am79c874_startup,
1115 .ack_int = phy_cmd_am79c874_ack_int,
1116 .shutdown = phy_cmd_am79c874_shutdown
1120 /* ------------------------------------------------------------------------- */
1121 /* Kendin KS8721BL phy */
1123 /* register definitions for the 8721 */
1125 #define MII_KS8721BL_RXERCR 21
1126 #define MII_KS8721BL_ICSR 22
1127 #define MII_KS8721BL_PHYCR 31
1129 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1130 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1131 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1132 { mk_mii_end, }
1134 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1135 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1136 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1137 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1138 { mk_mii_end, }
1140 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1141 /* find out the current status */
1142 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1143 /* we only need to read ISR to acknowledge */
1144 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1145 { mk_mii_end, }
1147 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1148 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1149 { mk_mii_end, }
1151 static phy_info_t const phy_info_ks8721bl = {
1152 .id = 0x00022161,
1153 .name = "KS8721BL",
1154 .config = phy_cmd_ks8721bl_config,
1155 .startup = phy_cmd_ks8721bl_startup,
1156 .ack_int = phy_cmd_ks8721bl_ack_int,
1157 .shutdown = phy_cmd_ks8721bl_shutdown
1160 /* ------------------------------------------------------------------------- */
1161 /* register definitions for the DP83848 */
1163 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1165 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1167 struct fec_enet_private *fep = dev->priv;
1168 volatile uint *s = &(fep->phy_status);
1170 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1172 /* Link up */
1173 if (mii_reg & 0x0001) {
1174 fep->link = 1;
1175 *s |= PHY_STAT_LINK;
1176 } else
1177 fep->link = 0;
1178 /* Status of link */
1179 if (mii_reg & 0x0010) /* Autonegotioation complete */
1180 *s |= PHY_STAT_ANC;
1181 if (mii_reg & 0x0002) { /* 10MBps? */
1182 if (mii_reg & 0x0004) /* Full Duplex? */
1183 *s |= PHY_STAT_10FDX;
1184 else
1185 *s |= PHY_STAT_10HDX;
1186 } else { /* 100 Mbps? */
1187 if (mii_reg & 0x0004) /* Full Duplex? */
1188 *s |= PHY_STAT_100FDX;
1189 else
1190 *s |= PHY_STAT_100HDX;
1192 if (mii_reg & 0x0008)
1193 *s |= PHY_STAT_FAULT;
1196 static phy_info_t phy_info_dp83848= {
1197 0x020005c9,
1198 "DP83848",
1200 (const phy_cmd_t []) { /* config */
1201 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1202 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1203 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1204 { mk_mii_end, }
1206 (const phy_cmd_t []) { /* startup - enable interrupts */
1207 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1208 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1209 { mk_mii_end, }
1211 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1212 { mk_mii_end, }
1214 (const phy_cmd_t []) { /* shutdown */
1215 { mk_mii_end, }
1219 /* ------------------------------------------------------------------------- */
1221 static phy_info_t const * const phy_info[] = {
1222 &phy_info_lxt970,
1223 &phy_info_lxt971,
1224 &phy_info_qs6612,
1225 &phy_info_am79c874,
1226 &phy_info_ks8721bl,
1227 &phy_info_dp83848,
1228 NULL
1231 /* ------------------------------------------------------------------------- */
1232 #if !defined(CONFIG_M532x)
1233 #ifdef CONFIG_RPXCLASSIC
1234 static void
1235 mii_link_interrupt(void *dev_id);
1236 #else
1237 static irqreturn_t
1238 mii_link_interrupt(int irq, void * dev_id);
1239 #endif
1240 #endif
1242 #if defined(CONFIG_M5272)
1245 * Code specific to Coldfire 5272 setup.
1247 static void __inline__ fec_request_intrs(struct net_device *dev)
1249 volatile unsigned long *icrp;
1250 static const struct idesc {
1251 char *name;
1252 unsigned short irq;
1253 irq_handler_t handler;
1254 } *idp, id[] = {
1255 { "fec(RX)", 86, fec_enet_interrupt },
1256 { "fec(TX)", 87, fec_enet_interrupt },
1257 { "fec(OTHER)", 88, fec_enet_interrupt },
1258 { "fec(MII)", 66, mii_link_interrupt },
1259 { NULL },
1262 /* Setup interrupt handlers. */
1263 for (idp = id; idp->name; idp++) {
1264 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1265 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1268 /* Unmask interrupt at ColdFire 5272 SIM */
1269 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1270 *icrp = 0x00000ddd;
1271 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1272 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1275 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1277 volatile fec_t *fecp;
1279 fecp = fep->hwp;
1280 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1281 fecp->fec_x_cntrl = 0x00;
1284 * Set MII speed to 2.5 MHz
1285 * See 5272 manual section 11.5.8: MSCR
1287 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1288 fecp->fec_mii_speed = fep->phy_speed;
1290 fec_restart(dev, 0);
1293 static void __inline__ fec_get_mac(struct net_device *dev)
1295 struct fec_enet_private *fep = netdev_priv(dev);
1296 volatile fec_t *fecp;
1297 unsigned char *iap, tmpaddr[ETH_ALEN];
1299 fecp = fep->hwp;
1301 if (FEC_FLASHMAC) {
1303 * Get MAC address from FLASH.
1304 * If it is all 1's or 0's, use the default.
1306 iap = (unsigned char *)FEC_FLASHMAC;
1307 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1308 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1309 iap = fec_mac_default;
1310 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1311 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1312 iap = fec_mac_default;
1313 } else {
1314 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1315 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1316 iap = &tmpaddr[0];
1319 memcpy(dev->dev_addr, iap, ETH_ALEN);
1321 /* Adjust MAC if using default MAC address */
1322 if (iap == fec_mac_default)
1323 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1326 static void __inline__ fec_enable_phy_intr(void)
1330 static void __inline__ fec_disable_phy_intr(void)
1332 volatile unsigned long *icrp;
1333 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1334 *icrp = (*icrp & 0x70777777) | 0x08000000;
1337 static void __inline__ fec_phy_ack_intr(void)
1339 volatile unsigned long *icrp;
1340 /* Acknowledge the interrupt */
1341 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1342 *icrp = (*icrp & 0x77777777) | 0x08000000;
1345 static void __inline__ fec_localhw_setup(void)
1350 * Do not need to make region uncached on 5272.
1352 static void __inline__ fec_uncache(unsigned long addr)
1356 /* ------------------------------------------------------------------------- */
1358 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1361 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1362 * the 5270/5271/5274/5275 and 5280/5282 setups.
1364 static void __inline__ fec_request_intrs(struct net_device *dev)
1366 struct fec_enet_private *fep;
1367 int b;
1368 static const struct idesc {
1369 char *name;
1370 unsigned short irq;
1371 } *idp, id[] = {
1372 { "fec(TXF)", 23 },
1373 { "fec(TXB)", 24 },
1374 { "fec(TXFIFO)", 25 },
1375 { "fec(TXCR)", 26 },
1376 { "fec(RXF)", 27 },
1377 { "fec(RXB)", 28 },
1378 { "fec(MII)", 29 },
1379 { "fec(LC)", 30 },
1380 { "fec(HBERR)", 31 },
1381 { "fec(GRA)", 32 },
1382 { "fec(EBERR)", 33 },
1383 { "fec(BABT)", 34 },
1384 { "fec(BABR)", 35 },
1385 { NULL },
1388 fep = netdev_priv(dev);
1389 b = (fep->index) ? 128 : 64;
1391 /* Setup interrupt handlers. */
1392 for (idp = id; idp->name; idp++) {
1393 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1394 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1397 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1399 volatile unsigned char *icrp;
1400 volatile unsigned long *imrp;
1401 int i, ilip;
1403 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1404 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1405 MCFINTC_ICR0);
1406 for (i = 23, ilip = 0x28; (i < 36); i++)
1407 icrp[i] = ilip--;
1409 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1410 MCFINTC_IMRH);
1411 *imrp &= ~0x0000000f;
1412 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1413 MCFINTC_IMRL);
1414 *imrp &= ~0xff800001;
1417 #if defined(CONFIG_M528x)
1418 /* Set up gpio outputs for MII lines */
1420 volatile u16 *gpio_paspar;
1421 volatile u8 *gpio_pehlpar;
1423 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1424 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1425 *gpio_paspar |= 0x0f00;
1426 *gpio_pehlpar = 0xc0;
1428 #endif
1431 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1433 volatile fec_t *fecp;
1435 fecp = fep->hwp;
1436 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1437 fecp->fec_x_cntrl = 0x00;
1440 * Set MII speed to 2.5 MHz
1441 * See 5282 manual section 17.5.4.7: MSCR
1443 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1444 fecp->fec_mii_speed = fep->phy_speed;
1446 fec_restart(dev, 0);
1449 static void __inline__ fec_get_mac(struct net_device *dev)
1451 struct fec_enet_private *fep = netdev_priv(dev);
1452 volatile fec_t *fecp;
1453 unsigned char *iap, tmpaddr[ETH_ALEN];
1455 fecp = fep->hwp;
1457 if (FEC_FLASHMAC) {
1459 * Get MAC address from FLASH.
1460 * If it is all 1's or 0's, use the default.
1462 iap = FEC_FLASHMAC;
1463 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1464 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1465 iap = fec_mac_default;
1466 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1467 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1468 iap = fec_mac_default;
1469 } else {
1470 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1471 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1472 iap = &tmpaddr[0];
1475 memcpy(dev->dev_addr, iap, ETH_ALEN);
1477 /* Adjust MAC if using default MAC address */
1478 if (iap == fec_mac_default)
1479 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1482 static void __inline__ fec_enable_phy_intr(void)
1486 static void __inline__ fec_disable_phy_intr(void)
1490 static void __inline__ fec_phy_ack_intr(void)
1494 static void __inline__ fec_localhw_setup(void)
1499 * Do not need to make region uncached on 5272.
1501 static void __inline__ fec_uncache(unsigned long addr)
1505 /* ------------------------------------------------------------------------- */
1507 #elif defined(CONFIG_M520x)
1510 * Code specific to Coldfire 520x
1512 static void __inline__ fec_request_intrs(struct net_device *dev)
1514 struct fec_enet_private *fep;
1515 int b;
1516 static const struct idesc {
1517 char *name;
1518 unsigned short irq;
1519 } *idp, id[] = {
1520 { "fec(TXF)", 23 },
1521 { "fec(TXB)", 24 },
1522 { "fec(TXFIFO)", 25 },
1523 { "fec(TXCR)", 26 },
1524 { "fec(RXF)", 27 },
1525 { "fec(RXB)", 28 },
1526 { "fec(MII)", 29 },
1527 { "fec(LC)", 30 },
1528 { "fec(HBERR)", 31 },
1529 { "fec(GRA)", 32 },
1530 { "fec(EBERR)", 33 },
1531 { "fec(BABT)", 34 },
1532 { "fec(BABR)", 35 },
1533 { NULL },
1536 fep = netdev_priv(dev);
1537 b = 64 + 13;
1539 /* Setup interrupt handlers. */
1540 for (idp = id; idp->name; idp++) {
1541 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1542 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1545 /* Unmask interrupts at ColdFire interrupt controller */
1547 volatile unsigned char *icrp;
1548 volatile unsigned long *imrp;
1550 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1551 MCFINTC_ICR0);
1552 for (b = 36; (b < 49); b++)
1553 icrp[b] = 0x04;
1554 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1555 MCFINTC_IMRH);
1556 *imrp &= ~0x0001FFF0;
1558 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1559 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1562 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1564 volatile fec_t *fecp;
1566 fecp = fep->hwp;
1567 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1568 fecp->fec_x_cntrl = 0x00;
1571 * Set MII speed to 2.5 MHz
1572 * See 5282 manual section 17.5.4.7: MSCR
1574 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1575 fecp->fec_mii_speed = fep->phy_speed;
1577 fec_restart(dev, 0);
1580 static void __inline__ fec_get_mac(struct net_device *dev)
1582 struct fec_enet_private *fep = netdev_priv(dev);
1583 volatile fec_t *fecp;
1584 unsigned char *iap, tmpaddr[ETH_ALEN];
1586 fecp = fep->hwp;
1588 if (FEC_FLASHMAC) {
1590 * Get MAC address from FLASH.
1591 * If it is all 1's or 0's, use the default.
1593 iap = FEC_FLASHMAC;
1594 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1595 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1596 iap = fec_mac_default;
1597 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1598 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1599 iap = fec_mac_default;
1600 } else {
1601 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1602 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1603 iap = &tmpaddr[0];
1606 memcpy(dev->dev_addr, iap, ETH_ALEN);
1608 /* Adjust MAC if using default MAC address */
1609 if (iap == fec_mac_default)
1610 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1613 static void __inline__ fec_enable_phy_intr(void)
1617 static void __inline__ fec_disable_phy_intr(void)
1621 static void __inline__ fec_phy_ack_intr(void)
1625 static void __inline__ fec_localhw_setup(void)
1629 static void __inline__ fec_uncache(unsigned long addr)
1633 /* ------------------------------------------------------------------------- */
1635 #elif defined(CONFIG_M532x)
1637 * Code specific for M532x
1639 static void __inline__ fec_request_intrs(struct net_device *dev)
1641 struct fec_enet_private *fep;
1642 int b;
1643 static const struct idesc {
1644 char *name;
1645 unsigned short irq;
1646 } *idp, id[] = {
1647 { "fec(TXF)", 36 },
1648 { "fec(TXB)", 37 },
1649 { "fec(TXFIFO)", 38 },
1650 { "fec(TXCR)", 39 },
1651 { "fec(RXF)", 40 },
1652 { "fec(RXB)", 41 },
1653 { "fec(MII)", 42 },
1654 { "fec(LC)", 43 },
1655 { "fec(HBERR)", 44 },
1656 { "fec(GRA)", 45 },
1657 { "fec(EBERR)", 46 },
1658 { "fec(BABT)", 47 },
1659 { "fec(BABR)", 48 },
1660 { NULL },
1663 fep = netdev_priv(dev);
1664 b = (fep->index) ? 128 : 64;
1666 /* Setup interrupt handlers. */
1667 for (idp = id; idp->name; idp++) {
1668 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1669 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1670 idp->name, b+idp->irq);
1673 /* Unmask interrupts */
1674 MCF_INTC0_ICR36 = 0x2;
1675 MCF_INTC0_ICR37 = 0x2;
1676 MCF_INTC0_ICR38 = 0x2;
1677 MCF_INTC0_ICR39 = 0x2;
1678 MCF_INTC0_ICR40 = 0x2;
1679 MCF_INTC0_ICR41 = 0x2;
1680 MCF_INTC0_ICR42 = 0x2;
1681 MCF_INTC0_ICR43 = 0x2;
1682 MCF_INTC0_ICR44 = 0x2;
1683 MCF_INTC0_ICR45 = 0x2;
1684 MCF_INTC0_ICR46 = 0x2;
1685 MCF_INTC0_ICR47 = 0x2;
1686 MCF_INTC0_ICR48 = 0x2;
1688 MCF_INTC0_IMRH &= ~(
1689 MCF_INTC_IMRH_INT_MASK36 |
1690 MCF_INTC_IMRH_INT_MASK37 |
1691 MCF_INTC_IMRH_INT_MASK38 |
1692 MCF_INTC_IMRH_INT_MASK39 |
1693 MCF_INTC_IMRH_INT_MASK40 |
1694 MCF_INTC_IMRH_INT_MASK41 |
1695 MCF_INTC_IMRH_INT_MASK42 |
1696 MCF_INTC_IMRH_INT_MASK43 |
1697 MCF_INTC_IMRH_INT_MASK44 |
1698 MCF_INTC_IMRH_INT_MASK45 |
1699 MCF_INTC_IMRH_INT_MASK46 |
1700 MCF_INTC_IMRH_INT_MASK47 |
1701 MCF_INTC_IMRH_INT_MASK48 );
1703 /* Set up gpio outputs for MII lines */
1704 MCF_GPIO_PAR_FECI2C |= (0 |
1705 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1706 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1707 MCF_GPIO_PAR_FEC = (0 |
1708 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1709 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1712 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1714 volatile fec_t *fecp;
1716 fecp = fep->hwp;
1717 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1718 fecp->fec_x_cntrl = 0x00;
1721 * Set MII speed to 2.5 MHz
1723 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1724 fecp->fec_mii_speed = fep->phy_speed;
1726 fec_restart(dev, 0);
1729 static void __inline__ fec_get_mac(struct net_device *dev)
1731 struct fec_enet_private *fep = netdev_priv(dev);
1732 volatile fec_t *fecp;
1733 unsigned char *iap, tmpaddr[ETH_ALEN];
1735 fecp = fep->hwp;
1737 if (FEC_FLASHMAC) {
1739 * Get MAC address from FLASH.
1740 * If it is all 1's or 0's, use the default.
1742 iap = FEC_FLASHMAC;
1743 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1744 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1745 iap = fec_mac_default;
1746 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1747 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1748 iap = fec_mac_default;
1749 } else {
1750 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1751 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1752 iap = &tmpaddr[0];
1755 memcpy(dev->dev_addr, iap, ETH_ALEN);
1757 /* Adjust MAC if using default MAC address */
1758 if (iap == fec_mac_default)
1759 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1762 static void __inline__ fec_enable_phy_intr(void)
1766 static void __inline__ fec_disable_phy_intr(void)
1770 static void __inline__ fec_phy_ack_intr(void)
1774 static void __inline__ fec_localhw_setup(void)
1779 * Do not need to make region uncached on 532x.
1781 static void __inline__ fec_uncache(unsigned long addr)
1785 /* ------------------------------------------------------------------------- */
1788 #else
1791 * Code specific to the MPC860T setup.
1793 static void __inline__ fec_request_intrs(struct net_device *dev)
1795 volatile immap_t *immap;
1797 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1799 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1800 panic("Could not allocate FEC IRQ!");
1802 #ifdef CONFIG_RPXCLASSIC
1803 /* Make Port C, bit 15 an input that causes interrupts.
1805 immap->im_ioport.iop_pcpar &= ~0x0001;
1806 immap->im_ioport.iop_pcdir &= ~0x0001;
1807 immap->im_ioport.iop_pcso &= ~0x0001;
1808 immap->im_ioport.iop_pcint |= 0x0001;
1809 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1811 /* Make LEDS reflect Link status.
1813 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1814 #endif
1815 #ifdef CONFIG_FADS
1816 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1817 panic("Could not allocate MII IRQ!");
1818 #endif
1821 static void __inline__ fec_get_mac(struct net_device *dev)
1823 bd_t *bd;
1825 bd = (bd_t *)__res;
1826 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1828 #ifdef CONFIG_RPXCLASSIC
1829 /* The Embedded Planet boards have only one MAC address in
1830 * the EEPROM, but can have two Ethernet ports. For the
1831 * FEC port, we create another address by setting one of
1832 * the address bits above something that would have (up to
1833 * now) been allocated.
1835 dev->dev_adrd[3] |= 0x80;
1836 #endif
1839 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1841 extern uint _get_IMMR(void);
1842 volatile immap_t *immap;
1843 volatile fec_t *fecp;
1845 fecp = fep->hwp;
1846 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1848 /* Configure all of port D for MII.
1850 immap->im_ioport.iop_pdpar = 0x1fff;
1852 /* Bits moved from Rev. D onward.
1854 if ((_get_IMMR() & 0xffff) < 0x0501)
1855 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1856 else
1857 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1859 /* Set MII speed to 2.5 MHz
1861 fecp->fec_mii_speed = fep->phy_speed =
1862 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1865 static void __inline__ fec_enable_phy_intr(void)
1867 volatile fec_t *fecp;
1869 fecp = fep->hwp;
1871 /* Enable MII command finished interrupt
1873 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1876 static void __inline__ fec_disable_phy_intr(void)
1880 static void __inline__ fec_phy_ack_intr(void)
1884 static void __inline__ fec_localhw_setup(void)
1886 volatile fec_t *fecp;
1888 fecp = fep->hwp;
1889 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1890 /* Enable big endian and don't care about SDMA FC.
1892 fecp->fec_fun_code = 0x78000000;
1895 static void __inline__ fec_uncache(unsigned long addr)
1897 pte_t *pte;
1898 pte = va_to_pte(mem_addr);
1899 pte_val(*pte) |= _PAGE_NO_CACHE;
1900 flush_tlb_page(init_mm.mmap, mem_addr);
1903 #endif
1905 /* ------------------------------------------------------------------------- */
1907 static void mii_display_status(struct net_device *dev)
1909 struct fec_enet_private *fep = netdev_priv(dev);
1910 volatile uint *s = &(fep->phy_status);
1912 if (!fep->link && !fep->old_link) {
1913 /* Link is still down - don't print anything */
1914 return;
1917 printk("%s: status: ", dev->name);
1919 if (!fep->link) {
1920 printk("link down");
1921 } else {
1922 printk("link up");
1924 switch(*s & PHY_STAT_SPMASK) {
1925 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1926 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1927 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1928 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1929 default:
1930 printk(", Unknown speed/duplex");
1933 if (*s & PHY_STAT_ANC)
1934 printk(", auto-negotiation complete");
1937 if (*s & PHY_STAT_FAULT)
1938 printk(", remote fault");
1940 printk(".\n");
1943 static void mii_display_config(struct net_device *dev)
1945 struct fec_enet_private *fep = netdev_priv(dev);
1946 uint status = fep->phy_status;
1949 ** When we get here, phy_task is already removed from
1950 ** the workqueue. It is thus safe to allow to reuse it.
1952 fep->mii_phy_task_queued = 0;
1953 printk("%s: config: auto-negotiation ", dev->name);
1955 if (status & PHY_CONF_ANE)
1956 printk("on");
1957 else
1958 printk("off");
1960 if (status & PHY_CONF_100FDX)
1961 printk(", 100FDX");
1962 if (status & PHY_CONF_100HDX)
1963 printk(", 100HDX");
1964 if (status & PHY_CONF_10FDX)
1965 printk(", 10FDX");
1966 if (status & PHY_CONF_10HDX)
1967 printk(", 10HDX");
1968 if (!(status & PHY_CONF_SPMASK))
1969 printk(", No speed/duplex selected?");
1971 if (status & PHY_CONF_LOOP)
1972 printk(", loopback enabled");
1974 printk(".\n");
1976 fep->sequence_done = 1;
1979 static void mii_relink(struct net_device *dev)
1981 struct fec_enet_private *fep = netdev_priv(dev);
1982 int duplex;
1985 ** When we get here, phy_task is already removed from
1986 ** the workqueue. It is thus safe to allow to reuse it.
1988 fep->mii_phy_task_queued = 0;
1989 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1990 mii_display_status(dev);
1991 fep->old_link = fep->link;
1993 if (fep->link) {
1994 duplex = 0;
1995 if (fep->phy_status
1996 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1997 duplex = 1;
1998 fec_restart(dev, duplex);
2000 else
2001 fec_stop(dev);
2003 #if 0
2004 enable_irq(fep->mii_irq);
2005 #endif
2009 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2010 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2012 struct fec_enet_private *fep = netdev_priv(dev);
2015 ** We cannot queue phy_task twice in the workqueue. It
2016 ** would cause an endless loop in the workqueue.
2017 ** Fortunately, if the last mii_relink entry has not yet been
2018 ** executed now, it will do the job for the current interrupt,
2019 ** which is just what we want.
2021 if (fep->mii_phy_task_queued)
2022 return;
2024 fep->mii_phy_task_queued = 1;
2025 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
2026 schedule_work(&fep->phy_task);
2029 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2030 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2032 struct fec_enet_private *fep = netdev_priv(dev);
2034 if (fep->mii_phy_task_queued)
2035 return;
2037 fep->mii_phy_task_queued = 1;
2038 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
2039 schedule_work(&fep->phy_task);
2042 phy_cmd_t const phy_cmd_relink[] = {
2043 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2044 { mk_mii_end, }
2046 phy_cmd_t const phy_cmd_config[] = {
2047 { mk_mii_read(MII_REG_CR), mii_queue_config },
2048 { mk_mii_end, }
2051 /* Read remainder of PHY ID.
2053 static void
2054 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2056 struct fec_enet_private *fep;
2057 int i;
2059 fep = netdev_priv(dev);
2060 fep->phy_id |= (mii_reg & 0xffff);
2061 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2063 for(i = 0; phy_info[i]; i++) {
2064 if(phy_info[i]->id == (fep->phy_id >> 4))
2065 break;
2068 if (phy_info[i])
2069 printk(" -- %s\n", phy_info[i]->name);
2070 else
2071 printk(" -- unknown PHY!\n");
2073 fep->phy = phy_info[i];
2074 fep->phy_id_done = 1;
2077 /* Scan all of the MII PHY addresses looking for someone to respond
2078 * with a valid ID. This usually happens quickly.
2080 static void
2081 mii_discover_phy(uint mii_reg, struct net_device *dev)
2083 struct fec_enet_private *fep;
2084 volatile fec_t *fecp;
2085 uint phytype;
2087 fep = netdev_priv(dev);
2088 fecp = fep->hwp;
2090 if (fep->phy_addr < 32) {
2091 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2093 /* Got first part of ID, now get remainder.
2095 fep->phy_id = phytype << 16;
2096 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2097 mii_discover_phy3);
2099 else {
2100 fep->phy_addr++;
2101 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2102 mii_discover_phy);
2104 } else {
2105 printk("FEC: No PHY device found.\n");
2106 /* Disable external MII interface */
2107 fecp->fec_mii_speed = fep->phy_speed = 0;
2108 fec_disable_phy_intr();
2112 /* This interrupt occurs when the PHY detects a link change.
2114 #ifdef CONFIG_RPXCLASSIC
2115 static void
2116 mii_link_interrupt(void *dev_id)
2117 #else
2118 static irqreturn_t
2119 mii_link_interrupt(int irq, void * dev_id)
2120 #endif
2122 struct net_device *dev = dev_id;
2123 struct fec_enet_private *fep = netdev_priv(dev);
2125 fec_phy_ack_intr();
2127 #if 0
2128 disable_irq(fep->mii_irq); /* disable now, enable later */
2129 #endif
2131 mii_do_cmd(dev, fep->phy->ack_int);
2132 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2134 return IRQ_HANDLED;
2137 static int
2138 fec_enet_open(struct net_device *dev)
2140 struct fec_enet_private *fep = netdev_priv(dev);
2142 /* I should reset the ring buffers here, but I don't yet know
2143 * a simple way to do that.
2145 fec_set_mac_address(dev);
2147 fep->sequence_done = 0;
2148 fep->link = 0;
2150 if (fep->phy) {
2151 mii_do_cmd(dev, fep->phy->ack_int);
2152 mii_do_cmd(dev, fep->phy->config);
2153 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2155 /* Poll until the PHY tells us its configuration
2156 * (not link state).
2157 * Request is initiated by mii_do_cmd above, but answer
2158 * comes by interrupt.
2159 * This should take about 25 usec per register at 2.5 MHz,
2160 * and we read approximately 5 registers.
2162 while(!fep->sequence_done)
2163 schedule();
2165 mii_do_cmd(dev, fep->phy->startup);
2167 /* Set the initial link state to true. A lot of hardware
2168 * based on this device does not implement a PHY interrupt,
2169 * so we are never notified of link change.
2171 fep->link = 1;
2172 } else {
2173 fep->link = 1; /* lets just try it and see */
2174 /* no phy, go full duplex, it's most likely a hub chip */
2175 fec_restart(dev, 1);
2178 netif_start_queue(dev);
2179 fep->opened = 1;
2180 return 0; /* Success */
2183 static int
2184 fec_enet_close(struct net_device *dev)
2186 struct fec_enet_private *fep = netdev_priv(dev);
2188 /* Don't know what to do yet.
2190 fep->opened = 0;
2191 netif_stop_queue(dev);
2192 fec_stop(dev);
2194 return 0;
2197 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2199 struct fec_enet_private *fep = netdev_priv(dev);
2201 return &fep->stats;
2204 /* Set or clear the multicast filter for this adaptor.
2205 * Skeleton taken from sunlance driver.
2206 * The CPM Ethernet implementation allows Multicast as well as individual
2207 * MAC address filtering. Some of the drivers check to make sure it is
2208 * a group multicast address, and discard those that are not. I guess I
2209 * will do the same for now, but just remove the test if you want
2210 * individual filtering as well (do the upper net layers want or support
2211 * this kind of feature?).
2214 #define HASH_BITS 6 /* #bits in hash */
2215 #define CRC32_POLY 0xEDB88320
2217 static void set_multicast_list(struct net_device *dev)
2219 struct fec_enet_private *fep;
2220 volatile fec_t *ep;
2221 struct dev_mc_list *dmi;
2222 unsigned int i, j, bit, data, crc;
2223 unsigned char hash;
2225 fep = netdev_priv(dev);
2226 ep = fep->hwp;
2228 if (dev->flags&IFF_PROMISC) {
2229 ep->fec_r_cntrl |= 0x0008;
2230 } else {
2232 ep->fec_r_cntrl &= ~0x0008;
2234 if (dev->flags & IFF_ALLMULTI) {
2235 /* Catch all multicast addresses, so set the
2236 * filter to all 1's.
2238 ep->fec_hash_table_high = 0xffffffff;
2239 ep->fec_hash_table_low = 0xffffffff;
2240 } else {
2241 /* Clear filter and add the addresses in hash register.
2243 ep->fec_hash_table_high = 0;
2244 ep->fec_hash_table_low = 0;
2246 dmi = dev->mc_list;
2248 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2250 /* Only support group multicast for now.
2252 if (!(dmi->dmi_addr[0] & 1))
2253 continue;
2255 /* calculate crc32 value of mac address
2257 crc = 0xffffffff;
2259 for (i = 0; i < dmi->dmi_addrlen; i++)
2261 data = dmi->dmi_addr[i];
2262 for (bit = 0; bit < 8; bit++, data >>= 1)
2264 crc = (crc >> 1) ^
2265 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2269 /* only upper 6 bits (HASH_BITS) are used
2270 which point to specific bit in he hash registers
2272 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2274 if (hash > 31)
2275 ep->fec_hash_table_high |= 1 << (hash - 32);
2276 else
2277 ep->fec_hash_table_low |= 1 << hash;
2283 /* Set a MAC change in hardware.
2285 static void
2286 fec_set_mac_address(struct net_device *dev)
2288 volatile fec_t *fecp;
2290 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2292 /* Set station address. */
2293 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2294 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2295 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2296 (dev->dev_addr[4] << 24);
2300 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2303 * XXX: We need to clean up on failure exits here.
2305 int __init fec_enet_init(struct net_device *dev)
2307 struct fec_enet_private *fep = netdev_priv(dev);
2308 unsigned long mem_addr;
2309 volatile cbd_t *bdp;
2310 cbd_t *cbd_base;
2311 volatile fec_t *fecp;
2312 int i, j;
2313 static int index = 0;
2315 /* Only allow us to be probed once. */
2316 if (index >= FEC_MAX_PORTS)
2317 return -ENXIO;
2319 /* Allocate memory for buffer descriptors.
2321 mem_addr = __get_free_page(GFP_KERNEL);
2322 if (mem_addr == 0) {
2323 printk("FEC: allocate descriptor memory failed?\n");
2324 return -ENOMEM;
2327 /* Create an Ethernet device instance.
2329 fecp = (volatile fec_t *) fec_hw[index];
2331 fep->index = index;
2332 fep->hwp = fecp;
2334 /* Whack a reset. We should wait for this.
2336 fecp->fec_ecntrl = 1;
2337 udelay(10);
2339 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2340 * this needs some work to get unique addresses.
2342 * This is our default MAC address unless the user changes
2343 * it via eth_mac_addr (our dev->set_mac_addr handler).
2345 fec_get_mac(dev);
2347 cbd_base = (cbd_t *)mem_addr;
2348 /* XXX: missing check for allocation failure */
2350 fec_uncache(mem_addr);
2352 /* Set receive and transmit descriptor base.
2354 fep->rx_bd_base = cbd_base;
2355 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2357 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2358 fep->cur_rx = fep->rx_bd_base;
2360 fep->skb_cur = fep->skb_dirty = 0;
2362 /* Initialize the receive buffer descriptors.
2364 bdp = fep->rx_bd_base;
2365 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2367 /* Allocate a page.
2369 mem_addr = __get_free_page(GFP_KERNEL);
2370 /* XXX: missing check for allocation failure */
2372 fec_uncache(mem_addr);
2374 /* Initialize the BD for every fragment in the page.
2376 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2377 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2378 bdp->cbd_bufaddr = __pa(mem_addr);
2379 mem_addr += FEC_ENET_RX_FRSIZE;
2380 bdp++;
2384 /* Set the last buffer to wrap.
2386 bdp--;
2387 bdp->cbd_sc |= BD_SC_WRAP;
2389 /* ...and the same for transmmit.
2391 bdp = fep->tx_bd_base;
2392 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2393 if (j >= FEC_ENET_TX_FRPPG) {
2394 mem_addr = __get_free_page(GFP_KERNEL);
2395 j = 1;
2396 } else {
2397 mem_addr += FEC_ENET_TX_FRSIZE;
2398 j++;
2400 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2402 /* Initialize the BD for every fragment in the page.
2404 bdp->cbd_sc = 0;
2405 bdp->cbd_bufaddr = 0;
2406 bdp++;
2409 /* Set the last buffer to wrap.
2411 bdp--;
2412 bdp->cbd_sc |= BD_SC_WRAP;
2414 /* Set receive and transmit descriptor base.
2416 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2417 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2419 /* Install our interrupt handlers. This varies depending on
2420 * the architecture.
2422 fec_request_intrs(dev);
2424 fecp->fec_hash_table_high = 0;
2425 fecp->fec_hash_table_low = 0;
2426 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2427 fecp->fec_ecntrl = 2;
2428 fecp->fec_r_des_active = 0;
2430 dev->base_addr = (unsigned long)fecp;
2432 /* The FEC Ethernet specific entries in the device structure. */
2433 dev->open = fec_enet_open;
2434 dev->hard_start_xmit = fec_enet_start_xmit;
2435 dev->tx_timeout = fec_timeout;
2436 dev->watchdog_timeo = TX_TIMEOUT;
2437 dev->stop = fec_enet_close;
2438 dev->get_stats = fec_enet_get_stats;
2439 dev->set_multicast_list = set_multicast_list;
2441 for (i=0; i<NMII-1; i++)
2442 mii_cmds[i].mii_next = &mii_cmds[i+1];
2443 mii_free = mii_cmds;
2445 /* setup MII interface */
2446 fec_set_mii(dev, fep);
2448 /* Clear and enable interrupts */
2449 fecp->fec_ievent = 0xffc00000;
2450 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2451 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2453 /* Queue up command to detect the PHY and initialize the
2454 * remainder of the interface.
2456 fep->phy_id_done = 0;
2457 fep->phy_addr = 0;
2458 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2460 index++;
2461 return 0;
2464 /* This function is called to start or restart the FEC during a link
2465 * change. This only happens when switching between half and full
2466 * duplex.
2468 static void
2469 fec_restart(struct net_device *dev, int duplex)
2471 struct fec_enet_private *fep;
2472 volatile cbd_t *bdp;
2473 volatile fec_t *fecp;
2474 int i;
2476 fep = netdev_priv(dev);
2477 fecp = fep->hwp;
2479 /* Whack a reset. We should wait for this.
2481 fecp->fec_ecntrl = 1;
2482 udelay(10);
2484 /* Clear any outstanding interrupt.
2486 fecp->fec_ievent = 0xffc00000;
2487 fec_enable_phy_intr();
2489 /* Set station address.
2491 fec_set_mac_address(dev);
2493 /* Reset all multicast.
2495 fecp->fec_hash_table_high = 0;
2496 fecp->fec_hash_table_low = 0;
2498 /* Set maximum receive buffer size.
2500 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2502 fec_localhw_setup();
2504 /* Set receive and transmit descriptor base.
2506 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2507 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2509 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2510 fep->cur_rx = fep->rx_bd_base;
2512 /* Reset SKB transmit buffers.
2514 fep->skb_cur = fep->skb_dirty = 0;
2515 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2516 if (fep->tx_skbuff[i] != NULL) {
2517 dev_kfree_skb_any(fep->tx_skbuff[i]);
2518 fep->tx_skbuff[i] = NULL;
2522 /* Initialize the receive buffer descriptors.
2524 bdp = fep->rx_bd_base;
2525 for (i=0; i<RX_RING_SIZE; i++) {
2527 /* Initialize the BD for every fragment in the page.
2529 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2530 bdp++;
2533 /* Set the last buffer to wrap.
2535 bdp--;
2536 bdp->cbd_sc |= BD_SC_WRAP;
2538 /* ...and the same for transmmit.
2540 bdp = fep->tx_bd_base;
2541 for (i=0; i<TX_RING_SIZE; i++) {
2543 /* Initialize the BD for every fragment in the page.
2545 bdp->cbd_sc = 0;
2546 bdp->cbd_bufaddr = 0;
2547 bdp++;
2550 /* Set the last buffer to wrap.
2552 bdp--;
2553 bdp->cbd_sc |= BD_SC_WRAP;
2555 /* Enable MII mode.
2557 if (duplex) {
2558 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2559 fecp->fec_x_cntrl = 0x04; /* FD enable */
2561 else {
2562 /* MII enable|No Rcv on Xmit */
2563 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2564 fecp->fec_x_cntrl = 0x00;
2566 fep->full_duplex = duplex;
2568 /* Set MII speed.
2570 fecp->fec_mii_speed = fep->phy_speed;
2572 /* And last, enable the transmit and receive processing.
2574 fecp->fec_ecntrl = 2;
2575 fecp->fec_r_des_active = 0;
2577 /* Enable interrupts we wish to service.
2579 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2580 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2583 static void
2584 fec_stop(struct net_device *dev)
2586 volatile fec_t *fecp;
2587 struct fec_enet_private *fep;
2589 fep = netdev_priv(dev);
2590 fecp = fep->hwp;
2593 ** We cannot expect a graceful transmit stop without link !!!
2595 if (fep->link)
2597 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2598 udelay(10);
2599 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2600 printk("fec_stop : Graceful transmit stop did not complete !\n");
2603 /* Whack a reset. We should wait for this.
2605 fecp->fec_ecntrl = 1;
2606 udelay(10);
2608 /* Clear outstanding MII command interrupts.
2610 fecp->fec_ievent = FEC_ENET_MII;
2611 fec_enable_phy_intr();
2613 fecp->fec_imask = FEC_ENET_MII;
2614 fecp->fec_mii_speed = fep->phy_speed;
2617 static int __init fec_enet_module_init(void)
2619 struct net_device *dev;
2620 int i, j, err;
2622 printk("FEC ENET Version 0.2\n");
2624 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2625 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2626 if (!dev)
2627 return -ENOMEM;
2628 err = fec_enet_init(dev);
2629 if (err) {
2630 free_netdev(dev);
2631 continue;
2633 if (register_netdev(dev) != 0) {
2634 /* XXX: missing cleanup here */
2635 free_netdev(dev);
2636 return -EIO;
2639 printk("%s: ethernet ", dev->name);
2640 for (j = 0; (j < 5); j++)
2641 printk("%02x:", dev->dev_addr[j]);
2642 printk("%02x\n", dev->dev_addr[5]);
2644 return 0;
2647 module_init(fec_enet_module_init);
2649 MODULE_LICENSE("GPL");