arch/parisc/kernel/cache.c

   1 /* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
   8  * Copyright (C) 1999 SuSE GmbH Nuernberg
   9  * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
  10  *
  11  * Cache and TLB management
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/pagemap.h>
  21
  22 #include <asm/pdc.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheflush.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/system.h>
  27 #include <asm/page.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/processor.h>
  30 #include <asm/sections.h>
  31
  32 int split_tlb __read_mostly;
  33 int dcache_stride __read_mostly;
  34 int icache_stride __read_mostly;
  35 EXPORT_SYMBOL(dcache_stride);
  36
  37
  38 #if defined(CONFIG_SMP)
  39 /* On some machines (e.g. ones with the Merced bus), there can be
  40  * only a single PxTLB broadcast at a time; this must be guaranteed
  41  * by software.  We put a spinlock around all TLB flushes  to
  42  * ensure this.
  43  */
  44 DEFINE_SPINLOCK(pa_tlb_lock);
  45 EXPORT_SYMBOL(pa_tlb_lock);
  46 #endif
  47
  48 struct pdc_cache_info cache_info __read_mostly;
  49 #ifndef CONFIG_PA20
  50 static struct pdc_btlb_info btlb_info __read_mostly;
  51 #endif
  52
  53 #ifdef CONFIG_SMP
  54 void
  55 flush_data_cache(void)
  56 {
  57         on_each_cpu(flush_data_cache_local, NULL, 1, 1);
  58 }
  59 void
  60 flush_instruction_cache(void)
  61 {
  62         on_each_cpu(flush_instruction_cache_local, NULL, 1, 1);
  63 }
  64 #endif
  65
  66 void
  67 flush_cache_all_local(void)
  68 {
  69         flush_instruction_cache_local(NULL);
  70         flush_data_cache_local(NULL);
  71 }
  72 EXPORT_SYMBOL(flush_cache_all_local);
  73
  74 /* flushes EVERYTHING (tlb & cache) */
  75
  76 void
  77 flush_all_caches(void)
  78 {
  79         flush_cache_all();
  80         flush_tlb_all();
  81 }
  82 EXPORT_SYMBOL(flush_all_caches);
  83
  84 void
  85 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  86 {
  87         struct page *page = pte_page(pte);
  88
  89         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
  90             test_bit(PG_dcache_dirty, &page->flags)) {
  91
  92                 flush_kernel_dcache_page(page);
  93                 clear_bit(PG_dcache_dirty, &page->flags);
  94         } else if (parisc_requires_coherency())
  95                 flush_kernel_dcache_page(page);
  96 }
  97
  98 void
  99 show_cache_info(struct seq_file *m)
 100 {
 101         char buf[32];
 102
 103         seq_printf(m, "I-cache\t\t: %ld KB\n",
 104                 cache_info.ic_size/1024 );
 105         if (cache_info.dc_loop == 1)
 106                 snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
 107         seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
 108                 cache_info.dc_size/1024,
 109                 (cache_info.dc_conf.cc_wt ? "WT":"WB"),
 110                 (cache_info.dc_conf.cc_sh ? ", shared I/D":""),
 111                 ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
 112         seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
 113                 cache_info.it_size,
 114                 cache_info.dt_size,
 115                 cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
 116         );
 117
 118 #ifndef CONFIG_PA20
 119         /* BTLB - Block TLB */
 120         if (btlb_info.max_size==0) {
 121                 seq_printf(m, "BTLB\t\t: not supported\n" );
 122         } else {
 123                 seq_printf(m,
 124                 "BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
 125                 "BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
 126                 "BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
 127                 btlb_info.max_size, (int)4096,
 128                 btlb_info.max_size>>8,
 129                 btlb_info.fixed_range_info.num_i,
 130                 btlb_info.fixed_range_info.num_d,
 131                 btlb_info.fixed_range_info.num_comb,
 132                 btlb_info.variable_range_info.num_i,
 133                 btlb_info.variable_range_info.num_d,
 134                 btlb_info.variable_range_info.num_comb
 135                 );
 136         }
 137 #endif
 138 }
 139
 140 void __init
 141 parisc_cache_init(void)
 142 {
 143         if (pdc_cache_info(&cache_info) < 0)
 144                 panic("parisc_cache_init: pdc_cache_info failed");
 145
 146 #if 0
 147         printk("ic_size %lx dc_size %lx it_size %lx\n",
 148                 cache_info.ic_size,
 149                 cache_info.dc_size,
 150                 cache_info.it_size);
 151
 152         printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 153                 cache_info.dc_base,
 154                 cache_info.dc_stride,
 155                 cache_info.dc_count,
 156                 cache_info.dc_loop);
 157
 158         printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 159                 *(unsigned long *) (&cache_info.dc_conf),
 160                 cache_info.dc_conf.cc_alias,
 161                 cache_info.dc_conf.cc_block,
 162                 cache_info.dc_conf.cc_line,
 163                 cache_info.dc_conf.cc_shift);
 164         printk("        wt %d sh %d cst %d hv %d\n",
 165                 cache_info.dc_conf.cc_wt,
 166                 cache_info.dc_conf.cc_sh,
 167                 cache_info.dc_conf.cc_cst,
 168                 cache_info.dc_conf.cc_hv);
 169
 170         printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
 171                 cache_info.ic_base,
 172                 cache_info.ic_stride,
 173                 cache_info.ic_count,
 174                 cache_info.ic_loop);
 175
 176         printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
 177                 *(unsigned long *) (&cache_info.ic_conf),
 178                 cache_info.ic_conf.cc_alias,
 179                 cache_info.ic_conf.cc_block,
 180                 cache_info.ic_conf.cc_line,
 181                 cache_info.ic_conf.cc_shift);
 182         printk("        wt %d sh %d cst %d hv %d\n",
 183                 cache_info.ic_conf.cc_wt,
 184                 cache_info.ic_conf.cc_sh,
 185                 cache_info.ic_conf.cc_cst,
 186                 cache_info.ic_conf.cc_hv);
 187
 188         printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 189                 cache_info.dt_conf.tc_sh,
 190                 cache_info.dt_conf.tc_page,
 191                 cache_info.dt_conf.tc_cst,
 192                 cache_info.dt_conf.tc_aid,
 193                 cache_info.dt_conf.tc_pad1);
 194
 195         printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
 196                 cache_info.it_conf.tc_sh,
 197                 cache_info.it_conf.tc_page,
 198                 cache_info.it_conf.tc_cst,
 199                 cache_info.it_conf.tc_aid,
 200                 cache_info.it_conf.tc_pad1);
 201 #endif
 202
 203         split_tlb = 0;
 204         if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
 205                 if (cache_info.dt_conf.tc_sh == 2)
 206                         printk(KERN_WARNING "Unexpected TLB configuration. "
 207                         "Will flush I/D separately (could be optimized).\n");
 208
 209                 split_tlb = 1;
 210         }
 211
 212         /* "New and Improved" version from Jim Hull
 213          *      (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
 214          * The following CAFL_STRIDE is an optimized version, see
 215          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
 216          * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
 217          */
 218 #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
 219         dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
 220         icache_stride = CAFL_STRIDE(cache_info.ic_conf);
 221 #undef CAFL_STRIDE
 222
 223 #ifndef CONFIG_PA20
 224         if (pdc_btlb_info(&btlb_info) < 0) {
 225                 memset(&btlb_info, 0, sizeof btlb_info);
 226         }
 227 #endif
 228
 229         if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
 230                                                 PDC_MODEL_NVA_UNSUPPORTED) {
 231                 printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
 232 #if 0
 233                 panic("SMP kernel required to avoid non-equivalent aliasing");
 234 #endif
 235         }
 236 }
 237
 238 void disable_sr_hashing(void)
 239 {
 240         int srhash_type, retval;
 241         unsigned long space_bits;
 242
 243         switch (boot_cpu_data.cpu_type) {
 244         case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
 245                 BUG();
 246                 return;
 247
 248         case pcxs:
 249         case pcxt:
 250         case pcxt_:
 251                 srhash_type = SRHASH_PCXST;
 252                 break;
 253
 254         case pcxl:
 255                 srhash_type = SRHASH_PCXL;
 256                 break;
 257
 258         case pcxl2: /* pcxl2 doesn't support space register hashing */
 259                 return;
 260
 261         default: /* Currently all PA2.0 machines use the same ins. sequence */
 262                 srhash_type = SRHASH_PA20;
 263                 break;
 264         }
 265
 266         disable_sr_hashing_asm(srhash_type);
 267
 268         retval = pdc_spaceid_bits(&space_bits);
 269         /* If this procedure isn't implemented, don't panic. */
 270         if (retval < 0 && retval != PDC_BAD_OPTION)
 271                 panic("pdc_spaceid_bits call failed.\n");
 272         if (space_bits != 0)
 273                 panic("SpaceID hashing is still on!\n");
 274 }
 275
 276 void flush_dcache_page(struct page *page)
 277 {
 278         struct address_space *mapping = page_mapping(page);
 279         struct vm_area_struct *mpnt;
 280         struct prio_tree_iter iter;
 281         unsigned long offset;
 282         unsigned long addr;
 283         pgoff_t pgoff;
 284         unsigned long pfn = page_to_pfn(page);
 285
 286
 287         if (mapping && !mapping_mapped(mapping)) {
 288                 set_bit(PG_dcache_dirty, &page->flags);
 289                 return;
 290         }
 291
 292         flush_kernel_dcache_page(page);
 293
 294         if (!mapping)
 295                 return;
 296
 297         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 298
 299         /* We have carefully arranged in arch_get_unmapped_area() that
 300          * *any* mappings of a file are always congruently mapped (whether
 301          * declared as MAP_PRIVATE or MAP_SHARED), so we only need
 302          * to flush one address here for them all to become coherent */
 303
 304         flush_dcache_mmap_lock(mapping);
 305         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 306                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 307                 addr = mpnt->vm_start + offset;
 308
 309                 /* Flush instructions produce non access tlb misses.
 310                  * On PA, we nullify these instructions rather than
 311                  * taking a page fault if the pte doesn't exist.
 312                  * This is just for speed.  If the page translation
 313                  * isn't there, there's no point exciting the
 314                  * nadtlb handler into a nullification frenzy.
 315                  *
 316                  * Make sure we really have this page: the private
 317                  * mappings may cover this area but have COW'd this
 318                  * particular page.
 319                  */
 320                 if (translation_exists(mpnt, addr, pfn)) {
 321                         __flush_cache_page(mpnt, addr);
 322                         break;
 323                 }
 324         }
 325         flush_dcache_mmap_unlock(mapping);
 326 }
 327 EXPORT_SYMBOL(flush_dcache_page);
 328
 329 /* Defined in arch/parisc/kernel/pacache.S */
 330 EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
 331 EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
 332 EXPORT_SYMBOL(flush_data_cache_local);
 333 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
 334
 335 void clear_user_page_asm(void *page, unsigned long vaddr)
 336 {
 337         /* This function is implemented in assembly in pacache.S */
 338         extern void __clear_user_page_asm(void *page, unsigned long vaddr);
 339
 340         purge_tlb_start();
 341         __clear_user_page_asm(page, vaddr);
 342         purge_tlb_end();
 343 }
 344
 345 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
 346 int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
 347
 348 void parisc_setup_cache_timing(void)
 349 {
 350         unsigned long rangetime, alltime;
 351         unsigned long size;
 352
 353         alltime = mfctl(16);
 354         flush_data_cache();
 355         alltime = mfctl(16) - alltime;
 356
 357         size = (unsigned long)(_end - _text);
 358         rangetime = mfctl(16);
 359         flush_kernel_dcache_range((unsigned long)_text, size);
 360         rangetime = mfctl(16) - rangetime;
 361
 362         printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
 363                 alltime, size, rangetime);
 364
 365         /* Racy, but if we see an intermediate value, it's ok too... */
 366         parisc_cache_flush_threshold = size * alltime / rangetime;
 367
 368         parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
 369         if (!parisc_cache_flush_threshold)
 370                 parisc_cache_flush_threshold = FLUSH_THRESHOLD;
 371
 372         printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
 373 }
 374
 375 extern void purge_kernel_dcache_page(unsigned long);
 376 extern void clear_user_page_asm(void *page, unsigned long vaddr);
 377
 378 void
 379 clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 380 {
 381         purge_kernel_dcache_page((unsigned long)page);
 382         purge_tlb_start();
 383         pdtlb_kernel(page);
 384         purge_tlb_end();
 385         clear_user_page_asm(page, vaddr);
 386 }
 387
 388 void flush_kernel_dcache_page_addr(void *addr)
 389 {
 390         flush_kernel_dcache_page_asm(addr);
 391         purge_tlb_start();
 392         pdtlb_kernel(addr);
 393         purge_tlb_end();
 394 }
 395 EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
 396
 397 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 398                     struct page *pg)
 399 {
 400         /* no coherency needed (all in kmap/kunmap) */
 401         copy_user_page_asm(vto, vfrom);
 402         if (!parisc_requires_coherency())
 403                 flush_kernel_dcache_page_asm(vto);
 404 }
 405 EXPORT_SYMBOL(copy_user_page);
 406
 407 #ifdef CONFIG_PA8X00
 408
 409 void kunmap_parisc(void *addr)
 410 {
 411         if (parisc_requires_coherency())
 412                 flush_kernel_dcache_page_addr(addr);
 413 }
 414 EXPORT_SYMBOL(kunmap_parisc);
 415 #endif