arch/ppc/platforms/83xx/mpc834x_sys.c

   1 /*
   2  * arch/ppc/platforms/83xx/mpc834x_sys.c
   3  *
   4  * MPC834x SYS board specific routines
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2005 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/major.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/root_dev.h>
  30 #include <linux/serial.h>
  31 #include <linux/tty.h>  /* for linux/serial_core.h */
  32 #include <linux/serial_core.h>
  33 #include <linux/initrd.h>
  34 #include <linux/module.h>
  35 #include <linux/fsl_devices.h>
  36
  37 #include <asm/system.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/page.h>
  40 #include <asm/atomic.h>
  41 #include <asm/time.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/ipic.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/pci-bridge.h>
  47 #include <asm/mpc83xx.h>
  48 #include <asm/irq.h>
  49 #include <asm/kgdb.h>
  50 #include <asm/ppc_sys.h>
  51 #include <mm/mmu_decl.h>
  52
  53 #include <syslib/ppc83xx_setup.h>
  54
  55 #ifndef CONFIG_PCI
  56 unsigned long isa_io_base = 0;
  57 unsigned long isa_mem_base = 0;
  58 #endif
  59
  60 extern unsigned long total_memory;      /* in mm/init */
  61
  62 unsigned char __res[sizeof (bd_t)];
  63
  64 #ifdef CONFIG_PCI
  65 int
  66 mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  67 {
  68         static char pci_irq_table[][4] =
  69             /*
  70              *      PCI IDSEL/INTPIN->INTLINE
  71              *       A      B      C      D
  72              */
  73         {
  74                 {PIRQA, PIRQB,  PIRQC,  PIRQD}, /* idsel 0x11 */
  75                 {PIRQC, PIRQD,  PIRQA,  PIRQB}, /* idsel 0x12 */
  76                 {PIRQD, PIRQA,  PIRQB,  PIRQC}  /* idsel 0x13 */
  77         };
  78
  79         const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
  80         return PCI_IRQ_TABLE_LOOKUP;
  81 }
  82
  83 int
  84 mpc83xx_exclude_device(u_char bus, u_char devfn)
  85 {
  86         return PCIBIOS_SUCCESSFUL;
  87 }
  88 #endif /* CONFIG_PCI */
  89
  90 /* ************************************************************************
  91  *
  92  * Setup the architecture
  93  *
  94  */
  95 static void __init
  96 mpc834x_sys_setup_arch(void)
  97 {
  98         bd_t *binfo = (bd_t *) __res;
  99         unsigned int freq;
 100         struct gianfar_platform_data *pdata;
 101
 102         /* get the core frequency */
 103         freq = binfo->bi_intfreq;
 104
 105         /* Set loops_per_jiffy to a half-way reasonable value,
 106            for use until calibrate_delay gets called. */
 107         loops_per_jiffy = freq / HZ;
 108
 109 #ifdef CONFIG_PCI
 110         /* setup PCI host bridges */
 111         mpc83xx_setup_hose();
 112 #endif
 113         mpc83xx_early_serial_map();
 114
 115         /* setup the board related information for the enet controllers */
 116         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
 117         if (pdata) {
 118                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 119                 pdata->interruptPHY = MPC83xx_IRQ_EXT1;
 120                 pdata->phyid = 0;
 121                 /* fixup phy address */
 122                 pdata->phy_reg_addr += binfo->bi_immr_base;
 123                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 124         }
 125
 126         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
 127         if (pdata) {
 128                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 129                 pdata->interruptPHY = MPC83xx_IRQ_EXT2;
 130                 pdata->phyid = 1;
 131                 /* fixup phy address */
 132                 pdata->phy_reg_addr += binfo->bi_immr_base;
 133                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 134         }
 135
 136 #ifdef CONFIG_BLK_DEV_INITRD
 137         if (initrd_start)
 138                 ROOT_DEV = Root_RAM0;
 139         else
 140 #endif
 141 #ifdef  CONFIG_ROOT_NFS
 142                 ROOT_DEV = Root_NFS;
 143 #else
 144                 ROOT_DEV = Root_HDA1;
 145 #endif
 146 }
 147
 148 static void __init
 149 mpc834x_sys_map_io(void)
 150 {
 151         /* we steal the lowest ioremap addr for virt space */
 152         io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
 153 }
 154
 155 int
 156 mpc834x_sys_show_cpuinfo(struct seq_file *m)
 157 {
 158         uint pvid, svid, phid1;
 159         bd_t *binfo = (bd_t *) __res;
 160         unsigned int freq;
 161
 162         /* get the core frequency */
 163         freq = binfo->bi_intfreq;
 164
 165         pvid = mfspr(SPRN_PVR);
 166         svid = mfspr(SPRN_SVR);
 167
 168         seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
 169         seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
 170         seq_printf(m, "core clock\t: %d MHz\n"
 171                         "bus  clock\t: %d MHz\n",
 172                         (int)(binfo->bi_intfreq / 1000000),
 173                         (int)(binfo->bi_busfreq / 1000000));
 174         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 175         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 176
 177         /* Display cpu Pll setting */
 178         phid1 = mfspr(SPRN_HID1);
 179         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 180
 181         /* Display the amount of memory */
 182         seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024)));
 183
 184         return 0;
 185 }
 186
 187
 188 void __init
 189 mpc834x_sys_init_IRQ(void)
 190 {
 191         bd_t *binfo = (bd_t *) __res;
 192
 193         u8 senses[8] = {
 194                 0,                      /* EXT 0 */
 195                 IRQ_SENSE_LEVEL,        /* EXT 1 */
 196                 IRQ_SENSE_LEVEL,        /* EXT 2 */
 197                 0,                      /* EXT 3 */
 198 #ifdef CONFIG_PCI
 199                 IRQ_SENSE_LEVEL,        /* EXT 4 */
 200                 IRQ_SENSE_LEVEL,        /* EXT 5 */
 201                 IRQ_SENSE_LEVEL,        /* EXT 6 */
 202                 IRQ_SENSE_LEVEL,        /* EXT 7 */
 203 #else
 204                 0,                      /* EXT 4 */
 205                 0,                      /* EXT 5 */
 206                 0,                      /* EXT 6 */
 207                 0,                      /* EXT 7 */
 208 #endif
 209         };
 210
 211         ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
 212
 213         /* Initialize the default interrupt mapping priorities,
 214          * in case the boot rom changed something on us.
 215          */
 216         ipic_set_default_priority();
 217 }
 218
 219 #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
 220 extern ulong    ds1374_get_rtc_time(void);
 221 extern int      ds1374_set_rtc_time(ulong);
 222
 223 static int __init
 224 mpc834x_rtc_hookup(void)
 225 {
 226         struct timespec tv;
 227
 228         ppc_md.get_rtc_time = ds1374_get_rtc_time;
 229         ppc_md.set_rtc_time = ds1374_set_rtc_time;
 230
 231         tv.tv_nsec = 0;
 232         tv.tv_sec = (ppc_md.get_rtc_time)();
 233         do_settimeofday(&tv);
 234
 235         return 0;
 236 }
 237 late_initcall(mpc834x_rtc_hookup);
 238 #endif
 239 static __inline__ void
 240 mpc834x_sys_set_bat(void)
 241 {
 242         /* we steal the lowest ioremap addr for virt space */
 243         mb();
 244         mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e);
 245         mtspr(SPRN_DBAT1L, immrbar | 0x2a);
 246         mb();
 247 }
 248
 249 void __init
 250 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 251               unsigned long r6, unsigned long r7)
 252 {
 253         bd_t *binfo = (bd_t *) __res;
 254
 255         /* parse_bootinfo must always be called first */
 256         parse_bootinfo(find_bootinfo());
 257
 258         /*
 259          * If we were passed in a board information, copy it into the
 260          * residual data area.
 261          */
 262         if (r3) {
 263                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 264                        sizeof (bd_t));
 265         }
 266
 267 #if defined(CONFIG_BLK_DEV_INITRD)
 268         /*
 269          * If the init RAM disk has been configured in, and there's a valid
 270          * starting address for it, set it up.
 271          */
 272         if (r4) {
 273                 initrd_start = r4 + KERNELBASE;
 274                 initrd_end = r5 + KERNELBASE;
 275         }
 276 #endif /* CONFIG_BLK_DEV_INITRD */
 277
 278         /* Copy the kernel command line arguments to a safe place. */
 279         if (r6) {
 280                 *(char *) (r7 + KERNELBASE) = 0;
 281                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 282         }
 283
 284         immrbar = binfo->bi_immr_base;
 285
 286         mpc834x_sys_set_bat();
 287
 288 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 289         {
 290                 struct uart_port p;
 291
 292                 memset(&p, 0, sizeof (p));
 293                 p.iotype = SERIAL_IO_MEM;
 294                 p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
 295                 p.uartclk = binfo->bi_busfreq;
 296
 297                 gen550_init(0, &p);
 298
 299                 memset(&p, 0, sizeof (p));
 300                 p.iotype = SERIAL_IO_MEM;
 301                 p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
 302                 p.uartclk = binfo->bi_busfreq;
 303
 304                 gen550_init(1, &p);
 305         }
 306 #endif
 307
 308         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 309
 310         /* setup the PowerPC module struct */
 311         ppc_md.setup_arch = mpc834x_sys_setup_arch;
 312         ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo;
 313
 314         ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
 315         ppc_md.get_irq = ipic_get_irq;
 316
 317         ppc_md.restart = mpc83xx_restart;
 318         ppc_md.power_off = mpc83xx_power_off;
 319         ppc_md.halt = mpc83xx_halt;
 320
 321         ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory;
 322         ppc_md.setup_io_mappings  = mpc834x_sys_map_io;
 323
 324         ppc_md.time_init = mpc83xx_time_init;
 325         ppc_md.set_rtc_time = NULL;
 326         ppc_md.get_rtc_time = NULL;
 327         ppc_md.calibrate_decr = mpc83xx_calibrate_decr;
 328
 329         ppc_md.early_serial_map = mpc83xx_early_serial_map;
 330 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 331         ppc_md.progress = gen550_progress;
 332 #endif  /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
 333
 334         if (ppc_md.progress)
 335                 ppc_md.progress("mpc834x_sys_init(): exit", 0);
 336
 337         return;
 338 }