eventfd/kaio integration fix
[linux-2.6.22.y-op.git] / drivers / spi / atmel_spi.c
blob8b2601de36306e085d9a55481b0b777248db4946
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
22 #include <asm/io.h>
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/cpu.h>
27 #include "atmel_spi.h"
30 * The core SPI transfer engine just talks to a register bank to set up
31 * DMA transfers; transfer queue progress is driven by IRQs. The clock
32 * framework provides the base clock, subdivided for each spi_device.
34 * Newer controllers, marked with "new_1" flag, have:
35 * - CR.LASTXFER
36 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
37 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
38 * - SPI_CSRx.CSAAT
39 * - SPI_CSRx.SBCR allows faster clocking
41 struct atmel_spi {
42 spinlock_t lock;
44 void __iomem *regs;
45 int irq;
46 struct clk *clk;
47 struct platform_device *pdev;
48 unsigned new_1:1;
50 u8 stopping;
51 struct list_head queue;
52 struct spi_transfer *current_transfer;
53 unsigned long remaining_bytes;
55 void *buffer;
56 dma_addr_t buffer_dma;
59 #define BUFFER_SIZE PAGE_SIZE
60 #define INVALID_DMA_ADDRESS 0xffffffff
63 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
64 * they assume that spi slave device state will not change on deselect, so
65 * that automagic deselection is OK. Not so! Workaround uses nCSx pins
66 * as GPIOs; or newer controllers have CSAAT and friends.
68 * Since the CSAAT functionality is a bit weird on newer controllers
69 * as well, we use GPIO to control nCSx pins on all controllers.
72 static inline void cs_activate(struct spi_device *spi)
74 unsigned gpio = (unsigned) spi->controller_data;
75 unsigned active = spi->mode & SPI_CS_HIGH;
77 dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : "");
78 gpio_set_value(gpio, active);
81 static inline void cs_deactivate(struct spi_device *spi)
83 unsigned gpio = (unsigned) spi->controller_data;
84 unsigned active = spi->mode & SPI_CS_HIGH;
86 dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
87 gpio_set_value(gpio, !active);
91 * Submit next transfer for DMA.
92 * lock is held, spi irq is blocked
94 static void atmel_spi_next_xfer(struct spi_master *master,
95 struct spi_message *msg)
97 struct atmel_spi *as = spi_master_get_devdata(master);
98 struct spi_transfer *xfer;
99 u32 len;
100 dma_addr_t tx_dma, rx_dma;
102 xfer = as->current_transfer;
103 if (!xfer || as->remaining_bytes == 0) {
104 if (xfer)
105 xfer = list_entry(xfer->transfer_list.next,
106 struct spi_transfer, transfer_list);
107 else
108 xfer = list_entry(msg->transfers.next,
109 struct spi_transfer, transfer_list);
110 as->remaining_bytes = xfer->len;
111 as->current_transfer = xfer;
114 len = as->remaining_bytes;
116 tx_dma = xfer->tx_dma + xfer->len - len;
117 rx_dma = xfer->rx_dma + xfer->len - len;
119 /* use scratch buffer only when rx or tx data is unspecified */
120 if (!xfer->rx_buf) {
121 rx_dma = as->buffer_dma;
122 if (len > BUFFER_SIZE)
123 len = BUFFER_SIZE;
125 if (!xfer->tx_buf) {
126 tx_dma = as->buffer_dma;
127 if (len > BUFFER_SIZE)
128 len = BUFFER_SIZE;
129 memset(as->buffer, 0, len);
130 dma_sync_single_for_device(&as->pdev->dev,
131 as->buffer_dma, len, DMA_TO_DEVICE);
134 spi_writel(as, RPR, rx_dma);
135 spi_writel(as, TPR, tx_dma);
137 as->remaining_bytes -= len;
138 if (msg->spi->bits_per_word > 8)
139 len >>= 1;
141 /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
142 * mechanism might help avoid the IRQ latency between transfers
144 * We're also waiting for ENDRX before we start the next
145 * transfer because we need to handle some difficult timing
146 * issues otherwise. If we wait for ENDTX in one transfer and
147 * then starts waiting for ENDRX in the next, it's difficult
148 * to tell the difference between the ENDRX interrupt we're
149 * actually waiting for and the ENDRX interrupt of the
150 * previous transfer.
152 * It should be doable, though. Just not now...
154 spi_writel(as, TNCR, 0);
155 spi_writel(as, RNCR, 0);
156 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
158 dev_dbg(&msg->spi->dev,
159 " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
160 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
161 xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
163 spi_writel(as, TCR, len);
164 spi_writel(as, RCR, len);
165 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
168 static void atmel_spi_next_message(struct spi_master *master)
170 struct atmel_spi *as = spi_master_get_devdata(master);
171 struct spi_message *msg;
172 u32 mr;
174 BUG_ON(as->current_transfer);
176 msg = list_entry(as->queue.next, struct spi_message, queue);
178 /* Select the chip */
179 mr = spi_readl(as, MR);
180 mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
181 spi_writel(as, MR, mr);
182 cs_activate(msg->spi);
184 atmel_spi_next_xfer(master, msg);
187 static void
188 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
190 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
191 if (xfer->tx_buf)
192 xfer->tx_dma = dma_map_single(&as->pdev->dev,
193 (void *) xfer->tx_buf, xfer->len,
194 DMA_TO_DEVICE);
195 if (xfer->rx_buf)
196 xfer->rx_dma = dma_map_single(&as->pdev->dev,
197 xfer->rx_buf, xfer->len,
198 DMA_FROM_DEVICE);
201 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
202 struct spi_transfer *xfer)
204 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
205 dma_unmap_single(master->cdev.dev, xfer->tx_dma,
206 xfer->len, DMA_TO_DEVICE);
207 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
208 dma_unmap_single(master->cdev.dev, xfer->rx_dma,
209 xfer->len, DMA_FROM_DEVICE);
212 static void
213 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
214 struct spi_message *msg, int status)
216 cs_deactivate(msg->spi);
217 list_del(&msg->queue);
218 msg->status = status;
220 dev_dbg(master->cdev.dev,
221 "xfer complete: %u bytes transferred\n",
222 msg->actual_length);
224 spin_unlock(&as->lock);
225 msg->complete(msg->context);
226 spin_lock(&as->lock);
228 as->current_transfer = NULL;
230 /* continue if needed */
231 if (list_empty(&as->queue) || as->stopping)
232 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
233 else
234 atmel_spi_next_message(master);
237 static irqreturn_t
238 atmel_spi_interrupt(int irq, void *dev_id)
240 struct spi_master *master = dev_id;
241 struct atmel_spi *as = spi_master_get_devdata(master);
242 struct spi_message *msg;
243 struct spi_transfer *xfer;
244 u32 status, pending, imr;
245 int ret = IRQ_NONE;
247 spin_lock(&as->lock);
249 xfer = as->current_transfer;
250 msg = list_entry(as->queue.next, struct spi_message, queue);
252 imr = spi_readl(as, IMR);
253 status = spi_readl(as, SR);
254 pending = status & imr;
256 if (pending & SPI_BIT(OVRES)) {
257 int timeout;
259 ret = IRQ_HANDLED;
261 spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
262 | SPI_BIT(OVRES)));
265 * When we get an overrun, we disregard the current
266 * transfer. Data will not be copied back from any
267 * bounce buffer and msg->actual_len will not be
268 * updated with the last xfer.
270 * We will also not process any remaning transfers in
271 * the message.
273 * First, stop the transfer and unmap the DMA buffers.
275 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
276 if (!msg->is_dma_mapped)
277 atmel_spi_dma_unmap_xfer(master, xfer);
279 /* REVISIT: udelay in irq is unfriendly */
280 if (xfer->delay_usecs)
281 udelay(xfer->delay_usecs);
283 dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n",
284 spi_readl(as, TCR), spi_readl(as, RCR));
287 * Clean up DMA registers and make sure the data
288 * registers are empty.
290 spi_writel(as, RNCR, 0);
291 spi_writel(as, TNCR, 0);
292 spi_writel(as, RCR, 0);
293 spi_writel(as, TCR, 0);
294 for (timeout = 1000; timeout; timeout--)
295 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
296 break;
297 if (!timeout)
298 dev_warn(master->cdev.dev,
299 "timeout waiting for TXEMPTY");
300 while (spi_readl(as, SR) & SPI_BIT(RDRF))
301 spi_readl(as, RDR);
303 /* Clear any overrun happening while cleaning up */
304 spi_readl(as, SR);
306 atmel_spi_msg_done(master, as, msg, -EIO);
307 } else if (pending & SPI_BIT(ENDRX)) {
308 ret = IRQ_HANDLED;
310 spi_writel(as, IDR, pending);
312 if (as->remaining_bytes == 0) {
313 msg->actual_length += xfer->len;
315 if (!msg->is_dma_mapped)
316 atmel_spi_dma_unmap_xfer(master, xfer);
318 /* REVISIT: udelay in irq is unfriendly */
319 if (xfer->delay_usecs)
320 udelay(xfer->delay_usecs);
322 if (msg->transfers.prev == &xfer->transfer_list) {
323 /* report completed message */
324 atmel_spi_msg_done(master, as, msg, 0);
325 } else {
326 if (xfer->cs_change) {
327 cs_deactivate(msg->spi);
328 udelay(1);
329 cs_activate(msg->spi);
333 * Not done yet. Submit the next transfer.
335 * FIXME handle protocol options for xfer
337 atmel_spi_next_xfer(master, msg);
339 } else {
341 * Keep going, we still have data to send in
342 * the current transfer.
344 atmel_spi_next_xfer(master, msg);
348 spin_unlock(&as->lock);
350 return ret;
353 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
355 static int atmel_spi_setup(struct spi_device *spi)
357 struct atmel_spi *as;
358 u32 scbr, csr;
359 unsigned int bits = spi->bits_per_word;
360 unsigned long bus_hz, sck_hz;
361 unsigned int npcs_pin;
362 int ret;
364 as = spi_master_get_devdata(spi->master);
366 if (as->stopping)
367 return -ESHUTDOWN;
369 if (spi->chip_select > spi->master->num_chipselect) {
370 dev_dbg(&spi->dev,
371 "setup: invalid chipselect %u (%u defined)\n",
372 spi->chip_select, spi->master->num_chipselect);
373 return -EINVAL;
376 if (bits == 0)
377 bits = 8;
378 if (bits < 8 || bits > 16) {
379 dev_dbg(&spi->dev,
380 "setup: invalid bits_per_word %u (8 to 16)\n",
381 bits);
382 return -EINVAL;
385 if (spi->mode & ~MODEBITS) {
386 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
387 spi->mode & ~MODEBITS);
388 return -EINVAL;
391 /* speed zero convention is used by some upper layers */
392 bus_hz = clk_get_rate(as->clk);
393 if (spi->max_speed_hz) {
394 /* assume div32/fdiv/mbz == 0 */
395 if (!as->new_1)
396 bus_hz /= 2;
397 scbr = ((bus_hz + spi->max_speed_hz - 1)
398 / spi->max_speed_hz);
399 if (scbr >= (1 << SPI_SCBR_SIZE)) {
400 dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
401 spi->max_speed_hz, scbr);
402 return -EINVAL;
404 } else
405 scbr = 0xff;
406 sck_hz = bus_hz / scbr;
408 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
409 if (spi->mode & SPI_CPOL)
410 csr |= SPI_BIT(CPOL);
411 if (!(spi->mode & SPI_CPHA))
412 csr |= SPI_BIT(NCPHA);
414 /* TODO: DLYBS and DLYBCT */
415 csr |= SPI_BF(DLYBS, 10);
416 csr |= SPI_BF(DLYBCT, 10);
418 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
419 npcs_pin = (unsigned int)spi->controller_data;
420 if (!spi->controller_state) {
421 ret = gpio_request(npcs_pin, "spi_npcs");
422 if (ret)
423 return ret;
424 spi->controller_state = (void *)npcs_pin;
425 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
428 dev_dbg(&spi->dev,
429 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
430 sck_hz, bits, spi->mode, spi->chip_select, csr);
432 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
434 return 0;
437 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
439 struct atmel_spi *as;
440 struct spi_transfer *xfer;
441 unsigned long flags;
442 struct device *controller = spi->master->cdev.dev;
444 as = spi_master_get_devdata(spi->master);
446 dev_dbg(controller, "new message %p submitted for %s\n",
447 msg, spi->dev.bus_id);
449 if (unlikely(list_empty(&msg->transfers)
450 || !spi->max_speed_hz))
451 return -EINVAL;
453 if (as->stopping)
454 return -ESHUTDOWN;
456 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
457 if (!(xfer->tx_buf || xfer->rx_buf)) {
458 dev_dbg(&spi->dev, "missing rx or tx buf\n");
459 return -EINVAL;
462 /* FIXME implement these protocol options!! */
463 if (xfer->bits_per_word || xfer->speed_hz) {
464 dev_dbg(&spi->dev, "no protocol options yet\n");
465 return -ENOPROTOOPT;
469 /* scrub dcache "early" */
470 if (!msg->is_dma_mapped) {
471 list_for_each_entry(xfer, &msg->transfers, transfer_list)
472 atmel_spi_dma_map_xfer(as, xfer);
475 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
476 dev_dbg(controller,
477 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
478 xfer, xfer->len,
479 xfer->tx_buf, xfer->tx_dma,
480 xfer->rx_buf, xfer->rx_dma);
483 msg->status = -EINPROGRESS;
484 msg->actual_length = 0;
486 spin_lock_irqsave(&as->lock, flags);
487 list_add_tail(&msg->queue, &as->queue);
488 if (!as->current_transfer)
489 atmel_spi_next_message(spi->master);
490 spin_unlock_irqrestore(&as->lock, flags);
492 return 0;
495 static void atmel_spi_cleanup(struct spi_device *spi)
497 if (spi->controller_state)
498 gpio_free((unsigned int)spi->controller_data);
501 /*-------------------------------------------------------------------------*/
503 static int __init atmel_spi_probe(struct platform_device *pdev)
505 struct resource *regs;
506 int irq;
507 struct clk *clk;
508 int ret;
509 struct spi_master *master;
510 struct atmel_spi *as;
512 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
513 if (!regs)
514 return -ENXIO;
516 irq = platform_get_irq(pdev, 0);
517 if (irq < 0)
518 return irq;
520 clk = clk_get(&pdev->dev, "spi_clk");
521 if (IS_ERR(clk))
522 return PTR_ERR(clk);
524 /* setup spi core then atmel-specific driver state */
525 ret = -ENOMEM;
526 master = spi_alloc_master(&pdev->dev, sizeof *as);
527 if (!master)
528 goto out_free;
530 master->bus_num = pdev->id;
531 master->num_chipselect = 4;
532 master->setup = atmel_spi_setup;
533 master->transfer = atmel_spi_transfer;
534 master->cleanup = atmel_spi_cleanup;
535 platform_set_drvdata(pdev, master);
537 as = spi_master_get_devdata(master);
539 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
540 &as->buffer_dma, GFP_KERNEL);
541 if (!as->buffer)
542 goto out_free;
544 spin_lock_init(&as->lock);
545 INIT_LIST_HEAD(&as->queue);
546 as->pdev = pdev;
547 as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
548 if (!as->regs)
549 goto out_free_buffer;
550 as->irq = irq;
551 as->clk = clk;
552 if (!cpu_is_at91rm9200())
553 as->new_1 = 1;
555 ret = request_irq(irq, atmel_spi_interrupt, 0,
556 pdev->dev.bus_id, master);
557 if (ret)
558 goto out_unmap_regs;
560 /* Initialize the hardware */
561 clk_enable(clk);
562 spi_writel(as, CR, SPI_BIT(SWRST));
563 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
564 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
565 spi_writel(as, CR, SPI_BIT(SPIEN));
567 /* go! */
568 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
569 (unsigned long)regs->start, irq);
571 ret = spi_register_master(master);
572 if (ret)
573 goto out_reset_hw;
575 return 0;
577 out_reset_hw:
578 spi_writel(as, CR, SPI_BIT(SWRST));
579 clk_disable(clk);
580 free_irq(irq, master);
581 out_unmap_regs:
582 iounmap(as->regs);
583 out_free_buffer:
584 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
585 as->buffer_dma);
586 out_free:
587 clk_put(clk);
588 spi_master_put(master);
589 return ret;
592 static int __exit atmel_spi_remove(struct platform_device *pdev)
594 struct spi_master *master = platform_get_drvdata(pdev);
595 struct atmel_spi *as = spi_master_get_devdata(master);
596 struct spi_message *msg;
598 /* reset the hardware and block queue progress */
599 spin_lock_irq(&as->lock);
600 as->stopping = 1;
601 spi_writel(as, CR, SPI_BIT(SWRST));
602 spi_readl(as, SR);
603 spin_unlock_irq(&as->lock);
605 /* Terminate remaining queued transfers */
606 list_for_each_entry(msg, &as->queue, queue) {
607 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
608 * but we shouldn't depend on that...
610 msg->status = -ESHUTDOWN;
611 msg->complete(msg->context);
614 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
615 as->buffer_dma);
617 clk_disable(as->clk);
618 clk_put(as->clk);
619 free_irq(as->irq, master);
620 iounmap(as->regs);
622 spi_unregister_master(master);
624 return 0;
627 #ifdef CONFIG_PM
629 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
631 struct spi_master *master = platform_get_drvdata(pdev);
632 struct atmel_spi *as = spi_master_get_devdata(master);
634 clk_disable(as->clk);
635 return 0;
638 static int atmel_spi_resume(struct platform_device *pdev)
640 struct spi_master *master = platform_get_drvdata(pdev);
641 struct atmel_spi *as = spi_master_get_devdata(master);
643 clk_enable(as->clk);
644 return 0;
647 #else
648 #define atmel_spi_suspend NULL
649 #define atmel_spi_resume NULL
650 #endif
653 static struct platform_driver atmel_spi_driver = {
654 .driver = {
655 .name = "atmel_spi",
656 .owner = THIS_MODULE,
658 .suspend = atmel_spi_suspend,
659 .resume = atmel_spi_resume,
660 .remove = __exit_p(atmel_spi_remove),
663 static int __init atmel_spi_init(void)
665 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
667 module_init(atmel_spi_init);
669 static void __exit atmel_spi_exit(void)
671 platform_driver_unregister(&atmel_spi_driver);
673 module_exit(atmel_spi_exit);
675 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
676 MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
677 MODULE_LICENSE("GPL");