2 w83627hf.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2003 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>,
6 and Mark Studebaker <mdsxyz123@yahoo.com>
7 Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
8 Copyright (c) 2007 Jean Delvare <khali@linux-fr.org>
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 Supports following chips:
28 Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
29 w83627hf 9 3 2 3 0x20 0x5ca3 no yes(LPC)
30 w83627thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
31 w83637hf 7 3 3 3 0x80 0x5ca3 no yes(LPC)
32 w83687thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
33 w83697hf 8 2 2 2 0x60 0x5ca3 no yes(LPC)
35 For other winbond chips, and for i2c support in the above chips,
38 Note: automatic ("cruise") fan control for 697, 637 & 627thf not
42 #include <linux/module.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/jiffies.h>
46 #include <linux/platform_device.h>
47 #include <linux/hwmon.h>
48 #include <linux/hwmon-vid.h>
49 #include <linux/err.h>
50 #include <linux/mutex.h>
51 #include <linux/ioport.h>
55 static struct platform_device
*pdev
;
57 #define DRVNAME "w83627hf"
58 enum chips
{ w83627hf
, w83627thf
, w83697hf
, w83637hf
, w83687thf
};
60 static u16 force_addr
;
61 module_param(force_addr
, ushort
, 0);
62 MODULE_PARM_DESC(force_addr
,
63 "Initialize the base address of the sensors");
64 static u8 force_i2c
= 0x1f;
65 module_param(force_i2c
, byte
, 0);
66 MODULE_PARM_DESC(force_i2c
,
67 "Initialize the i2c address of the sensors");
70 module_param(reset
, bool, 0);
71 MODULE_PARM_DESC(reset
, "Set to one to reset chip on load");
74 module_param(init
, bool, 0);
75 MODULE_PARM_DESC(init
, "Set to zero to bypass chip initialization");
77 /* modified from kernel/include/traps.c */
78 static int REG
; /* The register to read/write */
79 #define DEV 0x07 /* Register: Logical device select */
80 static int VAL
; /* The value to read/write */
82 /* logical device numbers for superio_select (below) */
83 #define W83627HF_LD_FDC 0x00
84 #define W83627HF_LD_PRT 0x01
85 #define W83627HF_LD_UART1 0x02
86 #define W83627HF_LD_UART2 0x03
87 #define W83627HF_LD_KBC 0x05
88 #define W83627HF_LD_CIR 0x06 /* w83627hf only */
89 #define W83627HF_LD_GAME 0x07
90 #define W83627HF_LD_MIDI 0x07
91 #define W83627HF_LD_GPIO1 0x07
92 #define W83627HF_LD_GPIO5 0x07 /* w83627thf only */
93 #define W83627HF_LD_GPIO2 0x08
94 #define W83627HF_LD_GPIO3 0x09
95 #define W83627HF_LD_GPIO4 0x09 /* w83627thf only */
96 #define W83627HF_LD_ACPI 0x0a
97 #define W83627HF_LD_HWM 0x0b
99 #define DEVID 0x20 /* Register: Device ID */
101 #define W83627THF_GPIO5_EN 0x30 /* w83627thf only */
102 #define W83627THF_GPIO5_IOSR 0xf3 /* w83627thf only */
103 #define W83627THF_GPIO5_DR 0xf4 /* w83627thf only */
105 #define W83687THF_VID_EN 0x29 /* w83687thf only */
106 #define W83687THF_VID_CFG 0xF0 /* w83687thf only */
107 #define W83687THF_VID_DATA 0xF1 /* w83687thf only */
110 superio_outb(int reg
, int val
)
124 superio_select(int ld
)
143 #define W627_DEVID 0x52
144 #define W627THF_DEVID 0x82
145 #define W697_DEVID 0x60
146 #define W637_DEVID 0x70
147 #define W687THF_DEVID 0x85
148 #define WINB_ACT_REG 0x30
149 #define WINB_BASE_REG 0x60
150 /* Constants specified below */
152 /* Alignment of the base address */
153 #define WINB_ALIGNMENT ~7
155 /* Offset & size of I/O region we are interested in */
156 #define WINB_REGION_OFFSET 5
157 #define WINB_REGION_SIZE 2
159 /* Where are the sensors address/data registers relative to the region offset */
160 #define W83781D_ADDR_REG_OFFSET 0
161 #define W83781D_DATA_REG_OFFSET 1
163 /* The W83781D registers */
164 /* The W83782D registers for nr=7,8 are in bank 5 */
165 #define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
166 (0x554 + (((nr) - 7) * 2)))
167 #define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
168 (0x555 + (((nr) - 7) * 2)))
169 #define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
172 #define W83781D_REG_FAN_MIN(nr) (0x3a + (nr))
173 #define W83781D_REG_FAN(nr) (0x27 + (nr))
175 #define W83781D_REG_TEMP2_CONFIG 0x152
176 #define W83781D_REG_TEMP3_CONFIG 0x252
177 #define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
178 ((nr == 2) ? (0x0150) : \
180 #define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
181 ((nr == 2) ? (0x153) : \
183 #define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
184 ((nr == 2) ? (0x155) : \
187 #define W83781D_REG_BANK 0x4E
189 #define W83781D_REG_CONFIG 0x40
190 #define W83781D_REG_ALARM1 0x459
191 #define W83781D_REG_ALARM2 0x45A
192 #define W83781D_REG_ALARM3 0x45B
194 #define W83781D_REG_BEEP_CONFIG 0x4D
195 #define W83781D_REG_BEEP_INTS1 0x56
196 #define W83781D_REG_BEEP_INTS2 0x57
197 #define W83781D_REG_BEEP_INTS3 0x453
199 #define W83781D_REG_VID_FANDIV 0x47
201 #define W83781D_REG_CHIPID 0x49
202 #define W83781D_REG_WCHIPID 0x58
203 #define W83781D_REG_CHIPMAN 0x4F
204 #define W83781D_REG_PIN 0x4B
206 #define W83781D_REG_VBAT 0x5D
208 #define W83627HF_REG_PWM1 0x5A
209 #define W83627HF_REG_PWM2 0x5B
211 #define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */
212 #define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */
213 #define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */
215 #define W83627THF_REG_VRM_OVT_CFG 0x18 /* 637HF/687THF too */
217 static const u8 regpwm_627hf
[] = { W83627HF_REG_PWM1
, W83627HF_REG_PWM2
};
218 static const u8 regpwm
[] = { W83627THF_REG_PWM1
, W83627THF_REG_PWM2
,
219 W83627THF_REG_PWM3
};
220 #define W836X7HF_REG_PWM(type, nr) (((type) == w83627hf) ? \
221 regpwm_627hf[(nr) - 1] : regpwm[(nr) - 1])
223 #define W83781D_REG_I2C_ADDR 0x48
224 #define W83781D_REG_I2C_SUBADDR 0x4A
226 /* Sensor selection */
227 #define W83781D_REG_SCFG1 0x5D
228 static const u8 BIT_SCFG1
[] = { 0x02, 0x04, 0x08 };
229 #define W83781D_REG_SCFG2 0x59
230 static const u8 BIT_SCFG2
[] = { 0x10, 0x20, 0x40 };
231 #define W83781D_DEFAULT_BETA 3435
233 /* Conversions. Limit checking is only done on the TO_REG
234 variants. Note that you should be a bit careful with which arguments
235 these macros are called: arguments may be evaluated more than once.
236 Fixing this is just not worth it. */
237 #define IN_TO_REG(val) (SENSORS_LIMIT((((val) + 8)/16),0,255))
238 #define IN_FROM_REG(val) ((val) * 16)
240 static inline u8
FAN_TO_REG(long rpm
, int div
)
244 rpm
= SENSORS_LIMIT(rpm
, 1, 1000000);
245 return SENSORS_LIMIT((1350000 + rpm
* div
/ 2) / (rpm
* div
), 1,
249 #define TEMP_MIN (-128000)
250 #define TEMP_MAX ( 127000)
252 /* TEMP: 0.001C/bit (-128C to +127C)
253 REG: 1C/bit, two's complement */
254 static u8
TEMP_TO_REG(int temp
)
256 int ntemp
= SENSORS_LIMIT(temp
, TEMP_MIN
, TEMP_MAX
);
257 ntemp
+= (ntemp
<0 ? -500 : 500);
258 return (u8
)(ntemp
/ 1000);
261 static int TEMP_FROM_REG(u8 reg
)
263 return (s8
)reg
* 1000;
266 #define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
268 #define PWM_TO_REG(val) (SENSORS_LIMIT((val),0,255))
270 #define BEEP_MASK_FROM_REG(val) (val)
271 #define BEEP_MASK_TO_REG(val) ((val) & 0xffffff)
272 #define BEEP_ENABLE_TO_REG(val) ((val)?1:0)
273 #define BEEP_ENABLE_FROM_REG(val) ((val)?1:0)
275 #define DIV_FROM_REG(val) (1 << (val))
277 static inline u8
DIV_TO_REG(long val
)
280 val
= SENSORS_LIMIT(val
, 1, 128) >> 1;
281 for (i
= 0; i
< 7; i
++) {
289 /* For each registered chip, we need to keep some data in memory.
290 The structure is dynamically allocated. */
291 struct w83627hf_data
{
294 struct class_device
*class_dev
;
298 struct mutex update_lock
;
299 char valid
; /* !=0 if following fields are valid */
300 unsigned long last_updated
; /* In jiffies */
302 u8 in
[9]; /* Register value */
303 u8 in_max
[9]; /* Register value */
304 u8 in_min
[9]; /* Register value */
305 u8 fan
[3]; /* Register value */
306 u8 fan_min
[3]; /* Register value */
308 u8 temp_max
; /* Register value */
309 u8 temp_max_hyst
; /* Register value */
310 u16 temp_add
[2]; /* Register value */
311 u16 temp_max_add
[2]; /* Register value */
312 u16 temp_max_hyst_add
[2]; /* Register value */
313 u8 fan_div
[3]; /* Register encoding, shifted right */
314 u8 vid
; /* Register encoding, combined */
315 u32 alarms
; /* Register encoding, combined */
316 u32 beep_mask
; /* Register encoding, combined */
317 u8 beep_enable
; /* Boolean */
318 u8 pwm
[3]; /* Register value */
319 u16 sens
[3]; /* 782D/783S only.
320 1 = pentium diode; 2 = 3904 diode;
321 3000-5000 = thermistor beta.
323 Other Betas unimplemented */
325 u8 vrm_ovt
; /* Register value, 627THF/637HF/687THF only */
328 struct w83627hf_sio_data
{
333 static int w83627hf_probe(struct platform_device
*pdev
);
334 static int w83627hf_remove(struct platform_device
*pdev
);
336 static int w83627hf_read_value(struct w83627hf_data
*data
, u16 reg
);
337 static int w83627hf_write_value(struct w83627hf_data
*data
, u16 reg
, u16 value
);
338 static void w83627hf_update_fan_div(struct w83627hf_data
*data
);
339 static struct w83627hf_data
*w83627hf_update_device(struct device
*dev
);
340 static void w83627hf_init_device(struct platform_device
*pdev
);
342 static struct platform_driver w83627hf_driver
= {
344 .owner
= THIS_MODULE
,
347 .probe
= w83627hf_probe
,
348 .remove
= __devexit_p(w83627hf_remove
),
351 /* following are the sysfs callback functions */
352 #define show_in_reg(reg) \
353 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
355 struct w83627hf_data *data = w83627hf_update_device(dev); \
356 return sprintf(buf,"%ld\n", (long)IN_FROM_REG(data->reg[nr])); \
362 #define store_in_reg(REG, reg) \
364 store_in_##reg (struct device *dev, const char *buf, size_t count, int nr) \
366 struct w83627hf_data *data = dev_get_drvdata(dev); \
369 val = simple_strtoul(buf, NULL, 10); \
371 mutex_lock(&data->update_lock); \
372 data->in_##reg[nr] = IN_TO_REG(val); \
373 w83627hf_write_value(data, W83781D_REG_IN_##REG(nr), \
374 data->in_##reg[nr]); \
376 mutex_unlock(&data->update_lock); \
379 store_in_reg(MIN
, min
)
380 store_in_reg(MAX
, max
)
382 #define sysfs_in_offset(offset) \
384 show_regs_in_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
386 return show_in(dev, buf, offset); \
388 static DEVICE_ATTR(in##offset##_input, S_IRUGO, show_regs_in_##offset, NULL);
390 #define sysfs_in_reg_offset(reg, offset) \
391 static ssize_t show_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
393 return show_in_##reg (dev, buf, offset); \
396 store_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, \
397 const char *buf, size_t count) \
399 return store_in_##reg (dev, buf, count, offset); \
401 static DEVICE_ATTR(in##offset##_##reg, S_IRUGO| S_IWUSR, \
402 show_regs_in_##reg##offset, store_regs_in_##reg##offset);
404 #define sysfs_in_offsets(offset) \
405 sysfs_in_offset(offset) \
406 sysfs_in_reg_offset(min, offset) \
407 sysfs_in_reg_offset(max, offset)
418 /* use a different set of functions for in0 */
419 static ssize_t
show_in_0(struct w83627hf_data
*data
, char *buf
, u8 reg
)
423 if ((data
->vrm_ovt
& 0x01) &&
424 (w83627thf
== data
->type
|| w83637hf
== data
->type
425 || w83687thf
== data
->type
))
427 /* use VRM9 calculation */
428 in0
= (long)((reg
* 488 + 70000 + 50) / 100);
430 /* use VRM8 (standard) calculation */
431 in0
= (long)IN_FROM_REG(reg
);
433 return sprintf(buf
,"%ld\n", in0
);
436 static ssize_t
show_regs_in_0(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
438 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
439 return show_in_0(data
, buf
, data
->in
[0]);
442 static ssize_t
show_regs_in_min0(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
444 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
445 return show_in_0(data
, buf
, data
->in_min
[0]);
448 static ssize_t
show_regs_in_max0(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
450 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
451 return show_in_0(data
, buf
, data
->in_max
[0]);
454 static ssize_t
store_regs_in_min0(struct device
*dev
, struct device_attribute
*attr
,
455 const char *buf
, size_t count
)
457 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
460 val
= simple_strtoul(buf
, NULL
, 10);
462 mutex_lock(&data
->update_lock
);
464 if ((data
->vrm_ovt
& 0x01) &&
465 (w83627thf
== data
->type
|| w83637hf
== data
->type
466 || w83687thf
== data
->type
))
468 /* use VRM9 calculation */
470 SENSORS_LIMIT(((val
* 100) - 70000 + 244) / 488, 0,
473 /* use VRM8 (standard) calculation */
474 data
->in_min
[0] = IN_TO_REG(val
);
476 w83627hf_write_value(data
, W83781D_REG_IN_MIN(0), data
->in_min
[0]);
477 mutex_unlock(&data
->update_lock
);
481 static ssize_t
store_regs_in_max0(struct device
*dev
, struct device_attribute
*attr
,
482 const char *buf
, size_t count
)
484 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
487 val
= simple_strtoul(buf
, NULL
, 10);
489 mutex_lock(&data
->update_lock
);
491 if ((data
->vrm_ovt
& 0x01) &&
492 (w83627thf
== data
->type
|| w83637hf
== data
->type
493 || w83687thf
== data
->type
))
495 /* use VRM9 calculation */
497 SENSORS_LIMIT(((val
* 100) - 70000 + 244) / 488, 0,
500 /* use VRM8 (standard) calculation */
501 data
->in_max
[0] = IN_TO_REG(val
);
503 w83627hf_write_value(data
, W83781D_REG_IN_MAX(0), data
->in_max
[0]);
504 mutex_unlock(&data
->update_lock
);
508 static DEVICE_ATTR(in0_input
, S_IRUGO
, show_regs_in_0
, NULL
);
509 static DEVICE_ATTR(in0_min
, S_IRUGO
| S_IWUSR
,
510 show_regs_in_min0
, store_regs_in_min0
);
511 static DEVICE_ATTR(in0_max
, S_IRUGO
| S_IWUSR
,
512 show_regs_in_max0
, store_regs_in_max0
);
514 #define show_fan_reg(reg) \
515 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
517 struct w83627hf_data *data = w83627hf_update_device(dev); \
518 return sprintf(buf,"%ld\n", \
519 FAN_FROM_REG(data->reg[nr-1], \
520 (long)DIV_FROM_REG(data->fan_div[nr-1]))); \
523 show_fan_reg(fan_min
);
526 store_fan_min(struct device
*dev
, const char *buf
, size_t count
, int nr
)
528 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
531 val
= simple_strtoul(buf
, NULL
, 10);
533 mutex_lock(&data
->update_lock
);
534 data
->fan_min
[nr
- 1] =
535 FAN_TO_REG(val
, DIV_FROM_REG(data
->fan_div
[nr
- 1]));
536 w83627hf_write_value(data
, W83781D_REG_FAN_MIN(nr
),
537 data
->fan_min
[nr
- 1]);
539 mutex_unlock(&data
->update_lock
);
543 #define sysfs_fan_offset(offset) \
544 static ssize_t show_regs_fan_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
546 return show_fan(dev, buf, offset); \
548 static DEVICE_ATTR(fan##offset##_input, S_IRUGO, show_regs_fan_##offset, NULL);
550 #define sysfs_fan_min_offset(offset) \
551 static ssize_t show_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, char *buf) \
553 return show_fan_min(dev, buf, offset); \
556 store_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
558 return store_fan_min(dev, buf, count, offset); \
560 static DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
561 show_regs_fan_min##offset, store_regs_fan_min##offset);
564 sysfs_fan_min_offset(1);
566 sysfs_fan_min_offset(2);
568 sysfs_fan_min_offset(3);
570 #define show_temp_reg(reg) \
571 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
573 struct w83627hf_data *data = w83627hf_update_device(dev); \
574 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
575 return sprintf(buf,"%ld\n", \
576 (long)LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
577 } else { /* TEMP1 */ \
578 return sprintf(buf,"%ld\n", (long)TEMP_FROM_REG(data->reg)); \
582 show_temp_reg(temp_max
);
583 show_temp_reg(temp_max_hyst
);
585 #define store_temp_reg(REG, reg) \
587 store_temp_##reg (struct device *dev, const char *buf, size_t count, int nr) \
589 struct w83627hf_data *data = dev_get_drvdata(dev); \
592 val = simple_strtoul(buf, NULL, 10); \
594 mutex_lock(&data->update_lock); \
596 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
597 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
598 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
599 data->temp_##reg##_add[nr-2]); \
600 } else { /* TEMP1 */ \
601 data->temp_##reg = TEMP_TO_REG(val); \
602 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
606 mutex_unlock(&data->update_lock); \
609 store_temp_reg(OVER
, max
);
610 store_temp_reg(HYST
, max_hyst
);
612 #define sysfs_temp_offset(offset) \
614 show_regs_temp_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
616 return show_temp(dev, buf, offset); \
618 static DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_regs_temp_##offset, NULL);
620 #define sysfs_temp_reg_offset(reg, offset) \
621 static ssize_t show_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
623 return show_temp_##reg (dev, buf, offset); \
626 store_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, \
627 const char *buf, size_t count) \
629 return store_temp_##reg (dev, buf, count, offset); \
631 static DEVICE_ATTR(temp##offset##_##reg, S_IRUGO| S_IWUSR, \
632 show_regs_temp_##reg##offset, store_regs_temp_##reg##offset);
634 #define sysfs_temp_offsets(offset) \
635 sysfs_temp_offset(offset) \
636 sysfs_temp_reg_offset(max, offset) \
637 sysfs_temp_reg_offset(max_hyst, offset)
639 sysfs_temp_offsets(1);
640 sysfs_temp_offsets(2);
641 sysfs_temp_offsets(3);
644 show_vid_reg(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
646 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
647 return sprintf(buf
, "%ld\n", (long) vid_from_reg(data
->vid
, data
->vrm
));
649 static DEVICE_ATTR(cpu0_vid
, S_IRUGO
, show_vid_reg
, NULL
);
652 show_vrm_reg(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
654 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
655 return sprintf(buf
, "%ld\n", (long) data
->vrm
);
658 store_vrm_reg(struct device
*dev
, struct device_attribute
*attr
, const char *buf
, size_t count
)
660 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
663 val
= simple_strtoul(buf
, NULL
, 10);
668 static DEVICE_ATTR(vrm
, S_IRUGO
| S_IWUSR
, show_vrm_reg
, store_vrm_reg
);
671 show_alarms_reg(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
673 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
674 return sprintf(buf
, "%ld\n", (long) data
->alarms
);
676 static DEVICE_ATTR(alarms
, S_IRUGO
, show_alarms_reg
, NULL
);
678 #define show_beep_reg(REG, reg) \
679 static ssize_t show_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
681 struct w83627hf_data *data = w83627hf_update_device(dev); \
682 return sprintf(buf,"%ld\n", \
683 (long)BEEP_##REG##_FROM_REG(data->beep_##reg)); \
685 show_beep_reg(ENABLE
, enable
)
686 show_beep_reg(MASK
, mask
)
688 #define BEEP_ENABLE 0 /* Store beep_enable */
689 #define BEEP_MASK 1 /* Store beep_mask */
692 store_beep_reg(struct device
*dev
, const char *buf
, size_t count
,
695 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
698 val
= simple_strtoul(buf
, NULL
, 10);
700 mutex_lock(&data
->update_lock
);
702 if (update_mask
== BEEP_MASK
) { /* We are storing beep_mask */
703 data
->beep_mask
= BEEP_MASK_TO_REG(val
);
704 w83627hf_write_value(data
, W83781D_REG_BEEP_INTS1
,
705 data
->beep_mask
& 0xff);
706 w83627hf_write_value(data
, W83781D_REG_BEEP_INTS3
,
707 ((data
->beep_mask
) >> 16) & 0xff);
708 val2
= (data
->beep_mask
>> 8) & 0x7f;
709 } else { /* We are storing beep_enable */
711 w83627hf_read_value(data
, W83781D_REG_BEEP_INTS2
) & 0x7f;
712 data
->beep_enable
= BEEP_ENABLE_TO_REG(val
);
715 w83627hf_write_value(data
, W83781D_REG_BEEP_INTS2
,
716 val2
| data
->beep_enable
<< 7);
718 mutex_unlock(&data
->update_lock
);
722 #define sysfs_beep(REG, reg) \
723 static ssize_t show_regs_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
725 return show_beep_##reg(dev, attr, buf); \
728 store_regs_beep_##reg (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
730 return store_beep_reg(dev, buf, count, BEEP_##REG); \
732 static DEVICE_ATTR(beep_##reg, S_IRUGO | S_IWUSR, \
733 show_regs_beep_##reg, store_regs_beep_##reg);
735 sysfs_beep(ENABLE
, enable
);
736 sysfs_beep(MASK
, mask
);
739 show_fan_div_reg(struct device
*dev
, char *buf
, int nr
)
741 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
742 return sprintf(buf
, "%ld\n",
743 (long) DIV_FROM_REG(data
->fan_div
[nr
- 1]));
746 /* Note: we save and restore the fan minimum here, because its value is
747 determined in part by the fan divisor. This follows the principle of
748 least surprise; the user doesn't expect the fan minimum to change just
749 because the divisor changed. */
751 store_fan_div_reg(struct device
*dev
, const char *buf
, size_t count
, int nr
)
753 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
756 unsigned long val
= simple_strtoul(buf
, NULL
, 10);
758 mutex_lock(&data
->update_lock
);
761 min
= FAN_FROM_REG(data
->fan_min
[nr
],
762 DIV_FROM_REG(data
->fan_div
[nr
]));
764 data
->fan_div
[nr
] = DIV_TO_REG(val
);
766 reg
= (w83627hf_read_value(data
, nr
==2 ? W83781D_REG_PIN
: W83781D_REG_VID_FANDIV
)
767 & (nr
==0 ? 0xcf : 0x3f))
768 | ((data
->fan_div
[nr
] & 0x03) << (nr
==0 ? 4 : 6));
769 w83627hf_write_value(data
, nr
==2 ? W83781D_REG_PIN
: W83781D_REG_VID_FANDIV
, reg
);
771 reg
= (w83627hf_read_value(data
, W83781D_REG_VBAT
)
773 | ((data
->fan_div
[nr
] & 0x04) << (3 + nr
));
774 w83627hf_write_value(data
, W83781D_REG_VBAT
, reg
);
776 /* Restore fan_min */
777 data
->fan_min
[nr
] = FAN_TO_REG(min
, DIV_FROM_REG(data
->fan_div
[nr
]));
778 w83627hf_write_value(data
, W83781D_REG_FAN_MIN(nr
+1), data
->fan_min
[nr
]);
780 mutex_unlock(&data
->update_lock
);
784 #define sysfs_fan_div(offset) \
785 static ssize_t show_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
787 return show_fan_div_reg(dev, buf, offset); \
790 store_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, \
791 const char *buf, size_t count) \
793 return store_fan_div_reg(dev, buf, count, offset - 1); \
795 static DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \
796 show_regs_fan_div_##offset, store_regs_fan_div_##offset);
803 show_pwm_reg(struct device
*dev
, char *buf
, int nr
)
805 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
806 return sprintf(buf
, "%ld\n", (long) data
->pwm
[nr
- 1]);
810 store_pwm_reg(struct device
*dev
, const char *buf
, size_t count
, int nr
)
812 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
815 val
= simple_strtoul(buf
, NULL
, 10);
817 mutex_lock(&data
->update_lock
);
819 if (data
->type
== w83627thf
) {
820 /* bits 0-3 are reserved in 627THF */
821 data
->pwm
[nr
- 1] = PWM_TO_REG(val
) & 0xf0;
822 w83627hf_write_value(data
,
823 W836X7HF_REG_PWM(data
->type
, nr
),
825 (w83627hf_read_value(data
,
826 W836X7HF_REG_PWM(data
->type
, nr
)) & 0x0f));
828 data
->pwm
[nr
- 1] = PWM_TO_REG(val
);
829 w83627hf_write_value(data
,
830 W836X7HF_REG_PWM(data
->type
, nr
),
834 mutex_unlock(&data
->update_lock
);
838 #define sysfs_pwm(offset) \
839 static ssize_t show_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
841 return show_pwm_reg(dev, buf, offset); \
844 store_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
846 return store_pwm_reg(dev, buf, count, offset); \
848 static DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \
849 show_regs_pwm_##offset, store_regs_pwm_##offset);
856 show_sensor_reg(struct device
*dev
, char *buf
, int nr
)
858 struct w83627hf_data
*data
= w83627hf_update_device(dev
);
859 return sprintf(buf
, "%ld\n", (long) data
->sens
[nr
- 1]);
863 store_sensor_reg(struct device
*dev
, const char *buf
, size_t count
, int nr
)
865 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
868 val
= simple_strtoul(buf
, NULL
, 10);
870 mutex_lock(&data
->update_lock
);
873 case 1: /* PII/Celeron diode */
874 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG1
);
875 w83627hf_write_value(data
, W83781D_REG_SCFG1
,
876 tmp
| BIT_SCFG1
[nr
- 1]);
877 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG2
);
878 w83627hf_write_value(data
, W83781D_REG_SCFG2
,
879 tmp
| BIT_SCFG2
[nr
- 1]);
880 data
->sens
[nr
- 1] = val
;
883 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG1
);
884 w83627hf_write_value(data
, W83781D_REG_SCFG1
,
885 tmp
| BIT_SCFG1
[nr
- 1]);
886 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG2
);
887 w83627hf_write_value(data
, W83781D_REG_SCFG2
,
888 tmp
& ~BIT_SCFG2
[nr
- 1]);
889 data
->sens
[nr
- 1] = val
;
891 case W83781D_DEFAULT_BETA
: /* thermistor */
892 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG1
);
893 w83627hf_write_value(data
, W83781D_REG_SCFG1
,
894 tmp
& ~BIT_SCFG1
[nr
- 1]);
895 data
->sens
[nr
- 1] = val
;
899 "Invalid sensor type %ld; must be 1, 2, or %d\n",
900 (long) val
, W83781D_DEFAULT_BETA
);
904 mutex_unlock(&data
->update_lock
);
908 #define sysfs_sensor(offset) \
909 static ssize_t show_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
911 return show_sensor_reg(dev, buf, offset); \
914 store_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
916 return store_sensor_reg(dev, buf, count, offset); \
918 static DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
919 show_regs_sensor_##offset, store_regs_sensor_##offset);
925 static ssize_t
show_name(struct device
*dev
, struct device_attribute
928 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
930 return sprintf(buf
, "%s\n", data
->name
);
932 static DEVICE_ATTR(name
, S_IRUGO
, show_name
, NULL
);
934 static int __init
w83627hf_find(int sioaddr
, unsigned short *addr
,
935 struct w83627hf_sio_data
*sio_data
)
940 static const __initdata
char *names
[] = {
952 val
= superio_inb(DEVID
);
955 sio_data
->type
= w83627hf
;
958 sio_data
->type
= w83627thf
;
961 sio_data
->type
= w83697hf
;
964 sio_data
->type
= w83637hf
;
967 sio_data
->type
= w83687thf
;
969 case 0xff: /* No device at all */
972 pr_debug(DRVNAME
": Unsupported chip (DEVID=0x%02x)\n", val
);
976 superio_select(W83627HF_LD_HWM
);
977 force_addr
&= WINB_ALIGNMENT
;
979 printk(KERN_WARNING DRVNAME
": Forcing address 0x%x\n",
981 superio_outb(WINB_BASE_REG
, force_addr
>> 8);
982 superio_outb(WINB_BASE_REG
+ 1, force_addr
& 0xff);
984 val
= (superio_inb(WINB_BASE_REG
) << 8) |
985 superio_inb(WINB_BASE_REG
+ 1);
986 *addr
= val
& WINB_ALIGNMENT
;
988 printk(KERN_WARNING DRVNAME
": Base address not set, "
993 val
= superio_inb(WINB_ACT_REG
);
995 printk(KERN_WARNING DRVNAME
": Enabling HWM logical device\n");
996 superio_outb(WINB_ACT_REG
, val
| 0x01);
1000 pr_info(DRVNAME
": Found %s chip at %#x\n",
1001 names
[sio_data
->type
], *addr
);
1008 static struct attribute
*w83627hf_attributes
[] = {
1009 &dev_attr_in0_input
.attr
,
1010 &dev_attr_in0_min
.attr
,
1011 &dev_attr_in0_max
.attr
,
1012 &dev_attr_in2_input
.attr
,
1013 &dev_attr_in2_min
.attr
,
1014 &dev_attr_in2_max
.attr
,
1015 &dev_attr_in3_input
.attr
,
1016 &dev_attr_in3_min
.attr
,
1017 &dev_attr_in3_max
.attr
,
1018 &dev_attr_in4_input
.attr
,
1019 &dev_attr_in4_min
.attr
,
1020 &dev_attr_in4_max
.attr
,
1021 &dev_attr_in7_input
.attr
,
1022 &dev_attr_in7_min
.attr
,
1023 &dev_attr_in7_max
.attr
,
1024 &dev_attr_in8_input
.attr
,
1025 &dev_attr_in8_min
.attr
,
1026 &dev_attr_in8_max
.attr
,
1028 &dev_attr_fan1_input
.attr
,
1029 &dev_attr_fan1_min
.attr
,
1030 &dev_attr_fan1_div
.attr
,
1031 &dev_attr_fan2_input
.attr
,
1032 &dev_attr_fan2_min
.attr
,
1033 &dev_attr_fan2_div
.attr
,
1035 &dev_attr_temp1_input
.attr
,
1036 &dev_attr_temp1_max
.attr
,
1037 &dev_attr_temp1_max_hyst
.attr
,
1038 &dev_attr_temp1_type
.attr
,
1039 &dev_attr_temp2_input
.attr
,
1040 &dev_attr_temp2_max
.attr
,
1041 &dev_attr_temp2_max_hyst
.attr
,
1042 &dev_attr_temp2_type
.attr
,
1044 &dev_attr_alarms
.attr
,
1045 &dev_attr_beep_enable
.attr
,
1046 &dev_attr_beep_mask
.attr
,
1048 &dev_attr_pwm1
.attr
,
1049 &dev_attr_pwm2
.attr
,
1051 &dev_attr_name
.attr
,
1055 static const struct attribute_group w83627hf_group
= {
1056 .attrs
= w83627hf_attributes
,
1059 static struct attribute
*w83627hf_attributes_opt
[] = {
1060 &dev_attr_in1_input
.attr
,
1061 &dev_attr_in1_min
.attr
,
1062 &dev_attr_in1_max
.attr
,
1063 &dev_attr_in5_input
.attr
,
1064 &dev_attr_in5_min
.attr
,
1065 &dev_attr_in5_max
.attr
,
1066 &dev_attr_in6_input
.attr
,
1067 &dev_attr_in6_min
.attr
,
1068 &dev_attr_in6_max
.attr
,
1070 &dev_attr_fan3_input
.attr
,
1071 &dev_attr_fan3_min
.attr
,
1072 &dev_attr_fan3_div
.attr
,
1074 &dev_attr_temp3_input
.attr
,
1075 &dev_attr_temp3_max
.attr
,
1076 &dev_attr_temp3_max_hyst
.attr
,
1077 &dev_attr_temp3_type
.attr
,
1079 &dev_attr_pwm3
.attr
,
1084 static const struct attribute_group w83627hf_group_opt
= {
1085 .attrs
= w83627hf_attributes_opt
,
1088 static int __devinit
w83627hf_probe(struct platform_device
*pdev
)
1090 struct device
*dev
= &pdev
->dev
;
1091 struct w83627hf_sio_data
*sio_data
= dev
->platform_data
;
1092 struct w83627hf_data
*data
;
1093 struct resource
*res
;
1096 static const char *names
[] = {
1104 res
= platform_get_resource(pdev
, IORESOURCE_IO
, 0);
1105 if (!request_region(res
->start
, WINB_REGION_SIZE
, DRVNAME
)) {
1106 dev_err(dev
, "Failed to request region 0x%lx-0x%lx\n",
1107 (unsigned long)res
->start
,
1108 (unsigned long)(res
->start
+ WINB_REGION_SIZE
- 1));
1113 if (!(data
= kzalloc(sizeof(struct w83627hf_data
), GFP_KERNEL
))) {
1117 data
->addr
= res
->start
;
1118 data
->type
= sio_data
->type
;
1119 data
->name
= names
[sio_data
->type
];
1120 mutex_init(&data
->lock
);
1121 mutex_init(&data
->update_lock
);
1122 platform_set_drvdata(pdev
, data
);
1124 /* Initialize the chip */
1125 w83627hf_init_device(pdev
);
1127 /* A few vars need to be filled upon startup */
1128 data
->fan_min
[0] = w83627hf_read_value(data
, W83781D_REG_FAN_MIN(1));
1129 data
->fan_min
[1] = w83627hf_read_value(data
, W83781D_REG_FAN_MIN(2));
1130 data
->fan_min
[2] = w83627hf_read_value(data
, W83781D_REG_FAN_MIN(3));
1131 w83627hf_update_fan_div(data
);
1133 /* Register common device attributes */
1134 if ((err
= sysfs_create_group(&dev
->kobj
, &w83627hf_group
)))
1137 /* Register chip-specific device attributes */
1138 if (data
->type
== w83627hf
|| data
->type
== w83697hf
)
1139 if ((err
= device_create_file(dev
, &dev_attr_in5_input
))
1140 || (err
= device_create_file(dev
, &dev_attr_in5_min
))
1141 || (err
= device_create_file(dev
, &dev_attr_in5_max
))
1142 || (err
= device_create_file(dev
, &dev_attr_in6_input
))
1143 || (err
= device_create_file(dev
, &dev_attr_in6_min
))
1144 || (err
= device_create_file(dev
, &dev_attr_in6_max
)))
1147 if (data
->type
!= w83697hf
)
1148 if ((err
= device_create_file(dev
, &dev_attr_in1_input
))
1149 || (err
= device_create_file(dev
, &dev_attr_in1_min
))
1150 || (err
= device_create_file(dev
, &dev_attr_in1_max
))
1151 || (err
= device_create_file(dev
, &dev_attr_fan3_input
))
1152 || (err
= device_create_file(dev
, &dev_attr_fan3_min
))
1153 || (err
= device_create_file(dev
, &dev_attr_fan3_div
))
1154 || (err
= device_create_file(dev
, &dev_attr_temp3_input
))
1155 || (err
= device_create_file(dev
, &dev_attr_temp3_max
))
1156 || (err
= device_create_file(dev
, &dev_attr_temp3_max_hyst
))
1157 || (err
= device_create_file(dev
, &dev_attr_temp3_type
)))
1160 if (data
->type
!= w83697hf
&& data
->vid
!= 0xff) {
1161 /* Convert VID to voltage based on VRM */
1162 data
->vrm
= vid_which_vrm();
1164 if ((err
= device_create_file(dev
, &dev_attr_cpu0_vid
))
1165 || (err
= device_create_file(dev
, &dev_attr_vrm
)))
1169 if (data
->type
== w83627thf
|| data
->type
== w83637hf
1170 || data
->type
== w83687thf
)
1171 if ((err
= device_create_file(dev
, &dev_attr_pwm3
)))
1174 data
->class_dev
= hwmon_device_register(dev
);
1175 if (IS_ERR(data
->class_dev
)) {
1176 err
= PTR_ERR(data
->class_dev
);
1183 sysfs_remove_group(&dev
->kobj
, &w83627hf_group
);
1184 sysfs_remove_group(&dev
->kobj
, &w83627hf_group_opt
);
1188 release_region(res
->start
, WINB_REGION_SIZE
);
1193 static int __devexit
w83627hf_remove(struct platform_device
*pdev
)
1195 struct w83627hf_data
*data
= platform_get_drvdata(pdev
);
1196 struct resource
*res
;
1198 platform_set_drvdata(pdev
, NULL
);
1199 hwmon_device_unregister(data
->class_dev
);
1201 sysfs_remove_group(&pdev
->dev
.kobj
, &w83627hf_group
);
1202 sysfs_remove_group(&pdev
->dev
.kobj
, &w83627hf_group_opt
);
1205 res
= platform_get_resource(pdev
, IORESOURCE_IO
, 0);
1206 release_region(res
->start
, WINB_REGION_SIZE
);
1212 /* Registers 0x50-0x5f are banked */
1213 static inline void w83627hf_set_bank(struct w83627hf_data
*data
, u16 reg
)
1215 if ((reg
& 0x00f0) == 0x50) {
1216 outb_p(W83781D_REG_BANK
, data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1217 outb_p(reg
>> 8, data
->addr
+ W83781D_DATA_REG_OFFSET
);
1221 /* Not strictly necessary, but play it safe for now */
1222 static inline void w83627hf_reset_bank(struct w83627hf_data
*data
, u16 reg
)
1225 outb_p(W83781D_REG_BANK
, data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1226 outb_p(0, data
->addr
+ W83781D_DATA_REG_OFFSET
);
1230 static int w83627hf_read_value(struct w83627hf_data
*data
, u16 reg
)
1232 int res
, word_sized
;
1234 mutex_lock(&data
->lock
);
1235 word_sized
= (((reg
& 0xff00) == 0x100)
1236 || ((reg
& 0xff00) == 0x200))
1237 && (((reg
& 0x00ff) == 0x50)
1238 || ((reg
& 0x00ff) == 0x53)
1239 || ((reg
& 0x00ff) == 0x55));
1240 w83627hf_set_bank(data
, reg
);
1241 outb_p(reg
& 0xff, data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1242 res
= inb_p(data
->addr
+ W83781D_DATA_REG_OFFSET
);
1244 outb_p((reg
& 0xff) + 1,
1245 data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1247 (res
<< 8) + inb_p(data
->addr
+
1248 W83781D_DATA_REG_OFFSET
);
1250 w83627hf_reset_bank(data
, reg
);
1251 mutex_unlock(&data
->lock
);
1255 static int __devinit
w83627thf_read_gpio5(struct platform_device
*pdev
)
1257 int res
= 0xff, sel
;
1260 superio_select(W83627HF_LD_GPIO5
);
1262 /* Make sure these GPIO pins are enabled */
1263 if (!(superio_inb(W83627THF_GPIO5_EN
) & (1<<3))) {
1264 dev_dbg(&pdev
->dev
, "GPIO5 disabled, no VID function\n");
1268 /* Make sure the pins are configured for input
1269 There must be at least five (VRM 9), and possibly 6 (VRM 10) */
1270 sel
= superio_inb(W83627THF_GPIO5_IOSR
) & 0x3f;
1271 if ((sel
& 0x1f) != 0x1f) {
1272 dev_dbg(&pdev
->dev
, "GPIO5 not configured for VID "
1277 dev_info(&pdev
->dev
, "Reading VID from GPIO5\n");
1278 res
= superio_inb(W83627THF_GPIO5_DR
) & sel
;
1285 static int __devinit
w83687thf_read_vid(struct platform_device
*pdev
)
1290 superio_select(W83627HF_LD_HWM
);
1292 /* Make sure these GPIO pins are enabled */
1293 if (!(superio_inb(W83687THF_VID_EN
) & (1 << 2))) {
1294 dev_dbg(&pdev
->dev
, "VID disabled, no VID function\n");
1298 /* Make sure the pins are configured for input */
1299 if (!(superio_inb(W83687THF_VID_CFG
) & (1 << 4))) {
1300 dev_dbg(&pdev
->dev
, "VID configured as output, "
1301 "no VID function\n");
1305 res
= superio_inb(W83687THF_VID_DATA
) & 0x3f;
1312 static int w83627hf_write_value(struct w83627hf_data
*data
, u16 reg
, u16 value
)
1316 mutex_lock(&data
->lock
);
1317 word_sized
= (((reg
& 0xff00) == 0x100)
1318 || ((reg
& 0xff00) == 0x200))
1319 && (((reg
& 0x00ff) == 0x53)
1320 || ((reg
& 0x00ff) == 0x55));
1321 w83627hf_set_bank(data
, reg
);
1322 outb_p(reg
& 0xff, data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1325 data
->addr
+ W83781D_DATA_REG_OFFSET
);
1326 outb_p((reg
& 0xff) + 1,
1327 data
->addr
+ W83781D_ADDR_REG_OFFSET
);
1329 outb_p(value
& 0xff,
1330 data
->addr
+ W83781D_DATA_REG_OFFSET
);
1331 w83627hf_reset_bank(data
, reg
);
1332 mutex_unlock(&data
->lock
);
1336 static void __devinit
w83627hf_init_device(struct platform_device
*pdev
)
1338 struct w83627hf_data
*data
= platform_get_drvdata(pdev
);
1340 enum chips type
= data
->type
;
1344 /* Resetting the chip has been the default for a long time,
1345 but repeatedly caused problems (fans going to full
1346 speed...) so it is now optional. It might even go away if
1347 nobody reports it as being useful, as I see very little
1348 reason why this would be needed at all. */
1349 dev_info(&pdev
->dev
, "If reset=1 solved a problem you were "
1350 "having, please report!\n");
1352 /* save this register */
1353 i
= w83627hf_read_value(data
, W83781D_REG_BEEP_CONFIG
);
1354 /* Reset all except Watchdog values and last conversion values
1355 This sets fan-divs to 2, among others */
1356 w83627hf_write_value(data
, W83781D_REG_CONFIG
, 0x80);
1357 /* Restore the register and disable power-on abnormal beep.
1358 This saves FAN 1/2/3 input/output values set by BIOS. */
1359 w83627hf_write_value(data
, W83781D_REG_BEEP_CONFIG
, i
| 0x80);
1360 /* Disable master beep-enable (reset turns it on).
1361 Individual beeps should be reset to off but for some reason
1362 disabling this bit helps some people not get beeped */
1363 w83627hf_write_value(data
, W83781D_REG_BEEP_INTS2
, 0);
1366 /* Minimize conflicts with other winbond i2c-only clients... */
1367 /* disable i2c subclients... how to disable main i2c client?? */
1368 /* force i2c address to relatively uncommon address */
1369 w83627hf_write_value(data
, W83781D_REG_I2C_SUBADDR
, 0x89);
1370 w83627hf_write_value(data
, W83781D_REG_I2C_ADDR
, force_i2c
);
1372 /* Read VID only once */
1373 if (type
== w83627hf
|| type
== w83637hf
) {
1374 int lo
= w83627hf_read_value(data
, W83781D_REG_VID_FANDIV
);
1375 int hi
= w83627hf_read_value(data
, W83781D_REG_CHIPID
);
1376 data
->vid
= (lo
& 0x0f) | ((hi
& 0x01) << 4);
1377 } else if (type
== w83627thf
) {
1378 data
->vid
= w83627thf_read_gpio5(pdev
);
1379 } else if (type
== w83687thf
) {
1380 data
->vid
= w83687thf_read_vid(pdev
);
1383 /* Read VRM & OVT Config only once */
1384 if (type
== w83627thf
|| type
== w83637hf
|| type
== w83687thf
) {
1386 w83627hf_read_value(data
, W83627THF_REG_VRM_OVT_CFG
);
1389 tmp
= w83627hf_read_value(data
, W83781D_REG_SCFG1
);
1390 for (i
= 1; i
<= 3; i
++) {
1391 if (!(tmp
& BIT_SCFG1
[i
- 1])) {
1392 data
->sens
[i
- 1] = W83781D_DEFAULT_BETA
;
1394 if (w83627hf_read_value
1396 W83781D_REG_SCFG2
) & BIT_SCFG2
[i
- 1])
1397 data
->sens
[i
- 1] = 1;
1399 data
->sens
[i
- 1] = 2;
1401 if ((type
== w83697hf
) && (i
== 2))
1407 tmp
= w83627hf_read_value(data
, W83781D_REG_TEMP2_CONFIG
);
1409 dev_warn(&pdev
->dev
, "Enabling temp2, readings "
1410 "might not make sense\n");
1411 w83627hf_write_value(data
, W83781D_REG_TEMP2_CONFIG
,
1416 if (type
!= w83697hf
) {
1417 tmp
= w83627hf_read_value(data
,
1418 W83781D_REG_TEMP3_CONFIG
);
1420 dev_warn(&pdev
->dev
, "Enabling temp3, "
1421 "readings might not make sense\n");
1422 w83627hf_write_value(data
,
1423 W83781D_REG_TEMP3_CONFIG
, tmp
& 0xfe);
1428 /* Start monitoring */
1429 w83627hf_write_value(data
, W83781D_REG_CONFIG
,
1430 (w83627hf_read_value(data
,
1431 W83781D_REG_CONFIG
) & 0xf7)
1435 static void w83627hf_update_fan_div(struct w83627hf_data
*data
)
1439 reg
= w83627hf_read_value(data
, W83781D_REG_VID_FANDIV
);
1440 data
->fan_div
[0] = (reg
>> 4) & 0x03;
1441 data
->fan_div
[1] = (reg
>> 6) & 0x03;
1442 if (data
->type
!= w83697hf
) {
1443 data
->fan_div
[2] = (w83627hf_read_value(data
,
1444 W83781D_REG_PIN
) >> 6) & 0x03;
1446 reg
= w83627hf_read_value(data
, W83781D_REG_VBAT
);
1447 data
->fan_div
[0] |= (reg
>> 3) & 0x04;
1448 data
->fan_div
[1] |= (reg
>> 4) & 0x04;
1449 if (data
->type
!= w83697hf
)
1450 data
->fan_div
[2] |= (reg
>> 5) & 0x04;
1453 static struct w83627hf_data
*w83627hf_update_device(struct device
*dev
)
1455 struct w83627hf_data
*data
= dev_get_drvdata(dev
);
1458 mutex_lock(&data
->update_lock
);
1460 if (time_after(jiffies
, data
->last_updated
+ HZ
+ HZ
/ 2)
1462 for (i
= 0; i
<= 8; i
++) {
1463 /* skip missing sensors */
1464 if (((data
->type
== w83697hf
) && (i
== 1)) ||
1465 ((data
->type
!= w83627hf
&& data
->type
!= w83697hf
)
1466 && (i
== 5 || i
== 6)))
1469 w83627hf_read_value(data
, W83781D_REG_IN(i
));
1471 w83627hf_read_value(data
,
1472 W83781D_REG_IN_MIN(i
));
1474 w83627hf_read_value(data
,
1475 W83781D_REG_IN_MAX(i
));
1477 for (i
= 1; i
<= 3; i
++) {
1479 w83627hf_read_value(data
, W83781D_REG_FAN(i
));
1480 data
->fan_min
[i
- 1] =
1481 w83627hf_read_value(data
,
1482 W83781D_REG_FAN_MIN(i
));
1484 for (i
= 1; i
<= 3; i
++) {
1485 u8 tmp
= w83627hf_read_value(data
,
1486 W836X7HF_REG_PWM(data
->type
, i
));
1487 /* bits 0-3 are reserved in 627THF */
1488 if (data
->type
== w83627thf
)
1490 data
->pwm
[i
- 1] = tmp
;
1492 (data
->type
== w83627hf
|| data
->type
== w83697hf
))
1496 data
->temp
= w83627hf_read_value(data
, W83781D_REG_TEMP(1));
1498 w83627hf_read_value(data
, W83781D_REG_TEMP_OVER(1));
1499 data
->temp_max_hyst
=
1500 w83627hf_read_value(data
, W83781D_REG_TEMP_HYST(1));
1502 w83627hf_read_value(data
, W83781D_REG_TEMP(2));
1503 data
->temp_max_add
[0] =
1504 w83627hf_read_value(data
, W83781D_REG_TEMP_OVER(2));
1505 data
->temp_max_hyst_add
[0] =
1506 w83627hf_read_value(data
, W83781D_REG_TEMP_HYST(2));
1507 if (data
->type
!= w83697hf
) {
1509 w83627hf_read_value(data
, W83781D_REG_TEMP(3));
1510 data
->temp_max_add
[1] =
1511 w83627hf_read_value(data
, W83781D_REG_TEMP_OVER(3));
1512 data
->temp_max_hyst_add
[1] =
1513 w83627hf_read_value(data
, W83781D_REG_TEMP_HYST(3));
1516 w83627hf_update_fan_div(data
);
1519 w83627hf_read_value(data
, W83781D_REG_ALARM1
) |
1520 (w83627hf_read_value(data
, W83781D_REG_ALARM2
) << 8) |
1521 (w83627hf_read_value(data
, W83781D_REG_ALARM3
) << 16);
1522 i
= w83627hf_read_value(data
, W83781D_REG_BEEP_INTS2
);
1523 data
->beep_enable
= i
>> 7;
1524 data
->beep_mask
= ((i
& 0x7f) << 8) |
1525 w83627hf_read_value(data
, W83781D_REG_BEEP_INTS1
) |
1526 w83627hf_read_value(data
, W83781D_REG_BEEP_INTS3
) << 16;
1527 data
->last_updated
= jiffies
;
1531 mutex_unlock(&data
->update_lock
);
1536 static int __init
w83627hf_device_add(unsigned short address
,
1537 const struct w83627hf_sio_data
*sio_data
)
1539 struct resource res
= {
1540 .start
= address
+ WINB_REGION_OFFSET
,
1541 .end
= address
+ WINB_REGION_OFFSET
+ WINB_REGION_SIZE
- 1,
1543 .flags
= IORESOURCE_IO
,
1547 pdev
= platform_device_alloc(DRVNAME
, address
);
1550 printk(KERN_ERR DRVNAME
": Device allocation failed\n");
1554 err
= platform_device_add_resources(pdev
, &res
, 1);
1556 printk(KERN_ERR DRVNAME
": Device resource addition failed "
1558 goto exit_device_put
;
1561 pdev
->dev
.platform_data
= kmalloc(sizeof(struct w83627hf_sio_data
),
1563 if (!pdev
->dev
.platform_data
) {
1565 printk(KERN_ERR DRVNAME
": Platform data allocation failed\n");
1566 goto exit_device_put
;
1568 memcpy(pdev
->dev
.platform_data
, sio_data
,
1569 sizeof(struct w83627hf_sio_data
));
1571 err
= platform_device_add(pdev
);
1573 printk(KERN_ERR DRVNAME
": Device addition failed (%d)\n",
1575 goto exit_device_put
;
1581 platform_device_put(pdev
);
1586 static int __init
sensors_w83627hf_init(void)
1589 unsigned short address
;
1590 struct w83627hf_sio_data sio_data
;
1592 if (w83627hf_find(0x2e, &address
, &sio_data
)
1593 && w83627hf_find(0x4e, &address
, &sio_data
))
1596 err
= platform_driver_register(&w83627hf_driver
);
1600 /* Sets global pdev as a side effect */
1601 err
= w83627hf_device_add(address
, &sio_data
);
1608 platform_driver_unregister(&w83627hf_driver
);
1613 static void __exit
sensors_w83627hf_exit(void)
1615 platform_device_unregister(pdev
);
1616 platform_driver_unregister(&w83627hf_driver
);
1619 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
1620 "Philip Edelbrock <phil@netroedge.com>, "
1621 "and Mark Studebaker <mdsxyz123@yahoo.com>");
1622 MODULE_DESCRIPTION("W83627HF driver");
1623 MODULE_LICENSE("GPL");
1625 module_init(sensors_w83627hf_init
);
1626 module_exit(sensors_w83627hf_exit
);