include/asm-sh/irq.h

   1 #ifndef __ASM_SH_IRQ_H
   2 #define __ASM_SH_IRQ_H
   3
   4 /*
   5  *
   6  * linux/include/asm-sh/irq.h
   7  *
   8  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   9  * Copyright (C) 2000  Kazumoto Kojima
  10  * Copyright (C) 2003  Paul Mundt
  11  *
  12  */
  13
  14 #include <asm/machvec.h>
  15 #include <asm/ptrace.h>         /* for pt_regs */
  16
  17 #if defined(CONFIG_SH_HP6XX) || \
  18     defined(CONFIG_SH_RTS7751R2D) || \
  19     defined(CONFIG_SH_HS7751RVOIP) || \
  20     defined(CONFIG_SH_HS7751RVOIP) || \
  21     defined(CONFIG_SH_SH03) || \
  22     defined(CONFIG_SH_R7780RP) || \
  23     defined(CONFIG_SH_LANDISK)
  24 #include <asm/mach/ide.h>
  25 #endif
  26
  27 #ifndef CONFIG_CPU_SUBTYPE_SH7780
  28
  29 #define INTC_DMAC0_MSK  0
  30
  31 #if defined(CONFIG_CPU_SH3)
  32 #define INTC_IPRA       0xfffffee2UL
  33 #define INTC_IPRB       0xfffffee4UL
  34 #elif defined(CONFIG_CPU_SH4)
  35 #define INTC_IPRA       0xffd00004UL
  36 #define INTC_IPRB       0xffd00008UL
  37 #define INTC_IPRC       0xffd0000cUL
  38 #define INTC_IPRD       0xffd00010UL
  39 #endif
  40
  41 #ifdef CONFIG_IDE
  42 # ifndef IRQ_CFCARD
  43 #  define IRQ_CFCARD    14
  44 # endif
  45 # ifndef IRQ_PCMCIA
  46 #  define IRQ_PCMCIA    15
  47 # endif
  48 #endif
  49
  50 #define TIMER_IRQ       16
  51 #define TIMER_IPR_ADDR  INTC_IPRA
  52 #define TIMER_IPR_POS    3
  53 #define TIMER_PRIORITY   2
  54
  55 #define TIMER1_IRQ      17
  56 #define TIMER1_IPR_ADDR INTC_IPRA
  57 #define TIMER1_IPR_POS   2
  58 #define TIMER1_PRIORITY  4
  59
  60 #define RTC_IRQ         22
  61 #define RTC_IPR_ADDR    INTC_IPRA
  62 #define RTC_IPR_POS      0
  63 #define RTC_PRIORITY    TIMER_PRIORITY
  64
  65 #if defined(CONFIG_CPU_SH3)
  66 #define DMTE0_IRQ       48
  67 #define DMTE1_IRQ       49
  68 #define DMTE2_IRQ       50
  69 #define DMTE3_IRQ       51
  70 #define DMA_IPR_ADDR    INTC_IPRE
  71 #define DMA_IPR_POS     3
  72 #define DMA_PRIORITY    7
  73 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  74 /* TMU2 */
  75 #define TIMER2_IRQ      18
  76 #define TIMER2_IPR_ADDR INTC_IPRA
  77 #define TIMER2_IPR_POS   1
  78 #define TIMER2_PRIORITY  2
  79
  80 /* WDT */
  81 #define WDT_IRQ         27
  82 #define WDT_IPR_ADDR    INTC_IPRB
  83 #define WDT_IPR_POS      3
  84 #define WDT_PRIORITY     2
  85
  86 /* SIM (SIM Card Module) */
  87 #define SIM_ERI_IRQ     23
  88 #define SIM_RXI_IRQ     24
  89 #define SIM_TXI_IRQ     25
  90 #define SIM_TEND_IRQ    26
  91 #define SIM_IPR_ADDR    INTC_IPRB
  92 #define SIM_IPR_POS      1
  93 #define SIM_PRIORITY     2
  94
  95 /* VIO (Video I/O) */
  96 #define VIO_IRQ         52
  97 #define VIO_IPR_ADDR    INTC_IPRE
  98 #define VIO_IPR_POS      2
  99 #define VIO_PRIORITY     2
 100
 101 /* MFI (Multi Functional Interface) */
 102 #define MFI_IRQ         56
 103 #define MFI_IPR_ADDR    INTC_IPRE
 104 #define MFI_IPR_POS      1
 105 #define MFI_PRIORITY     2
 106
 107 /* VPU (Video Processing Unit) */
 108 #define VPU_IRQ         60
 109 #define VPU_IPR_ADDR    INTC_IPRE
 110 #define VPU_IPR_POS      0
 111 #define VPU_PRIORITY     2
 112
 113 /* KEY (Key Scan Interface) */
 114 #define KEY_IRQ         79
 115 #define KEY_IPR_ADDR    INTC_IPRF
 116 #define KEY_IPR_POS      3
 117 #define KEY_PRIORITY     2
 118
 119 /* CMT (Compare Match Timer) */
 120 #define CMT_IRQ         104
 121 #define CMT_IPR_ADDR    INTC_IPRF
 122 #define CMT_IPR_POS      0
 123 #define CMT_PRIORITY     2
 124
 125 /* DMAC(1) */
 126 #define DMTE0_IRQ       48
 127 #define DMTE1_IRQ       49
 128 #define DMTE2_IRQ       50
 129 #define DMTE3_IRQ       51
 130 #define DMA1_IPR_ADDR   INTC_IPRE
 131 #define DMA1_IPR_POS    3
 132 #define DMA1_PRIORITY   7
 133
 134 /* DMAC(2) */
 135 #define DMTE4_IRQ       76
 136 #define DMTE5_IRQ       77
 137 #define DMA2_IPR_ADDR   INTC_IPRF
 138 #define DMA2_IPR_POS    2
 139 #define DMA2_PRIORITY   7
 140
 141 /* SIOF0 */
 142 #define SIOF0_IRQ       84
 143 #define SIOF0_IPR_ADDR  INTC_IPRH
 144 #define SIOF0_IPR_POS   3
 145 #define SIOF0_PRIORITY  3
 146
 147 /* FLCTL (Flash Memory Controller) */
 148 #define FLSTE_IRQ       92
 149 #define FLTEND_IRQ      93
 150 #define FLTRQ0_IRQ      94
 151 #define FLTRQ1_IRQ      95
 152 #define FLCTL_IPR_ADDR  INTC_IPRH
 153 #define FLCTL_IPR_POS   1
 154 #define FLCTL_PRIORITY  3
 155
 156 /* IIC (IIC Bus Interface) */
 157 #define IIC_ALI_IRQ     96
 158 #define IIC_TACKI_IRQ   97
 159 #define IIC_WAITI_IRQ   98
 160 #define IIC_DTEI_IRQ    99
 161 #define IIC_IPR_ADDR    INTC_IPRH
 162 #define IIC_IPR_POS     0
 163 #define IIC_PRIORITY    3
 164
 165 /* SIO0 */
 166 #define SIO0_IRQ        88
 167 #define SIO0_IPR_ADDR   INTC_IPRI
 168 #define SIO0_IPR_POS    3
 169 #define SIO0_PRIORITY   3
 170
 171 /* SIU (Sound Interface Unit) */
 172 #define SIU_IRQ         108
 173 #define SIU_IPR_ADDR    INTC_IPRJ
 174 #define SIU_IPR_POS     1
 175 #define SIU_PRIORITY    3
 176
 177 #endif
 178 #elif defined(CONFIG_CPU_SH4)
 179 #define DMTE0_IRQ       34
 180 #define DMTE1_IRQ       35
 181 #define DMTE2_IRQ       36
 182 #define DMTE3_IRQ       37
 183 #define DMTE4_IRQ       44      /* 7751R only */
 184 #define DMTE5_IRQ       45      /* 7751R only */
 185 #define DMTE6_IRQ       46      /* 7751R only */
 186 #define DMTE7_IRQ       47      /* 7751R only */
 187 #define DMAE_IRQ        38
 188 #define DMA_IPR_ADDR    INTC_IPRC
 189 #define DMA_IPR_POS     2
 190 #define DMA_PRIORITY    7
 191 #endif
 192
 193 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
 194     defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
 195     defined (CONFIG_CPU_SUBTYPE_SH7751)
 196 #define SCI_ERI_IRQ     23
 197 #define SCI_RXI_IRQ     24
 198 #define SCI_TXI_IRQ     25
 199 #define SCI_IPR_ADDR    INTC_IPRB
 200 #define SCI_IPR_POS     1
 201 #define SCI_PRIORITY    3
 202 #endif
 203
 204 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 205 #define SCIF0_IRQ       80
 206 #define SCIF0_IPR_ADDR  INTC_IPRG
 207 #define SCIF0_IPR_POS   3
 208 #define SCIF0_PRIORITY  3
 209 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 210       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 211       defined(CONFIG_CPU_SUBTYPE_SH7709)
 212 #define SCIF_ERI_IRQ    56
 213 #define SCIF_RXI_IRQ    57
 214 #define SCIF_BRI_IRQ    58
 215 #define SCIF_TXI_IRQ    59
 216 #define SCIF_IPR_ADDR   INTC_IPRE
 217 #define SCIF_IPR_POS    1
 218 #define SCIF_PRIORITY   3
 219
 220 #define IRDA_ERI_IRQ    52
 221 #define IRDA_RXI_IRQ    53
 222 #define IRDA_BRI_IRQ    54
 223 #define IRDA_TXI_IRQ    55
 224 #define IRDA_IPR_ADDR   INTC_IPRE
 225 #define IRDA_IPR_POS    2
 226 #define IRDA_PRIORITY   3
 227 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 228       defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 229 #define SCIF_ERI_IRQ    40
 230 #define SCIF_RXI_IRQ    41
 231 #define SCIF_BRI_IRQ    42
 232 #define SCIF_TXI_IRQ    43
 233 #define SCIF_IPR_ADDR   INTC_IPRC
 234 #define SCIF_IPR_POS    1
 235 #define SCIF_PRIORITY   3
 236 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 237 #define SCIF1_ERI_IRQ   23
 238 #define SCIF1_RXI_IRQ   24
 239 #define SCIF1_BRI_IRQ   25
 240 #define SCIF1_TXI_IRQ   26
 241 #define SCIF1_IPR_ADDR  INTC_IPRB
 242 #define SCIF1_IPR_POS   1
 243 #define SCIF1_PRIORITY  3
 244 #endif /* ST40STB1 */
 245
 246 #endif /* 775x / SH4-202 / ST40STB1 */
 247 #endif /* 7780 */
 248
 249 /* NR_IRQS is made from three components:
 250  *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
 251  *   2. PINT_NR_IRQS   - number of PINT interrupts
 252  *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
 253  */
 254
 255 /* 1. ONCHIP_NR_IRQS */
 256 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
 257 # define ONCHIP_NR_IRQS 24      // Actually 21
 258 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 259 # define ONCHIP_NR_IRQS 64
 260 # define PINT_NR_IRQS   16
 261 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 262 # define ONCHIP_NR_IRQS 32
 263 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 264       defined(CONFIG_CPU_SUBTYPE_SH7705)
 265 # define ONCHIP_NR_IRQS 64      // Actually 61
 266 # define PINT_NR_IRQS   16
 267 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 268 # define ONCHIP_NR_IRQS 48      // Actually 44
 269 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
 270 # define ONCHIP_NR_IRQS 72
 271 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 272 # define ONCHIP_NR_IRQS 112     /* XXX */
 273 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 274 # define ONCHIP_NR_IRQS 72
 275 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 276 # define ONCHIP_NR_IRQS 144
 277 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
 278       defined(CONFIG_CPU_SUBTYPE_SH73180)
 279 # define ONCHIP_NR_IRQS 109
 280 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 281 # define ONCHIP_NR_IRQS 111
 282 #elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
 283 # define ONCHIP_NR_IRQS 144
 284 #endif
 285
 286 /* 2. PINT_NR_IRQS */
 287 #ifdef CONFIG_SH_UNKNOWN
 288 # define PINT_NR_IRQS 16
 289 #else
 290 # ifndef PINT_NR_IRQS
 291 #  define PINT_NR_IRQS 0
 292 # endif
 293 #endif
 294
 295 #if PINT_NR_IRQS > 0
 296 # define PINT_IRQ_BASE  ONCHIP_NR_IRQS
 297 #endif
 298
 299 /* 3. OFFCHIP_NR_IRQS */
 300 #if defined(CONFIG_HD64461)
 301 # define OFFCHIP_NR_IRQS 18
 302 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
 303 # define OFFCHIP_NR_IRQS 48
 304 #elif defined(CONFIG_HD64465)
 305 # define OFFCHIP_NR_IRQS 16
 306 #elif defined (CONFIG_SH_EC3104)
 307 # define OFFCHIP_NR_IRQS 16
 308 #elif defined (CONFIG_SH_DREAMCAST)
 309 # define OFFCHIP_NR_IRQS 96
 310 #elif defined (CONFIG_SH_TITAN)
 311 # define OFFCHIP_NR_IRQS 4
 312 #elif defined(CONFIG_SH_R7780RP)
 313 # define OFFCHIP_NR_IRQS 16
 314 #elif defined(CONFIG_SH_UNKNOWN)
 315 # define OFFCHIP_NR_IRQS 16     /* Must also be last */
 316 #else
 317 # define OFFCHIP_NR_IRQS 0
 318 #endif
 319
 320 #if OFFCHIP_NR_IRQS > 0
 321 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
 322 #endif
 323
 324 /* NR_IRQS. 1+2+3 */
 325 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
 326
 327 extern void disable_irq(unsigned int);
 328 extern void disable_irq_nosync(unsigned int);
 329 extern void enable_irq(unsigned int);
 330
 331 /*
 332  * Simple Mask Register Support
 333  */
 334 extern void make_maskreg_irq(unsigned int irq);
 335 extern unsigned short *irq_mask_register;
 336
 337 /*
 338  * Function for "on chip support modules".
 339  */
 340 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
 341                          int pos,  int priority);
 342 extern void make_imask_irq(unsigned int irq);
 343
 344 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 345 #undef INTC_IPRA
 346 #undef INTC_IPRB
 347 #define INTC_IPRA       0xA414FEE2UL
 348 #define INTC_IPRB       0xA414FEE4UL
 349 #define INTC_IPRC       0xA4140016UL
 350 #define INTC_IPRD       0xA4140018UL
 351 #define INTC_IPRE       0xA414001AUL
 352 #define INTC_IPRF       0xA4080000UL
 353 #define INTC_IPRG       0xA4080002UL
 354 #define INTC_IPRH       0xA4080004UL
 355 #define INTC_IPRI       0xA4080006UL
 356 #define INTC_IPRJ       0xA4080008UL
 357
 358 #define INTC_IMR0       0xA4080040UL
 359 #define INTC_IMR1       0xA4080042UL
 360 #define INTC_IMR2       0xA4080044UL
 361 #define INTC_IMR3       0xA4080046UL
 362 #define INTC_IMR4       0xA4080048UL
 363 #define INTC_IMR5       0xA408004AUL
 364 #define INTC_IMR6       0xA408004CUL
 365 #define INTC_IMR7       0xA408004EUL
 366 #define INTC_IMR8       0xA4080050UL
 367 #define INTC_IMR9       0xA4080052UL
 368 #define INTC_IMR10      0xA4080054UL
 369
 370 #define INTC_IMCR0      0xA4080060UL
 371 #define INTC_IMCR1      0xA4080062UL
 372 #define INTC_IMCR2      0xA4080064UL
 373 #define INTC_IMCR3      0xA4080066UL
 374 #define INTC_IMCR4      0xA4080068UL
 375 #define INTC_IMCR5      0xA408006AUL
 376 #define INTC_IMCR6      0xA408006CUL
 377 #define INTC_IMCR7      0xA408006EUL
 378 #define INTC_IMCR8      0xA4080070UL
 379 #define INTC_IMCR9      0xA4080072UL
 380 #define INTC_IMCR10     0xA4080074UL
 381
 382 #define INTC_ICR0       0xA414FEE0UL
 383 #define INTC_ICR1       0xA4140010UL
 384
 385 #define INTC_IRR0       0xA4140004UL
 386
 387 #define PORT_PACR       0xA4050100UL
 388 #define PORT_PBCR       0xA4050102UL
 389 #define PORT_PCCR       0xA4050104UL
 390 #define PORT_PDCR       0xA4050106UL
 391 #define PORT_PECR       0xA4050108UL
 392 #define PORT_PFCR       0xA405010AUL
 393 #define PORT_PGCR       0xA405010CUL
 394 #define PORT_PHCR       0xA405010EUL
 395 #define PORT_PJCR       0xA4050110UL
 396 #define PORT_PKCR       0xA4050112UL
 397 #define PORT_PLCR       0xA4050114UL
 398 #define PORT_SCPCR      0xA4050116UL
 399 #define PORT_PMCR       0xA4050118UL
 400 #define PORT_PNCR       0xA405011AUL
 401 #define PORT_PQCR       0xA405011CUL
 402
 403 #define PORT_PSELA      0xA4050140UL
 404 #define PORT_PSELB      0xA4050142UL
 405 #define PORT_PSELC      0xA4050144UL
 406
 407 #define PORT_HIZCRA     0xA4050146UL
 408 #define PORT_HIZCRB     0xA4050148UL
 409 #define PORT_DRVCR      0xA4050150UL
 410
 411 #define PORT_PADR       0xA4050120UL
 412 #define PORT_PBDR       0xA4050122UL
 413 #define PORT_PCDR       0xA4050124UL
 414 #define PORT_PDDR       0xA4050126UL
 415 #define PORT_PEDR       0xA4050128UL
 416 #define PORT_PFDR       0xA405012AUL
 417 #define PORT_PGDR       0xA405012CUL
 418 #define PORT_PHDR       0xA405012EUL
 419 #define PORT_PJDR       0xA4050130UL
 420 #define PORT_PKDR       0xA4050132UL
 421 #define PORT_PLDR       0xA4050134UL
 422 #define PORT_SCPDR      0xA4050136UL
 423 #define PORT_PMDR       0xA4050138UL
 424 #define PORT_PNDR       0xA405013AUL
 425 #define PORT_PQDR       0xA405013CUL
 426
 427 #define IRQ0_IRQ        32
 428 #define IRQ1_IRQ        33
 429 #define IRQ2_IRQ        34
 430 #define IRQ3_IRQ        35
 431 #define IRQ4_IRQ        36
 432 #define IRQ5_IRQ        37
 433
 434 #define IRQ0_IPR_ADDR   INTC_IPRC
 435 #define IRQ1_IPR_ADDR   INTC_IPRC
 436 #define IRQ2_IPR_ADDR   INTC_IPRC
 437 #define IRQ3_IPR_ADDR   INTC_IPRC
 438 #define IRQ4_IPR_ADDR   INTC_IPRD
 439 #define IRQ5_IPR_ADDR   INTC_IPRD
 440
 441 #define IRQ0_IPR_POS    0
 442 #define IRQ1_IPR_POS    1
 443 #define IRQ2_IPR_POS    2
 444 #define IRQ3_IPR_POS    3
 445 #define IRQ4_IPR_POS    0
 446 #define IRQ5_IPR_POS    1
 447
 448 #define IRQ0_PRIORITY   1
 449 #define IRQ1_PRIORITY   1
 450 #define IRQ2_PRIORITY   1
 451 #define IRQ3_PRIORITY   1
 452 #define IRQ4_PRIORITY   1
 453 #define IRQ5_PRIORITY   1
 454
 455 extern int ipr_irq_demux(int irq);
 456 #define __irq_demux(irq) ipr_irq_demux(irq)
 457
 458 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 459 #define INTC_IPRA       0xfffffee2UL
 460 #define INTC_IPRB       0xfffffe60UL
 461
 462 #define INTC_VCRA       0xfffffe62UL
 463 #define INTC_VCRB       0xfffffe64UL
 464 #define INTC_VCRC       0xfffffe66UL
 465 #define INTC_VCRD       0xfffffe68UL
 466
 467 #define INTC_VCRWDT     0xfffffee4UL
 468 #define INTC_VCRDIV     0xffffff0cUL
 469 #define INTC_VCRDMA0    0xffffffa0UL
 470 #define INTC_VCRDMA1    0xffffffa8UL
 471
 472 #define INTC_ICR        0xfffffee0UL
 473 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 474       defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 475       defined(CONFIG_CPU_SUBTYPE_SH7709)
 476 #define INTC_IRR0       0xa4000004UL
 477 #define INTC_IRR1       0xa4000006UL
 478 #define INTC_IRR2       0xa4000008UL
 479
 480 #define INTC_ICR0       0xfffffee0UL
 481 #define INTC_ICR1       0xa4000010UL
 482 #define INTC_ICR2       0xa4000012UL
 483 #define INTC_INTER      0xa4000014UL
 484
 485 #define INTC_IPRC       0xa4000016UL
 486 #define INTC_IPRD       0xa4000018UL
 487 #define INTC_IPRE       0xa400001aUL
 488 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 489 #define INTC_IPRF       0xa400001cUL
 490 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 491 #define INTC_IPRF       0xa4080000UL
 492 #define INTC_IPRG       0xa4080002UL
 493 #define INTC_IPRH       0xa4080004UL
 494 #endif
 495
 496 #define PORT_PACR       0xa4000100UL
 497 #define PORT_PBCR       0xa4000102UL
 498 #define PORT_PCCR       0xa4000104UL
 499 #define PORT_PFCR       0xa400010aUL
 500 #define PORT_PADR       0xa4000120UL
 501 #define PORT_PBDR       0xa4000122UL
 502 #define PORT_PCDR       0xa4000124UL
 503 #define PORT_PFDR       0xa400012aUL
 504
 505 #define IRQ0_IRQ        32
 506 #define IRQ1_IRQ        33
 507 #define IRQ2_IRQ        34
 508 #define IRQ3_IRQ        35
 509 #define IRQ4_IRQ        36
 510 #define IRQ5_IRQ        37
 511
 512 #define IRQ0_IPR_ADDR   INTC_IPRC
 513 #define IRQ1_IPR_ADDR   INTC_IPRC
 514 #define IRQ2_IPR_ADDR   INTC_IPRC
 515 #define IRQ3_IPR_ADDR   INTC_IPRC
 516 #define IRQ4_IPR_ADDR   INTC_IPRD
 517 #define IRQ5_IPR_ADDR   INTC_IPRD
 518
 519 #define IRQ0_IPR_POS    0
 520 #define IRQ1_IPR_POS    1
 521 #define IRQ2_IPR_POS    2
 522 #define IRQ3_IPR_POS    3
 523 #define IRQ4_IPR_POS    0
 524 #define IRQ5_IPR_POS    1
 525
 526 #define IRQ0_PRIORITY   1
 527 #define IRQ1_PRIORITY   1
 528 #define IRQ2_PRIORITY   1
 529 #define IRQ3_PRIORITY   1
 530 #define IRQ4_PRIORITY   1
 531 #define IRQ5_PRIORITY   1
 532
 533 #define PINT0_IRQ       40
 534 #define PINT8_IRQ       41
 535
 536 #define PINT0_IPR_ADDR  INTC_IPRD
 537 #define PINT8_IPR_ADDR  INTC_IPRD
 538
 539 #define PINT0_IPR_POS   3
 540 #define PINT8_IPR_POS   2
 541 #define PINT0_PRIORITY  2
 542 #define PINT8_PRIORITY  2
 543
 544 extern int ipr_irq_demux(int irq);
 545 #define __irq_demux(irq) ipr_irq_demux(irq)
 546 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 547
 548 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 549     defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
 550 #define INTC_ICR        0xffd00000
 551 #define INTC_ICR_NMIL   (1<<15)
 552 #define INTC_ICR_MAI    (1<<14)
 553 #define INTC_ICR_NMIB   (1<<9)
 554 #define INTC_ICR_NMIE   (1<<8)
 555 #define INTC_ICR_IRLM   (1<<7)
 556 #endif
 557
 558 #ifdef CONFIG_CPU_SUBTYPE_SH7780
 559 #include <asm/irq-sh7780.h>
 560 #endif
 561
 562 /* SH with INTC2-style interrupts */
 563 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
 564 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 565 #define INTC2_BASE      0xfe080000
 566 #define INTC2_FIRST_IRQ 64
 567 #define INTC2_INTREQ_OFFSET     0x20
 568 #define INTC2_INTMSK_OFFSET     0x40
 569 #define INTC2_INTMSKCLR_OFFSET  0x60
 570 #define NR_INTC2_IRQS   25
 571 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 572 #define INTC2_BASE      0xfe080000
 573 #define INTC2_FIRST_IRQ 48      /* INTEVT 0x800 */
 574 #define INTC2_INTREQ_OFFSET     0x20
 575 #define INTC2_INTMSK_OFFSET     0x40
 576 #define INTC2_INTMSKCLR_OFFSET  0x60
 577 #define NR_INTC2_IRQS   64
 578 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 579 #define INTC2_BASE      0xffd40000
 580 #define INTC2_FIRST_IRQ 22
 581 #define INTC2_INTMSK_OFFSET     (0x38)
 582 #define INTC2_INTMSKCLR_OFFSET  (0x3c)
 583 #define NR_INTC2_IRQS   60
 584 #endif
 585
 586 #define INTC2_INTPRI_OFFSET     0x00
 587
 588 void make_intc2_irq(unsigned int irq,
 589                     unsigned int ipr_offset, unsigned int ipr_shift,
 590                     unsigned int msk_offset, unsigned int msk_shift,
 591                     unsigned int priority);
 592 void init_IRQ_intc2(void);
 593 void intc2_add_clear_irq(int irq, int (*fn)(int));
 594
 595 #endif
 596
 597 static inline int generic_irq_demux(int irq)
 598 {
 599         return irq;
 600 }
 601
 602 #ifndef __irq_demux
 603 #define __irq_demux(irq)        (irq)
 604 #endif
 605 #define irq_canonicalize(irq)   (irq)
 606 #define irq_demux(irq)          __irq_demux(sh_mv.mv_irq_demux(irq))
 607
 608 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
 609 #include <asm/irq-sh73180.h>
 610 #endif
 611
 612 #endif /* __ASM_SH_IRQ_H */