2 * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
4 * Copyright (C) 2005 Kontron Canada
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
16 * NON INFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
24 * Maintainer <mark.gross@intel.com>
26 * Description : This is the TELECOM CLOCK module driver for the ATCA
27 * MPCBL0010 ATCA computer.
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34 #include <linux/kernel.h> /* printk() */
35 #include <linux/fs.h> /* everything... */
36 #include <linux/errno.h> /* error codes */
37 #include <linux/slab.h>
38 #include <linux/ioport.h>
39 #include <linux/interrupt.h>
40 #include <linux/spinlock.h>
41 #include <linux/timer.h>
42 #include <linux/sysfs.h>
43 #include <linux/device.h>
44 #include <linux/miscdevice.h>
45 #include <linux/platform_device.h>
46 #include <asm/io.h> /* inb/outb */
47 #include <asm/uaccess.h>
49 MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
50 MODULE_LICENSE("GPL");
52 /*Hardware Reset of the PLL */
54 #define RESET_OFF 0x01
57 #define NORMAL_MODE 0x00
58 #define HOLDOVER_MODE 0x10
59 #define FREERUN_MODE 0x20
62 #define FILTER_6HZ 0x04
63 #define FILTER_12HZ 0x00
65 /* SELECT REFERENCE FREQUENCY */
66 #define REF_CLK1_8kHz 0x00
67 #define REF_CLK2_19_44MHz 0x02
69 /* Select primary or secondary redundant clock */
70 #define PRIMARY_CLOCK 0x00
71 #define SECONDARY_CLOCK 0x01
73 /* CLOCK TRANSMISSION DEFINE */
75 #define CLK_16_384MHz 0xfb
77 #define CLK_1_544MHz 0x00
78 #define CLK_2_048MHz 0x01
79 #define CLK_4_096MHz 0x02
80 #define CLK_6_312MHz 0x03
81 #define CLK_8_192MHz 0x04
82 #define CLK_19_440MHz 0x06
84 #define CLK_8_592MHz 0x08
85 #define CLK_11_184MHz 0x09
86 #define CLK_34_368MHz 0x0b
87 #define CLK_44_736MHz 0x0a
89 /* RECEIVED REFERENCE */
93 /* HARDWARE SWITCHING DEFINE */
94 #define HW_ENABLE 0x80
95 #define HW_DISABLE 0x00
97 /* HARDWARE SWITCHING MODE DEFINE */
98 #define PLL_HOLDOVER 0x40
99 #define LOST_CLOCK 0x00
102 #define UNLOCK_MASK 0x10
103 #define HOLDOVER_MASK 0x20
104 #define SEC_LOST_MASK 0x40
105 #define PRI_LOST_MASK 0x80
107 /* INTERRUPT CAUSE DEFINE */
109 #define PRI_LOS_01_MASK 0x01
110 #define PRI_LOS_10_MASK 0x02
112 #define SEC_LOS_01_MASK 0x04
113 #define SEC_LOS_10_MASK 0x08
115 #define HOLDOVER_01_MASK 0x10
116 #define HOLDOVER_10_MASK 0x20
118 #define UNLOCK_01_MASK 0x40
119 #define UNLOCK_10_MASK 0x80
121 struct tlclk_alarms
{
123 __u32 lost_primary_clock
;
124 __u32 lost_secondary_clock
;
125 __u32 primary_clock_back
;
126 __u32 secondary_clock_back
;
127 __u32 switchover_primary
;
128 __u32 switchover_secondary
;
130 __u32 pll_end_holdover
;
134 /* Telecom clock I/O register definition */
135 #define TLCLK_BASE 0xa08
136 #define TLCLK_REG0 TLCLK_BASE
137 #define TLCLK_REG1 (TLCLK_BASE+1)
138 #define TLCLK_REG2 (TLCLK_BASE+2)
139 #define TLCLK_REG3 (TLCLK_BASE+3)
140 #define TLCLK_REG4 (TLCLK_BASE+4)
141 #define TLCLK_REG5 (TLCLK_BASE+5)
142 #define TLCLK_REG6 (TLCLK_BASE+6)
143 #define TLCLK_REG7 (TLCLK_BASE+7)
145 #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
147 /* 0 = Dynamic allocation of the major device number */
148 #define TLCLK_MAJOR 0
150 /* sysfs interface definition:
151 Upon loading the driver will create a sysfs directory under
152 /sys/devices/platform/telco_clock.
154 This directory exports the following interfaces. There operation is
155 documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
160 enable_clk3a_output :
161 enable_clk3b_output :
162 enable_clka0_output :
163 enable_clka1_output :
164 enable_clkb0_output :
165 enable_clkb1_output :
168 hardware_switching_mode :
173 select_amcb1_transmit_clock :
174 select_amcb2_transmit_clock :
175 select_redundant_clock :
176 select_ref_frequency :
178 All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
179 has the same effect as echo 0x99 > refalign.
182 static unsigned int telclk_interrupt
;
184 static int int_events
; /* Event that generate a interrupt */
185 static int got_event
; /* if events processing have been done */
187 static void switchover_timeout(unsigned long data
);
188 static struct timer_list switchover_timer
=
189 TIMER_INITIALIZER(switchover_timeout
, 0, 0);
191 static struct tlclk_alarms
*alarm_events
;
193 static DEFINE_SPINLOCK(event_lock
);
195 static int tlclk_major
= TLCLK_MAJOR
;
197 static irqreturn_t
tlclk_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
199 static DECLARE_WAIT_QUEUE_HEAD(wq
);
201 static int tlclk_open(struct inode
*inode
, struct file
*filp
)
205 /* Make sure there is no interrupt pending while
206 * initialising interrupt handler */
209 /* This device is wired through the FPGA IO space of the ATCA blade
210 * we can't share this IRQ */
211 result
= request_irq(telclk_interrupt
, &tlclk_interrupt
,
212 SA_INTERRUPT
, "telco_clock", tlclk_interrupt
);
213 if (result
== -EBUSY
) {
214 printk(KERN_ERR
"tlclk: Interrupt can't be reserved.\n");
217 inb(TLCLK_REG6
); /* Clear interrupt events */
222 static int tlclk_release(struct inode
*inode
, struct file
*filp
)
224 free_irq(telclk_interrupt
, tlclk_interrupt
);
229 static ssize_t
tlclk_read(struct file
*filp
, char __user
*buf
, size_t count
,
232 if (count
< sizeof(struct tlclk_alarms
))
235 wait_event_interruptible(wq
, got_event
);
236 if (copy_to_user(buf
, alarm_events
, sizeof(struct tlclk_alarms
)))
239 memset(alarm_events
, 0, sizeof(struct tlclk_alarms
));
242 return sizeof(struct tlclk_alarms
);
245 static ssize_t
tlclk_write(struct file
*filp
, const char __user
*buf
, size_t count
,
251 static struct file_operations tlclk_fops
= {
253 .write
= tlclk_write
,
255 .release
= tlclk_release
,
259 static struct miscdevice tlclk_miscdev
= {
260 .minor
= MISC_DYNAMIC_MINOR
,
261 .name
= "telco_clock",
265 static ssize_t
show_current_ref(struct device
*d
,
266 struct device_attribute
*attr
, char *buf
)
268 unsigned long ret_val
;
271 spin_lock_irqsave(&event_lock
, flags
);
272 ret_val
= ((inb(TLCLK_REG1
) & 0x08) >> 3);
273 spin_unlock_irqrestore(&event_lock
, flags
);
275 return sprintf(buf
, "0x%lX\n", ret_val
);
278 static DEVICE_ATTR(current_ref
, S_IRUGO
, show_current_ref
, NULL
);
281 static ssize_t
show_telclock_version(struct device
*d
,
282 struct device_attribute
*attr
, char *buf
)
284 unsigned long ret_val
;
287 spin_lock_irqsave(&event_lock
, flags
);
288 ret_val
= inb(TLCLK_REG5
);
289 spin_unlock_irqrestore(&event_lock
, flags
);
291 return sprintf(buf
, "0x%lX\n", ret_val
);
294 static DEVICE_ATTR(telclock_version
, S_IRUGO
,
295 show_telclock_version
, NULL
);
297 static ssize_t
show_alarms(struct device
*d
,
298 struct device_attribute
*attr
, char *buf
)
300 unsigned long ret_val
;
303 spin_lock_irqsave(&event_lock
, flags
);
304 ret_val
= (inb(TLCLK_REG2
) & 0xf0);
305 spin_unlock_irqrestore(&event_lock
, flags
);
307 return sprintf(buf
, "0x%lX\n", ret_val
);
310 static DEVICE_ATTR(alarms
, S_IRUGO
, show_alarms
, NULL
);
312 static ssize_t
store_received_ref_clk3a(struct device
*d
,
313 struct device_attribute
*attr
, const char *buf
, size_t count
)
319 sscanf(buf
, "%lX", &tmp
);
320 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
322 val
= (unsigned char)tmp
;
323 spin_lock_irqsave(&event_lock
, flags
);
324 SET_PORT_BITS(TLCLK_REG1
, 0xef, val
);
325 spin_unlock_irqrestore(&event_lock
, flags
);
327 return strnlen(buf
, count
);
330 static DEVICE_ATTR(received_ref_clk3a
, (S_IWUSR
|S_IWGRP
), NULL
,
331 store_received_ref_clk3a
);
334 static ssize_t
store_received_ref_clk3b(struct device
*d
,
335 struct device_attribute
*attr
, const char *buf
, size_t count
)
341 sscanf(buf
, "%lX", &tmp
);
342 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
344 val
= (unsigned char)tmp
;
345 spin_lock_irqsave(&event_lock
, flags
);
346 SET_PORT_BITS(TLCLK_REG1
, 0xef, val
<< 1);
347 spin_unlock_irqrestore(&event_lock
, flags
);
349 return strnlen(buf
, count
);
352 static DEVICE_ATTR(received_ref_clk3b
, (S_IWUSR
|S_IWGRP
), NULL
,
353 store_received_ref_clk3b
);
356 static ssize_t
store_enable_clk3b_output(struct device
*d
,
357 struct device_attribute
*attr
, const char *buf
, size_t count
)
363 sscanf(buf
, "%lX", &tmp
);
364 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
366 val
= (unsigned char)tmp
;
367 spin_lock_irqsave(&event_lock
, flags
);
368 SET_PORT_BITS(TLCLK_REG3
, 0x7f, val
<< 7);
369 spin_unlock_irqrestore(&event_lock
, flags
);
371 return strnlen(buf
, count
);
374 static DEVICE_ATTR(enable_clk3b_output
, (S_IWUSR
|S_IWGRP
), NULL
,
375 store_enable_clk3b_output
);
377 static ssize_t
store_enable_clk3a_output(struct device
*d
,
378 struct device_attribute
*attr
, const char *buf
, size_t count
)
384 sscanf(buf
, "%lX", &tmp
);
385 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
387 val
= (unsigned char)tmp
;
388 spin_lock_irqsave(&event_lock
, flags
);
389 SET_PORT_BITS(TLCLK_REG3
, 0xbf, val
<< 6);
390 spin_unlock_irqrestore(&event_lock
, flags
);
392 return strnlen(buf
, count
);
395 static DEVICE_ATTR(enable_clk3a_output
, (S_IWUSR
|S_IWGRP
), NULL
,
396 store_enable_clk3a_output
);
398 static ssize_t
store_enable_clkb1_output(struct device
*d
,
399 struct device_attribute
*attr
, const char *buf
, size_t count
)
405 sscanf(buf
, "%lX", &tmp
);
406 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
408 val
= (unsigned char)tmp
;
409 spin_lock_irqsave(&event_lock
, flags
);
410 SET_PORT_BITS(TLCLK_REG2
, 0xf7, val
<< 3);
411 spin_unlock_irqrestore(&event_lock
, flags
);
413 return strnlen(buf
, count
);
416 static DEVICE_ATTR(enable_clkb1_output
, (S_IWUSR
|S_IWGRP
), NULL
,
417 store_enable_clkb1_output
);
420 static ssize_t
store_enable_clka1_output(struct device
*d
,
421 struct device_attribute
*attr
, const char *buf
, size_t count
)
427 sscanf(buf
, "%lX", &tmp
);
428 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
430 val
= (unsigned char)tmp
;
431 spin_lock_irqsave(&event_lock
, flags
);
432 SET_PORT_BITS(TLCLK_REG2
, 0xfb, val
<< 2);
433 spin_unlock_irqrestore(&event_lock
, flags
);
435 return strnlen(buf
, count
);
438 static DEVICE_ATTR(enable_clka1_output
, (S_IWUSR
|S_IWGRP
), NULL
,
439 store_enable_clka1_output
);
441 static ssize_t
store_enable_clkb0_output(struct device
*d
,
442 struct device_attribute
*attr
, const char *buf
, size_t count
)
448 sscanf(buf
, "%lX", &tmp
);
449 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
451 val
= (unsigned char)tmp
;
452 spin_lock_irqsave(&event_lock
, flags
);
453 SET_PORT_BITS(TLCLK_REG2
, 0xfd, val
<< 1);
454 spin_unlock_irqrestore(&event_lock
, flags
);
456 return strnlen(buf
, count
);
459 static DEVICE_ATTR(enable_clkb0_output
, (S_IWUSR
|S_IWGRP
), NULL
,
460 store_enable_clkb0_output
);
462 static ssize_t
store_enable_clka0_output(struct device
*d
,
463 struct device_attribute
*attr
, const char *buf
, size_t count
)
469 sscanf(buf
, "%lX", &tmp
);
470 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
472 val
= (unsigned char)tmp
;
473 spin_lock_irqsave(&event_lock
, flags
);
474 SET_PORT_BITS(TLCLK_REG2
, 0xfe, val
);
475 spin_unlock_irqrestore(&event_lock
, flags
);
477 return strnlen(buf
, count
);
480 static DEVICE_ATTR(enable_clka0_output
, (S_IWUSR
|S_IWGRP
), NULL
,
481 store_enable_clka0_output
);
483 static ssize_t
store_select_amcb2_transmit_clock(struct device
*d
,
484 struct device_attribute
*attr
, const char *buf
, size_t count
)
490 sscanf(buf
, "%lX", &tmp
);
491 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
493 val
= (unsigned char)tmp
;
494 spin_lock_irqsave(&event_lock
, flags
);
495 if ((val
== CLK_8kHz
) || (val
== CLK_16_384MHz
)) {
496 SET_PORT_BITS(TLCLK_REG3
, 0xc7, 0x28);
497 SET_PORT_BITS(TLCLK_REG1
, 0xfb, ~val
);
498 } else if (val
>= CLK_8_592MHz
) {
499 SET_PORT_BITS(TLCLK_REG3
, 0xc7, 0x38);
502 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 2);
505 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 0);
508 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 3);
511 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 1);
515 SET_PORT_BITS(TLCLK_REG3
, 0xc7, val
<< 3);
517 spin_unlock_irqrestore(&event_lock
, flags
);
519 return strnlen(buf
, count
);
522 static DEVICE_ATTR(select_amcb2_transmit_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
523 store_select_amcb2_transmit_clock
);
525 static ssize_t
store_select_amcb1_transmit_clock(struct device
*d
,
526 struct device_attribute
*attr
, const char *buf
, size_t count
)
532 sscanf(buf
, "%lX", &tmp
);
533 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
535 val
= (unsigned char)tmp
;
536 spin_lock_irqsave(&event_lock
, flags
);
537 if ((val
== CLK_8kHz
) || (val
== CLK_16_384MHz
)) {
538 SET_PORT_BITS(TLCLK_REG3
, 0xf8, 0x5);
539 SET_PORT_BITS(TLCLK_REG1
, 0xfb, ~val
);
540 } else if (val
>= CLK_8_592MHz
) {
541 SET_PORT_BITS(TLCLK_REG3
, 0xf8, 0x7);
544 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 1);
547 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 0);
550 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 3);
553 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 2);
557 SET_PORT_BITS(TLCLK_REG3
, 0xf8, val
);
558 spin_unlock_irqrestore(&event_lock
, flags
);
560 return strnlen(buf
, count
);
563 static DEVICE_ATTR(select_amcb1_transmit_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
564 store_select_amcb1_transmit_clock
);
566 static ssize_t
store_select_redundant_clock(struct device
*d
,
567 struct device_attribute
*attr
, const char *buf
, size_t count
)
573 sscanf(buf
, "%lX", &tmp
);
574 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
576 val
= (unsigned char)tmp
;
577 spin_lock_irqsave(&event_lock
, flags
);
578 SET_PORT_BITS(TLCLK_REG1
, 0xfe, val
);
579 spin_unlock_irqrestore(&event_lock
, flags
);
581 return strnlen(buf
, count
);
584 static DEVICE_ATTR(select_redundant_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
585 store_select_redundant_clock
);
587 static ssize_t
store_select_ref_frequency(struct device
*d
,
588 struct device_attribute
*attr
, const char *buf
, size_t count
)
594 sscanf(buf
, "%lX", &tmp
);
595 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
597 val
= (unsigned char)tmp
;
598 spin_lock_irqsave(&event_lock
, flags
);
599 SET_PORT_BITS(TLCLK_REG1
, 0xfd, val
);
600 spin_unlock_irqrestore(&event_lock
, flags
);
602 return strnlen(buf
, count
);
605 static DEVICE_ATTR(select_ref_frequency
, (S_IWUSR
|S_IWGRP
), NULL
,
606 store_select_ref_frequency
);
608 static ssize_t
store_filter_select(struct device
*d
,
609 struct device_attribute
*attr
, const char *buf
, size_t count
)
615 sscanf(buf
, "%lX", &tmp
);
616 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
618 val
= (unsigned char)tmp
;
619 spin_lock_irqsave(&event_lock
, flags
);
620 SET_PORT_BITS(TLCLK_REG0
, 0xfb, val
);
621 spin_unlock_irqrestore(&event_lock
, flags
);
623 return strnlen(buf
, count
);
626 static DEVICE_ATTR(filter_select
, (S_IWUSR
|S_IWGRP
), NULL
, store_filter_select
);
628 static ssize_t
store_hardware_switching_mode(struct device
*d
,
629 struct device_attribute
*attr
, const char *buf
, size_t count
)
635 sscanf(buf
, "%lX", &tmp
);
636 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
638 val
= (unsigned char)tmp
;
639 spin_lock_irqsave(&event_lock
, flags
);
640 SET_PORT_BITS(TLCLK_REG0
, 0xbf, val
);
641 spin_unlock_irqrestore(&event_lock
, flags
);
643 return strnlen(buf
, count
);
646 static DEVICE_ATTR(hardware_switching_mode
, (S_IWUSR
|S_IWGRP
), NULL
,
647 store_hardware_switching_mode
);
649 static ssize_t
store_hardware_switching(struct device
*d
,
650 struct device_attribute
*attr
, const char *buf
, size_t count
)
656 sscanf(buf
, "%lX", &tmp
);
657 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
659 val
= (unsigned char)tmp
;
660 spin_lock_irqsave(&event_lock
, flags
);
661 SET_PORT_BITS(TLCLK_REG0
, 0x7f, val
);
662 spin_unlock_irqrestore(&event_lock
, flags
);
664 return strnlen(buf
, count
);
667 static DEVICE_ATTR(hardware_switching
, (S_IWUSR
|S_IWGRP
), NULL
,
668 store_hardware_switching
);
670 static ssize_t
store_refalign (struct device
*d
,
671 struct device_attribute
*attr
, const char *buf
, size_t count
)
676 sscanf(buf
, "%lX", &tmp
);
677 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
678 spin_lock_irqsave(&event_lock
, flags
);
679 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0);
680 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0x08);
681 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0);
682 spin_unlock_irqrestore(&event_lock
, flags
);
684 return strnlen(buf
, count
);
687 static DEVICE_ATTR(refalign
, (S_IWUSR
|S_IWGRP
), NULL
, store_refalign
);
689 static ssize_t
store_mode_select (struct device
*d
,
690 struct device_attribute
*attr
, const char *buf
, size_t count
)
696 sscanf(buf
, "%lX", &tmp
);
697 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
699 val
= (unsigned char)tmp
;
700 spin_lock_irqsave(&event_lock
, flags
);
701 SET_PORT_BITS(TLCLK_REG0
, 0xcf, val
);
702 spin_unlock_irqrestore(&event_lock
, flags
);
704 return strnlen(buf
, count
);
707 static DEVICE_ATTR(mode_select
, (S_IWUSR
|S_IWGRP
), NULL
, store_mode_select
);
709 static ssize_t
store_reset (struct device
*d
,
710 struct device_attribute
*attr
, const char *buf
, size_t count
)
716 sscanf(buf
, "%lX", &tmp
);
717 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
719 val
= (unsigned char)tmp
;
720 spin_lock_irqsave(&event_lock
, flags
);
721 SET_PORT_BITS(TLCLK_REG4
, 0xfd, val
);
722 spin_unlock_irqrestore(&event_lock
, flags
);
724 return strnlen(buf
, count
);
727 static DEVICE_ATTR(reset
, (S_IWUSR
|S_IWGRP
), NULL
, store_reset
);
729 static struct attribute
*tlclk_sysfs_entries
[] = {
730 &dev_attr_current_ref
.attr
,
731 &dev_attr_telclock_version
.attr
,
732 &dev_attr_alarms
.attr
,
733 &dev_attr_received_ref_clk3a
.attr
,
734 &dev_attr_received_ref_clk3b
.attr
,
735 &dev_attr_enable_clk3a_output
.attr
,
736 &dev_attr_enable_clk3b_output
.attr
,
737 &dev_attr_enable_clkb1_output
.attr
,
738 &dev_attr_enable_clka1_output
.attr
,
739 &dev_attr_enable_clkb0_output
.attr
,
740 &dev_attr_enable_clka0_output
.attr
,
741 &dev_attr_select_amcb1_transmit_clock
.attr
,
742 &dev_attr_select_amcb2_transmit_clock
.attr
,
743 &dev_attr_select_redundant_clock
.attr
,
744 &dev_attr_select_ref_frequency
.attr
,
745 &dev_attr_filter_select
.attr
,
746 &dev_attr_hardware_switching_mode
.attr
,
747 &dev_attr_hardware_switching
.attr
,
748 &dev_attr_refalign
.attr
,
749 &dev_attr_mode_select
.attr
,
750 &dev_attr_reset
.attr
,
754 static struct attribute_group tlclk_attribute_group
= {
755 .name
= NULL
, /* put in device directory */
756 .attrs
= tlclk_sysfs_entries
,
759 static struct platform_device
*tlclk_device
;
761 static int __init
tlclk_init(void)
765 ret
= register_chrdev(tlclk_major
, "telco_clock", &tlclk_fops
);
767 printk(KERN_ERR
"tlclk: can't get major %d.\n", tlclk_major
);
771 alarm_events
= kzalloc( sizeof(struct tlclk_alarms
), GFP_KERNEL
);
775 /* Read telecom clock IRQ number (Set by BIOS) */
776 if (!request_region(TLCLK_BASE
, 8, "telco_clock")) {
777 printk(KERN_ERR
"tlclk: request_region 0x%X failed.\n",
782 telclk_interrupt
= (inb(TLCLK_REG7
) & 0x0f);
784 if (0x0F == telclk_interrupt
) { /* not MCPBL0010 ? */
785 printk(KERN_ERR
"telclk_interrup = 0x%x non-mcpbl0010 hw.\n",
791 init_timer(&switchover_timer
);
793 ret
= misc_register(&tlclk_miscdev
);
795 printk(KERN_ERR
"tlclk: misc_register returns %d.\n", ret
);
800 tlclk_device
= platform_device_register_simple("telco_clock",
803 printk(KERN_ERR
"tlclk: platform_device_register failed.\n");
808 ret
= sysfs_create_group(&tlclk_device
->dev
.kobj
,
809 &tlclk_attribute_group
);
811 printk(KERN_ERR
"tlclk: failed to create sysfs device attributes.\n");
812 sysfs_remove_group(&tlclk_device
->dev
.kobj
,
813 &tlclk_attribute_group
);
819 platform_device_unregister(tlclk_device
);
821 misc_deregister(&tlclk_miscdev
);
823 release_region(TLCLK_BASE
, 8);
827 unregister_chrdev(tlclk_major
, "telco_clock");
831 static void __exit
tlclk_cleanup(void)
833 sysfs_remove_group(&tlclk_device
->dev
.kobj
, &tlclk_attribute_group
);
834 platform_device_unregister(tlclk_device
);
835 misc_deregister(&tlclk_miscdev
);
836 unregister_chrdev(tlclk_major
, "telco_clock");
838 release_region(TLCLK_BASE
, 8);
839 del_timer_sync(&switchover_timer
);
844 static void switchover_timeout(unsigned long data
)
847 if ((inb(TLCLK_REG1
) & 0x08) != (data
& 0x08))
848 alarm_events
->switchover_primary
++;
850 if ((inb(TLCLK_REG1
) & 0x08) != (data
& 0x08))
851 alarm_events
->switchover_secondary
++;
854 /* Alarm processing is done, wake up read task */
855 del_timer(&switchover_timer
);
860 static irqreturn_t
tlclk_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
864 spin_lock_irqsave(&event_lock
, flags
);
865 /* Read and clear interrupt events */
866 int_events
= inb(TLCLK_REG6
);
868 /* Primary_Los changed from 0 to 1 ? */
869 if (int_events
& PRI_LOS_01_MASK
) {
870 if (inb(TLCLK_REG2
) & SEC_LOST_MASK
)
871 alarm_events
->lost_clocks
++;
873 alarm_events
->lost_primary_clock
++;
876 /* Primary_Los changed from 1 to 0 ? */
877 if (int_events
& PRI_LOS_10_MASK
) {
878 alarm_events
->primary_clock_back
++;
879 SET_PORT_BITS(TLCLK_REG1
, 0xFE, 1);
881 /* Secondary_Los changed from 0 to 1 ? */
882 if (int_events
& SEC_LOS_01_MASK
) {
883 if (inb(TLCLK_REG2
) & PRI_LOST_MASK
)
884 alarm_events
->lost_clocks
++;
886 alarm_events
->lost_secondary_clock
++;
888 /* Secondary_Los changed from 1 to 0 ? */
889 if (int_events
& SEC_LOS_10_MASK
) {
890 alarm_events
->secondary_clock_back
++;
891 SET_PORT_BITS(TLCLK_REG1
, 0xFE, 0);
893 if (int_events
& HOLDOVER_10_MASK
)
894 alarm_events
->pll_end_holdover
++;
896 if (int_events
& UNLOCK_01_MASK
)
897 alarm_events
->pll_lost_sync
++;
899 if (int_events
& UNLOCK_10_MASK
)
900 alarm_events
->pll_sync
++;
902 /* Holdover changed from 0 to 1 ? */
903 if (int_events
& HOLDOVER_01_MASK
) {
904 alarm_events
->pll_holdover
++;
906 /* TIMEOUT in ~10ms */
907 switchover_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
908 switchover_timer
.data
= inb(TLCLK_REG1
);
909 add_timer(&switchover_timer
);
914 spin_unlock_irqrestore(&event_lock
, flags
);
919 module_init(tlclk_init
);
920 module_exit(tlclk_cleanup
);