2 * Alpha specific irq code.
5 #include <linux/init.h>
6 #include <linux/sched.h>
8 #include <linux/kernel_stat.h>
10 #include <asm/machvec.h>
16 /* Hack minimum IPL during interrupt processing for broken hardware. */
17 #ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
22 * Performance counter hook. A module can override this to
23 * do something useful.
26 dummy_perf(unsigned long vector
, struct pt_regs
*regs
)
29 printk(KERN_CRIT
"Performance counter interrupt!\n");
32 void (*perf_irq
)(unsigned long, struct pt_regs
*) = dummy_perf
;
35 * The main interrupt entry point.
39 do_entInt(unsigned long type
, unsigned long vector
,
40 unsigned long la_ptr
, struct pt_regs
*regs
)
42 struct pt_regs
*old_regs
;
50 printk(KERN_CRIT
"Interprocessor interrupt? "
51 "You must be kidding!\n");
55 old_regs
= set_irq_regs(regs
);
61 smp_percpu_timer_interrupt(regs
);
62 cpu
= smp_processor_id();
63 if (cpu
!= boot_cpuid
) {
64 kstat_cpu(cpu
).irqs
[RTC_IRQ
]++;
72 set_irq_regs(old_regs
);
75 alpha_mv
.machine_check(vector
, la_ptr
, regs
);
78 old_regs
= set_irq_regs(regs
);
79 alpha_mv
.device_interrupt(vector
);
80 set_irq_regs(old_regs
);
83 perf_irq(la_ptr
, regs
);
86 printk(KERN_CRIT
"Hardware intr %ld %lx? Huh?\n",
89 printk(KERN_CRIT
"PC = %016lx PS=%04lx\n", regs
->pc
, regs
->ps
);
93 common_init_isa_dma(void)
95 outb(0, DMA1_RESET_REG
);
96 outb(0, DMA2_RESET_REG
);
97 outb(0, DMA1_CLR_MASK_REG
);
98 outb(0, DMA2_CLR_MASK_REG
);
104 /* Just in case the platform init_irq() causes interrupts/mchecks
105 (as is the case with RAWHIDE, at least). */
112 * machine error checks
114 #define MCHK_K_TPERR 0x0080
115 #define MCHK_K_TCPERR 0x0082
116 #define MCHK_K_HERR 0x0084
117 #define MCHK_K_ECC_C 0x0086
118 #define MCHK_K_ECC_NC 0x0088
119 #define MCHK_K_OS_BUGCHECK 0x008A
120 #define MCHK_K_PAL_BUGCHECK 0x0090
123 struct mcheck_info __mcheck_info
;
127 process_mcheck_info(unsigned long vector
, unsigned long la_ptr
,
128 struct pt_regs
*regs
, const char *machine
,
131 struct el_common
*mchk_header
;
135 * See if the machine check is due to a badaddr() and if so,
139 #ifdef CONFIG_VERBOSE_MCHECK
140 if (alpha_verbose_mcheck
> 1) {
141 printk(KERN_CRIT
"%s machine check %s\n", machine
,
142 expected
? "expected." : "NOT expected!!!");
147 int cpu
= smp_processor_id();
148 mcheck_expected(cpu
) = 0;
149 mcheck_taken(cpu
) = 1;
153 mchk_header
= (struct el_common
*)la_ptr
;
155 printk(KERN_CRIT
"%s machine check: vector=0x%lx pc=0x%lx code=0x%x\n",
156 machine
, vector
, regs
->pc
, mchk_header
->code
);
158 switch (mchk_header
->code
) {
159 /* Machine check reasons. Defined according to PALcode sources. */
160 case 0x80: reason
= "tag parity error"; break;
161 case 0x82: reason
= "tag control parity error"; break;
162 case 0x84: reason
= "generic hard error"; break;
163 case 0x86: reason
= "correctable ECC error"; break;
164 case 0x88: reason
= "uncorrectable ECC error"; break;
165 case 0x8A: reason
= "OS-specific PAL bugcheck"; break;
166 case 0x90: reason
= "callsys in kernel mode"; break;
167 case 0x96: reason
= "i-cache read retryable error"; break;
168 case 0x98: reason
= "processor detected hard error"; break;
170 /* System specific (these are for Alcor, at least): */
171 case 0x202: reason
= "system detected hard error"; break;
172 case 0x203: reason
= "system detected uncorrectable ECC error"; break;
173 case 0x204: reason
= "SIO SERR occurred on PCI bus"; break;
174 case 0x205: reason
= "parity error detected by core logic"; break;
175 case 0x206: reason
= "SIO IOCHK occurred on ISA bus"; break;
176 case 0x207: reason
= "non-existent memory error"; break;
177 case 0x208: reason
= "MCHK_K_DCSR"; break;
178 case 0x209: reason
= "PCI SERR detected"; break;
179 case 0x20b: reason
= "PCI data parity error detected"; break;
180 case 0x20d: reason
= "PCI address parity error detected"; break;
181 case 0x20f: reason
= "PCI master abort error"; break;
182 case 0x211: reason
= "PCI target abort error"; break;
183 case 0x213: reason
= "scatter/gather PTE invalid error"; break;
184 case 0x215: reason
= "flash ROM write error"; break;
185 case 0x217: reason
= "IOA timeout detected"; break;
186 case 0x219: reason
= "IOCHK#, EISA add-in board parity or other catastrophic error"; break;
187 case 0x21b: reason
= "EISA fail-safe timer timeout"; break;
188 case 0x21d: reason
= "EISA bus time-out"; break;
189 case 0x21f: reason
= "EISA software generated NMI"; break;
190 case 0x221: reason
= "unexpected ev5 IRQ[3] interrupt"; break;
191 default: reason
= "unknown"; break;
194 printk(KERN_CRIT
"machine check type: %s%s\n",
195 reason
, mchk_header
->retry
? " (retryable)" : "");
197 dik_show_regs(regs
, NULL
);
199 #ifdef CONFIG_VERBOSE_MCHECK
200 if (alpha_verbose_mcheck
> 1) {
201 /* Dump the logout area to give all info. */
202 unsigned long *ptr
= (unsigned long *)la_ptr
;
204 for (i
= 0; i
< mchk_header
->size
/ sizeof(long); i
+= 2) {
205 printk(KERN_CRIT
" +%8lx %016lx %016lx\n",
206 i
*sizeof(long), ptr
[i
], ptr
[i
+1]);
209 #endif /* CONFIG_VERBOSE_MCHECK */
213 * The special RTC interrupt type. The interrupt itself was
214 * processed by PALcode, and comes in via entInt vector 1.
217 static void rtc_enable_disable(unsigned int irq
) { }
218 static unsigned int rtc_startup(unsigned int irq
) { return 0; }
220 struct irqaction timer_irqaction
= {
221 .handler
= timer_interrupt
,
222 .flags
= IRQF_DISABLED
,
226 static struct hw_interrupt_type rtc_irq_type
= {
228 .startup
= rtc_startup
,
229 .shutdown
= rtc_enable_disable
,
230 .enable
= rtc_enable_disable
,
231 .disable
= rtc_enable_disable
,
232 .ack
= rtc_enable_disable
,
233 .end
= rtc_enable_disable
,
239 irq_desc
[RTC_IRQ
].status
= IRQ_DISABLED
;
240 irq_desc
[RTC_IRQ
].chip
= &rtc_irq_type
;
241 setup_irq(RTC_IRQ
, &timer_irqaction
);
244 /* Dummy irqactions. */
245 struct irqaction isa_cascade_irqaction
= {
246 .handler
= no_action
,
247 .name
= "isa-cascade"
250 struct irqaction timer_cascade_irqaction
= {
251 .handler
= no_action
,
252 .name
= "timer-cascade"
255 struct irqaction halt_switch_irqaction
= {
256 .handler
= no_action
,
257 .name
= "halt-switch"