2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
12 * Assume the maximum number of hot plug slots supported by the system is about
13 * ten. The worstcase is that each of these slots is hot-added with a device,
14 * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
15 * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
16 * as below to ensure at least one message is assigned to each detected MSI/
17 * MSI-X device function.
19 #define NR_HP_RESERVED_VECTORS 20
21 extern int vector_irq
[NR_VECTORS
];
22 extern void (*interrupt
[NR_IRQS
])(void);
23 extern int pci_vector_resources(int last
, int nr_released
);
26 * MSI-X Address Register
28 #define PCI_MSIX_FLAGS_QSIZE 0x7FF
29 #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
30 #define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
31 #define PCI_MSIX_FLAGS_BITMASK (1 << 0)
33 #define PCI_MSIX_ENTRY_SIZE 16
34 #define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
35 #define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
36 #define PCI_MSIX_ENTRY_DATA_OFFSET 8
37 #define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
39 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
40 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
41 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
42 #define msi_data_reg(base, is64bit) \
43 ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
44 #define msi_mask_bits_reg(base, is64bit) \
45 ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
46 #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
47 #define multi_msi_capable(control) \
48 (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
49 #define multi_msi_enable(control, num) \
50 control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
51 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
52 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
53 #define msi_enable(control, num) multi_msi_enable(control, num); \
54 control |= PCI_MSI_FLAGS_ENABLE
56 #define msix_table_offset_reg(base) (base + 0x04)
57 #define msix_pba_offset_reg(base) (base + 0x08)
58 #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
59 #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
60 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
61 #define multi_msix_capable msix_table_size
62 #define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
63 #define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
64 #define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
68 __u8 type
: 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
69 __u8 maskbit
: 1; /* mask-pending bit supported ? */
70 __u8 state
: 1; /* {0: free, 1: busy} */
71 __u8 is_64
: 1; /* Address size: 0=32bit 1=64bit */
72 __u8 entry_nr
; /* specific enabled entry */
73 __u8 default_vector
; /* default pre-assigned vector */
74 __u8 pos
; /* Location of the msi capability */
82 void __iomem
*mask_base
;
86 /* PM save area for MSIX address/data */
87 struct msi_msg msg_save
;