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[ARM] 3215/1: Iomega NAS 100d (MACH_NAS100D) machine support
[linux-2.6.22.y-op.git] / arch / arm / mach-s3c2410 / irq.c
blob66d8c068e940b9436693361f7bdd5dc5f941bc6e
1 /* linux/arch/arm/mach-s3c2410/irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 *
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
24 *
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
27 *
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
30 *
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
33 *
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
36 *
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
39 *
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
42 *
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
45 *
46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
51 */
52
53 #include <linux/init.h>
54 #include <linux/module.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/ptrace.h>
58 #include <linux/sysdev.h>
59
60 #include <asm/hardware.h>
61 #include <asm/irq.h>
62 #include <asm/io.h>
63
64 #include <asm/mach/irq.h>
65
66 #include <asm/arch/regs-irq.h>
67 #include <asm/arch/regs-gpio.h>
68
69 #include "cpu.h"
70 #include "pm.h"
71 #include "irq.h"
72
73 /* wakeup irq control */
74
75 #ifdef CONFIG_PM
76
77 /* state for IRQs over sleep */
78
79 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 *
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
82 */
83
84 unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85 unsigned long s3c_irqwake_intmask = 0xffffffffL;
86 unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87 unsigned long s3c_irqwake_eintmask = 0xffffffffL;
88
89 static int
90 s3c_irq_wake(unsigned int irqno, unsigned int state)
91 {
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
93
94 if (!(s3c_irqwake_intallow & irqbit))
95 return -ENOENT;
96
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
99
100 if (!state)
101 s3c_irqwake_intmask |= irqbit;
102 else
103 s3c_irqwake_intmask &= ~irqbit;
104
105 return 0;
106 }
107
108 static int
109 s3c_irqext_wake(unsigned int irqno, unsigned int state)
110 {
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
112
113 if (!(s3c_irqwake_eintallow & bit))
114 return -ENOENT;
115
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
118
119 if (!state)
120 s3c_irqwake_eintmask |= bit;
121 else
122 s3c_irqwake_eintmask &= ~bit;
123
124 return 0;
125 }
126
127 #else
128 #define s3c_irqext_wake NULL
129 #define s3c_irq_wake NULL
130 #endif
131
132
133 static void
134 s3c_irq_mask(unsigned int irqno)
135 {
136 unsigned long mask;
137
138 irqno -= IRQ_EINT0;
139
140 mask = __raw_readl(S3C2410_INTMSK);
141 mask |= 1UL << irqno;
142 __raw_writel(mask, S3C2410_INTMSK);
143 }
144
145 static inline void
146 s3c_irq_ack(unsigned int irqno)
147 {
148 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
149
150 __raw_writel(bitval, S3C2410_SRCPND);
151 __raw_writel(bitval, S3C2410_INTPND);
152 }
153
154 static inline void
155 s3c_irq_maskack(unsigned int irqno)
156 {
157 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
158 unsigned long mask;
159
160 mask = __raw_readl(S3C2410_INTMSK);
161 __raw_writel(mask|bitval, S3C2410_INTMSK);
162
163 __raw_writel(bitval, S3C2410_SRCPND);
164 __raw_writel(bitval, S3C2410_INTPND);
165 }
166
167
168 static void
169 s3c_irq_unmask(unsigned int irqno)
170 {
171 unsigned long mask;
172
173 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
174 irqdbf2("s3c_irq_unmask %d\n", irqno);
175
176 irqno -= IRQ_EINT0;
177
178 mask = __raw_readl(S3C2410_INTMSK);
179 mask &= ~(1UL << irqno);
180 __raw_writel(mask, S3C2410_INTMSK);
181 }
182
183 struct irqchip s3c_irq_level_chip = {
184 .ack = s3c_irq_maskack,
185 .mask = s3c_irq_mask,
186 .unmask = s3c_irq_unmask,
187 .set_wake = s3c_irq_wake
188 };
189
190 static struct irqchip s3c_irq_chip = {
191 .ack = s3c_irq_ack,
192 .mask = s3c_irq_mask,
193 .unmask = s3c_irq_unmask,
194 .set_wake = s3c_irq_wake
195 };
196
197 /* S3C2410_EINTMASK
198 * S3C2410_EINTPEND
199 */
200
201 static void
202 s3c_irqext_mask(unsigned int irqno)
203 {
204 unsigned long mask;
205
206 irqno -= EXTINT_OFF;
207
208 mask = __raw_readl(S3C2410_EINTMASK);
209 mask |= ( 1UL << irqno);
210 __raw_writel(mask, S3C2410_EINTMASK);
211
212 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
213 /* check to see if all need masking */
214
215 if ((mask & (0xf << 4)) == (0xf << 4)) {
216 /* all masked, mask the parent */
217 s3c_irq_mask(IRQ_EINT4t7);
218 }
219 } else {
220 /* todo: the same check as above for the rest of the irq regs...*/
221
222 }
223 }
224
225 static void
226 s3c_irqext_ack(unsigned int irqno)
227 {
228 unsigned long req;
229 unsigned long bit;
230 unsigned long mask;
231
232 bit = 1UL << (irqno - EXTINT_OFF);
233
234
235 mask = __raw_readl(S3C2410_EINTMASK);
236
237 __raw_writel(bit, S3C2410_EINTPEND);
238
239 req = __raw_readl(S3C2410_EINTPEND);
240 req &= ~mask;
241
242 /* not sure if we should be acking the parent irq... */
243
244 if (irqno <= IRQ_EINT7 ) {
245 if ((req & 0xf0) == 0)
246 s3c_irq_ack(IRQ_EINT4t7);
247 } else {
248 if ((req >> 8) == 0)
249 s3c_irq_ack(IRQ_EINT8t23);
250 }
251 }
252
253 static void
254 s3c_irqext_unmask(unsigned int irqno)
255 {
256 unsigned long mask;
257
258 irqno -= EXTINT_OFF;
259
260 mask = __raw_readl(S3C2410_EINTMASK);
261 mask &= ~( 1UL << irqno);
262 __raw_writel(mask, S3C2410_EINTMASK);
263
264 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
265 }
266
267 static int
268 s3c_irqext_type(unsigned int irq, unsigned int type)
269 {
270 void __iomem *extint_reg;
271 void __iomem *gpcon_reg;
272 unsigned long gpcon_offset, extint_offset;
273 unsigned long newvalue = 0, value;
274
275 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
276 {
277 gpcon_reg = S3C2410_GPFCON;
278 extint_reg = S3C2410_EXTINT0;
279 gpcon_offset = (irq - IRQ_EINT0) * 2;
280 extint_offset = (irq - IRQ_EINT0) * 4;
281 }
282 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
283 {
284 gpcon_reg = S3C2410_GPFCON;
285 extint_reg = S3C2410_EXTINT0;
286 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
287 extint_offset = (irq - (EXTINT_OFF)) * 4;
288 }
289 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
290 {
291 gpcon_reg = S3C2410_GPGCON;
292 extint_reg = S3C2410_EXTINT1;
293 gpcon_offset = (irq - IRQ_EINT8) * 2;
294 extint_offset = (irq - IRQ_EINT8) * 4;
295 }
296 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
297 {
298 gpcon_reg = S3C2410_GPGCON;
299 extint_reg = S3C2410_EXTINT2;
300 gpcon_offset = (irq - IRQ_EINT8) * 2;
301 extint_offset = (irq - IRQ_EINT16) * 4;
302 } else
303 return -1;
304
305 /* Set the GPIO to external interrupt mode */
306 value = __raw_readl(gpcon_reg);
307 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
308 __raw_writel(value, gpcon_reg);
309
310 /* Set the external interrupt to pointed trigger type */
311 switch (type)
312 {
313 case IRQT_NOEDGE:
314 printk(KERN_WARNING "No edge setting!\n");
315 break;
316
317 case IRQT_RISING:
318 newvalue = S3C2410_EXTINT_RISEEDGE;
319 break;
320
321 case IRQT_FALLING:
322 newvalue = S3C2410_EXTINT_FALLEDGE;
323 break;
324
325 case IRQT_BOTHEDGE:
326 newvalue = S3C2410_EXTINT_BOTHEDGE;
327 break;
328
329 case IRQT_LOW:
330 newvalue = S3C2410_EXTINT_LOWLEV;
331 break;
332
333 case IRQT_HIGH:
334 newvalue = S3C2410_EXTINT_HILEV;
335 break;
336
337 default:
338 printk(KERN_ERR "No such irq type %d", type);
339 return -1;
340 }
341
342 value = __raw_readl(extint_reg);
343 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
344 __raw_writel(value, extint_reg);
345
346 return 0;
347 }
348
349 static struct irqchip s3c_irqext_chip = {
350 .mask = s3c_irqext_mask,
351 .unmask = s3c_irqext_unmask,
352 .ack = s3c_irqext_ack,
353 .set_type = s3c_irqext_type,
354 .set_wake = s3c_irqext_wake
355 };
356
357 static struct irqchip s3c_irq_eint0t4 = {
358 .ack = s3c_irq_ack,
359 .mask = s3c_irq_mask,
360 .unmask = s3c_irq_unmask,
361 .set_wake = s3c_irq_wake,
362 .set_type = s3c_irqext_type,
363 };
364
365 /* mask values for the parent registers for each of the interrupt types */
366
367 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
368 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
369 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
370 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
371
372
373 /* UART0 */
374
375 static void
376 s3c_irq_uart0_mask(unsigned int irqno)
377 {
378 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
379 }
380
381 static void
382 s3c_irq_uart0_unmask(unsigned int irqno)
383 {
384 s3c_irqsub_unmask(irqno, INTMSK_UART0);
385 }
386
387 static void
388 s3c_irq_uart0_ack(unsigned int irqno)
389 {
390 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
391 }
392
393 static struct irqchip s3c_irq_uart0 = {
394 .mask = s3c_irq_uart0_mask,
395 .unmask = s3c_irq_uart0_unmask,
396 .ack = s3c_irq_uart0_ack,
397 };
398
399 /* UART1 */
400
401 static void
402 s3c_irq_uart1_mask(unsigned int irqno)
403 {
404 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
405 }
406
407 static void
408 s3c_irq_uart1_unmask(unsigned int irqno)
409 {
410 s3c_irqsub_unmask(irqno, INTMSK_UART1);
411 }
412
413 static void
414 s3c_irq_uart1_ack(unsigned int irqno)
415 {
416 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
417 }
418
419 static struct irqchip s3c_irq_uart1 = {
420 .mask = s3c_irq_uart1_mask,
421 .unmask = s3c_irq_uart1_unmask,
422 .ack = s3c_irq_uart1_ack,
423 };
424
425 /* UART2 */
426
427 static void
428 s3c_irq_uart2_mask(unsigned int irqno)
429 {
430 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
431 }
432
433 static void
434 s3c_irq_uart2_unmask(unsigned int irqno)
435 {
436 s3c_irqsub_unmask(irqno, INTMSK_UART2);
437 }
438
439 static void
440 s3c_irq_uart2_ack(unsigned int irqno)
441 {
442 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
443 }
444
445 static struct irqchip s3c_irq_uart2 = {
446 .mask = s3c_irq_uart2_mask,
447 .unmask = s3c_irq_uart2_unmask,
448 .ack = s3c_irq_uart2_ack,
449 };
450
451 /* ADC and Touchscreen */
452
453 static void
454 s3c_irq_adc_mask(unsigned int irqno)
455 {
456 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
457 }
458
459 static void
460 s3c_irq_adc_unmask(unsigned int irqno)
461 {
462 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
463 }
464
465 static void
466 s3c_irq_adc_ack(unsigned int irqno)
467 {
468 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
469 }
470
471 static struct irqchip s3c_irq_adc = {
472 .mask = s3c_irq_adc_mask,
473 .unmask = s3c_irq_adc_unmask,
474 .ack = s3c_irq_adc_ack,
475 };
476
477 /* irq demux for adc */
478 static void s3c_irq_demux_adc(unsigned int irq,
479 struct irqdesc *desc,
480 struct pt_regs *regs)
481 {
482 unsigned int subsrc, submsk;
483 unsigned int offset = 9;
484 struct irqdesc *mydesc;
485
486 /* read the current pending interrupts, and the mask
487 * for what it is available */
488
489 subsrc = __raw_readl(S3C2410_SUBSRCPND);
490 submsk = __raw_readl(S3C2410_INTSUBMSK);
491
492 subsrc &= ~submsk;
493 subsrc >>= offset;
494 subsrc &= 3;
495
496 if (subsrc != 0) {
497 if (subsrc & 1) {
498 mydesc = irq_desc + IRQ_TC;
499 desc_handle_irq(IRQ_TC, mydesc, regs);
500 }
501 if (subsrc & 2) {
502 mydesc = irq_desc + IRQ_ADC;
503 desc_handle_irq(IRQ_ADC, mydesc, regs);
504 }
505 }
506 }
507
508 static void s3c_irq_demux_uart(unsigned int start,
509 struct pt_regs *regs)
510 {
511 unsigned int subsrc, submsk;
512 unsigned int offset = start - IRQ_S3CUART_RX0;
513 struct irqdesc *desc;
514
515 /* read the current pending interrupts, and the mask
516 * for what it is available */
517
518 subsrc = __raw_readl(S3C2410_SUBSRCPND);
519 submsk = __raw_readl(S3C2410_INTSUBMSK);
520
521 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
522 start, offset, subsrc, submsk);
523
524 subsrc &= ~submsk;
525 subsrc >>= offset;
526 subsrc &= 7;
527
528 if (subsrc != 0) {
529 desc = irq_desc + start;
530
531 if (subsrc & 1)
532 desc_handle_irq(start, desc, regs);
533
534 desc++;
535
536 if (subsrc & 2)
537 desc_handle_irq(start+1, desc, regs);
538
539 desc++;
540
541 if (subsrc & 4)
542 desc_handle_irq(start+2, desc, regs);
543 }
544 }
545
546 /* uart demux entry points */
547
548 static void
549 s3c_irq_demux_uart0(unsigned int irq,
550 struct irqdesc *desc,
551 struct pt_regs *regs)
552 {
553 irq = irq;
554 s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
555 }
556
557 static void
558 s3c_irq_demux_uart1(unsigned int irq,
559 struct irqdesc *desc,
560 struct pt_regs *regs)
561 {
562 irq = irq;
563 s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
564 }
565
566 static void
567 s3c_irq_demux_uart2(unsigned int irq,
568 struct irqdesc *desc,
569 struct pt_regs *regs)
570 {
571 irq = irq;
572 s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
573 }
574
575
576 /* s3c24xx_init_irq
577 *
578 * Initialise S3C2410 IRQ system
579 */
580
581 void __init s3c24xx_init_irq(void)
582 {
583 unsigned long pend;
584 unsigned long last;
585 int irqno;
586 int i;
587
588 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
589
590 /* first, clear all interrupts pending... */
591
592 last = 0;
593 for (i = 0; i < 4; i++) {
594 pend = __raw_readl(S3C2410_EINTPEND);
595
596 if (pend == 0 || pend == last)
597 break;
598
599 __raw_writel(pend, S3C2410_EINTPEND);
600 printk("irq: clearing pending ext status %08x\n", (int)pend);
601 last = pend;
602 }
603
604 last = 0;
605 for (i = 0; i < 4; i++) {
606 pend = __raw_readl(S3C2410_INTPND);
607
608 if (pend == 0 || pend == last)
609 break;
610
611 __raw_writel(pend, S3C2410_SRCPND);
612 __raw_writel(pend, S3C2410_INTPND);
613 printk("irq: clearing pending status %08x\n", (int)pend);
614 last = pend;
615 }
616
617 last = 0;
618 for (i = 0; i < 4; i++) {
619 pend = __raw_readl(S3C2410_SUBSRCPND);
620
621 if (pend == 0 || pend == last)
622 break;
623
624 printk("irq: clearing subpending status %08x\n", (int)pend);
625 __raw_writel(pend, S3C2410_SUBSRCPND);
626 last = pend;
627 }
628
629 /* register the main interrupts */
630
631 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
632
633 for (irqno = IRQ_BATT_FLT; irqno <= IRQ_ADCPARENT; irqno++) {
634 /* set all the s3c2410 internal irqs */
635
636 switch (irqno) {
637 /* deal with the special IRQs (cascaded) */
638
639 case IRQ_UART0:
640 case IRQ_UART1:
641 case IRQ_UART2:
642 case IRQ_ADCPARENT:
643 set_irq_chip(irqno, &s3c_irq_level_chip);
644 set_irq_handler(irqno, do_level_IRQ);
645 break;
646
647 case IRQ_RESERVED6:
648 case IRQ_RESERVED24:
649 /* no IRQ here */
650 break;
651
652 default:
653 //irqdbf("registering irq %d (s3c irq)\n", irqno);
654 set_irq_chip(irqno, &s3c_irq_chip);
655 set_irq_handler(irqno, do_edge_IRQ);
656 set_irq_flags(irqno, IRQF_VALID);
657 }
658 }
659
660 /* setup the cascade irq handlers */
661
662 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
663 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
664 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
665 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
666
667
668 /* external interrupts */
669
670 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
671 irqdbf("registering irq %d (ext int)\n", irqno);
672 set_irq_chip(irqno, &s3c_irq_eint0t4);
673 set_irq_handler(irqno, do_edge_IRQ);
674 set_irq_flags(irqno, IRQF_VALID);
675 }
676
677 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
678 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
679 set_irq_chip(irqno, &s3c_irqext_chip);
680 set_irq_handler(irqno, do_edge_IRQ);
681 set_irq_flags(irqno, IRQF_VALID);
682 }
683
684 /* register the uart interrupts */
685
686 irqdbf("s3c2410: registering external interrupts\n");
687
688 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
689 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
690 set_irq_chip(irqno, &s3c_irq_uart0);
691 set_irq_handler(irqno, do_level_IRQ);
692 set_irq_flags(irqno, IRQF_VALID);
693 }
694
695 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
696 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
697 set_irq_chip(irqno, &s3c_irq_uart1);
698 set_irq_handler(irqno, do_level_IRQ);
699 set_irq_flags(irqno, IRQF_VALID);
700 }
701
702 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
703 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
704 set_irq_chip(irqno, &s3c_irq_uart2);
705 set_irq_handler(irqno, do_level_IRQ);
706 set_irq_flags(irqno, IRQF_VALID);
707 }
708
709 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
710 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
711 set_irq_chip(irqno, &s3c_irq_adc);
712 set_irq_handler(irqno, do_edge_IRQ);
713 set_irq_flags(irqno, IRQF_VALID);
714 }
715
716 irqdbf("s3c2410: registered interrupt handlers\n");
717 }
linux v2.6.22.y-op