2 * Cell Internal Interrupt Controller
4 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
7 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
9 * Author: Arnd Bergmann <arndb@de.ibm.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
27 * vs node numbers in the setup code
28 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
29 * a non-active node to the active node)
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/module.h>
35 #include <linux/percpu.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
40 #include <asm/pgtable.h>
42 #include <asm/ptrace.h>
43 #include <asm/machdep.h>
45 #include "interrupt.h"
49 struct cbe_iic_thread_regs __iomem
*regs
;
53 struct device_node
*node
;
56 static DEFINE_PER_CPU(struct iic
, iic
);
57 #define IIC_NODE_COUNT 2
58 static struct irq_host
*iic_host
;
60 /* Convert between "pending" bits and hw irq number */
61 static irq_hw_number_t
iic_pending_to_hwnum(struct cbe_iic_pending_bits bits
)
63 unsigned char unit
= bits
.source
& 0xf;
64 unsigned char node
= bits
.source
>> 4;
65 unsigned char class = bits
.class & 3;
68 if (bits
.flags
& CBE_IIC_IRQ_IPI
)
69 return IIC_IRQ_TYPE_IPI
| (bits
.prio
>> 4);
71 return (node
<< IIC_IRQ_NODE_SHIFT
) | (class << 4) | unit
;
74 static void iic_mask(unsigned int irq
)
78 static void iic_unmask(unsigned int irq
)
82 static void iic_eoi(unsigned int irq
)
84 struct iic
*iic
= &__get_cpu_var(iic
);
85 out_be64(&iic
->regs
->prio
, iic
->eoi_stack
[--iic
->eoi_ptr
]);
86 BUG_ON(iic
->eoi_ptr
< 0);
89 static struct irq_chip iic_chip
= {
90 .typename
= " CELL-IIC ",
97 static void iic_ioexc_eoi(unsigned int irq
)
101 static void iic_ioexc_cascade(unsigned int irq
, struct irq_desc
*desc
,
102 struct pt_regs
*regs
)
104 struct cbe_iic_regs
*node_iic
= desc
->handler_data
;
105 unsigned int base
= (irq
& 0xffffff00) | IIC_IRQ_TYPE_IOEXC
;
106 unsigned long bits
, ack
;
110 bits
= in_be64(&node_iic
->iic_is
);
113 /* pre-ack edge interrupts */
114 ack
= bits
& IIC_ISR_EDGE_MASK
;
116 out_be64(&node_iic
->iic_is
, ack
);
118 for (cascade
= 63; cascade
>= 0; cascade
--)
119 if (bits
& (0x8000000000000000UL
>> cascade
)) {
121 irq_linear_revmap(iic_host
,
124 generic_handle_irq(cirq
, regs
);
126 /* post-ack level interrupts */
127 ack
= bits
& ~IIC_ISR_EDGE_MASK
;
129 out_be64(&node_iic
->iic_is
, ack
);
131 desc
->chip
->eoi(irq
);
135 static struct irq_chip iic_ioexc_chip
= {
136 .typename
= " CELL-IOEX",
138 .unmask
= iic_unmask
,
139 .eoi
= iic_ioexc_eoi
,
142 /* Get an IRQ number from the pending state register of the IIC */
143 static unsigned int iic_get_irq(struct pt_regs
*regs
)
145 struct cbe_iic_pending_bits pending
;
149 iic
= &__get_cpu_var(iic
);
150 *(unsigned long *) &pending
=
151 in_be64((unsigned long __iomem
*) &iic
->regs
->pending_destr
);
152 if (!(pending
.flags
& CBE_IIC_IRQ_VALID
))
154 virq
= irq_linear_revmap(iic_host
, iic_pending_to_hwnum(pending
));
157 iic
->eoi_stack
[++iic
->eoi_ptr
] = pending
.prio
;
158 BUG_ON(iic
->eoi_ptr
> 15);
164 /* Use the highest interrupt priorities for IPI */
165 static inline int iic_ipi_to_irq(int ipi
)
167 return IIC_IRQ_TYPE_IPI
+ 0xf - ipi
;
170 void iic_setup_cpu(void)
172 out_be64(&__get_cpu_var(iic
).regs
->prio
, 0xff);
175 void iic_cause_IPI(int cpu
, int mesg
)
177 out_be64(&per_cpu(iic
, cpu
).regs
->generate
, (0xf - mesg
) << 4);
180 u8
iic_get_target_id(int cpu
)
182 return per_cpu(iic
, cpu
).target_id
;
184 EXPORT_SYMBOL_GPL(iic_get_target_id
);
186 struct irq_host
*iic_get_irq_host(int node
)
190 EXPORT_SYMBOL_GPL(iic_get_irq_host
);
193 static irqreturn_t
iic_ipi_action(int irq
, void *dev_id
, struct pt_regs
*regs
)
195 int ipi
= (int)(long)dev_id
;
197 smp_message_recv(ipi
, regs
);
201 static void iic_request_ipi(int ipi
, const char *name
)
205 virq
= irq_create_mapping(iic_host
, iic_ipi_to_irq(ipi
));
206 if (virq
== NO_IRQ
) {
208 "iic: failed to map IPI %s\n", name
);
211 if (request_irq(virq
, iic_ipi_action
, IRQF_DISABLED
, name
,
214 "iic: failed to request IPI %s\n", name
);
217 void iic_request_IPIs(void)
219 iic_request_ipi(PPC_MSG_CALL_FUNCTION
, "IPI-call");
220 iic_request_ipi(PPC_MSG_RESCHEDULE
, "IPI-resched");
221 #ifdef CONFIG_DEBUGGER
222 iic_request_ipi(PPC_MSG_DEBUGGER_BREAK
, "IPI-debug");
223 #endif /* CONFIG_DEBUGGER */
226 #endif /* CONFIG_SMP */
229 static int iic_host_match(struct irq_host
*h
, struct device_node
*node
)
231 return device_is_compatible(node
,
232 "IBM,CBEA-Internal-Interrupt-Controller");
235 static int iic_host_map(struct irq_host
*h
, unsigned int virq
,
238 switch (hw
& IIC_IRQ_TYPE_MASK
) {
239 case IIC_IRQ_TYPE_IPI
:
240 set_irq_chip_and_handler(virq
, &iic_chip
, handle_percpu_irq
);
242 case IIC_IRQ_TYPE_IOEXC
:
243 set_irq_chip_and_handler(virq
, &iic_ioexc_chip
,
247 set_irq_chip_and_handler(virq
, &iic_chip
, handle_fasteoi_irq
);
252 static int iic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
253 u32
*intspec
, unsigned int intsize
,
254 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
257 unsigned int node
, ext
, unit
, class;
260 if (!device_is_compatible(ct
,
261 "IBM,CBEA-Internal-Interrupt-Controller"))
265 val
= get_property(ct
, "#interrupt-cells", NULL
);
266 if (val
== NULL
|| *val
!= 1)
269 node
= intspec
[0] >> 24;
270 ext
= (intspec
[0] >> 16) & 0xff;
271 class = (intspec
[0] >> 8) & 0xff;
272 unit
= intspec
[0] & 0xff;
274 /* Check if node is in supported range */
278 /* Build up interrupt number, special case for IO exceptions */
279 *out_hwirq
= (node
<< IIC_IRQ_NODE_SHIFT
);
280 if (unit
== IIC_UNIT_IIC
&& class == 1)
281 *out_hwirq
|= IIC_IRQ_TYPE_IOEXC
| ext
;
283 *out_hwirq
|= IIC_IRQ_TYPE_NORMAL
|
284 (class << IIC_IRQ_CLASS_SHIFT
) | unit
;
286 /* Dummy flags, ignored by iic code */
287 *out_flags
= IRQ_TYPE_EDGE_RISING
;
292 static struct irq_host_ops iic_host_ops
= {
293 .match
= iic_host_match
,
295 .xlate
= iic_host_xlate
,
298 static void __init
init_one_iic(unsigned int hw_cpu
, unsigned long addr
,
299 struct device_node
*node
)
301 /* XXX FIXME: should locate the linux CPU number from the HW cpu
302 * number properly. We are lucky for now
304 struct iic
*iic
= &per_cpu(iic
, hw_cpu
);
306 iic
->regs
= ioremap(addr
, sizeof(struct cbe_iic_thread_regs
));
307 BUG_ON(iic
->regs
== NULL
);
309 iic
->target_id
= ((hw_cpu
& 2) << 3) | ((hw_cpu
& 1) ? 0xf : 0xe);
310 iic
->eoi_stack
[0] = 0xff;
311 iic
->node
= of_node_get(node
);
312 out_be64(&iic
->regs
->prio
, 0);
314 printk(KERN_INFO
"IIC for CPU %d target id 0x%x : %s\n",
315 hw_cpu
, iic
->target_id
, node
->full_name
);
318 static int __init
setup_iic(void)
320 struct device_node
*dn
;
321 struct resource r0
, r1
;
322 unsigned int node
, cascade
, found
= 0;
323 struct cbe_iic_regs
*node_iic
;
327 (dn
= of_find_node_by_name(dn
,"interrupt-controller")) != NULL
;) {
328 if (!device_is_compatible(dn
,
329 "IBM,CBEA-Internal-Interrupt-Controller"))
331 np
= get_property(dn
, "ibm,interrupt-server-ranges", NULL
);
333 printk(KERN_WARNING
"IIC: CPU association not found\n");
337 if (of_address_to_resource(dn
, 0, &r0
) ||
338 of_address_to_resource(dn
, 1, &r1
)) {
339 printk(KERN_WARNING
"IIC: Can't resolve addresses\n");
344 init_one_iic(np
[0], r0
.start
, dn
);
345 init_one_iic(np
[1], r1
.start
, dn
);
347 /* Setup cascade for IO exceptions. XXX cleanup tricks to get
349 * Note that we configure the IIC_IRR here with a hard coded
350 * priority of 1. We might want to improve that later.
353 node_iic
= cbe_get_cpu_iic_regs(np
[0]);
354 cascade
= node
<< IIC_IRQ_NODE_SHIFT
;
355 cascade
|= 1 << IIC_IRQ_CLASS_SHIFT
;
356 cascade
|= IIC_UNIT_IIC
;
357 cascade
= irq_create_mapping(iic_host
, cascade
);
358 if (cascade
== NO_IRQ
)
360 set_irq_data(cascade
, node_iic
);
361 set_irq_chained_handler(cascade
, iic_ioexc_cascade
);
362 out_be64(&node_iic
->iic_ir
,
363 (1 << 12) /* priority */ |
364 (node
<< 4) /* dest node */ |
365 IIC_UNIT_THREAD_0
/* route them to thread 0 */);
366 /* Flush pending (make sure it triggers if there is
369 out_be64(&node_iic
->iic_is
, 0xfffffffffffffffful
);
378 void __init
iic_init_IRQ(void)
380 /* Setup an irq host data structure */
381 iic_host
= irq_alloc_host(IRQ_HOST_MAP_LINEAR
, IIC_SOURCE_COUNT
,
382 &iic_host_ops
, IIC_IRQ_INVALID
);
383 BUG_ON(iic_host
== NULL
);
384 irq_set_default_host(iic_host
);
386 /* Discover and initialize iics */
388 panic("IIC: Failed to initialize !\n");
390 /* Set master interrupt handling function */
391 ppc_md
.get_irq
= iic_get_irq
;
393 /* Enable on current CPU */